Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46272 )
Change subject: soc/intel/skl + cpu/intel/common: move AES-NI locking to common cpu code
......................................................................
Patch Set 4:
(2 comments)
https://review.coreboot.org/c/coreboot/+/46272/4/src/include/cpu/intel/msr.h
File src/include/cpu/intel/msr.h:
https://review.coreboot.org/c/coreboot/+/46272/4/src/include/cpu/intel/msr.…
PS4, Line 8: #define MSR_FEATURE_CONFIG 0x13c
> I meant the one that is close to this change and was used in the moved […]
got it, done locally; will be pushed with the next patchset
https://review.coreboot.org/c/coreboot/+/46272/4/src/include/cpu/intel/msr.…
PS4, Line 9: #define AESNI_LOCK_BIT 0
> I would replace msr_set_bit() with _unset and _set versions like we have […]
sounds like a plan
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Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46120 )
Change subject: mb/google/poppy/variant/atlas: Reset bluetooth on boot
......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/46120/2/src/mainboard/google/poppy…
File src/mainboard/google/poppy/variants/atlas/gpio.c:
https://review.coreboot.org/c/coreboot/+/46120/2/src/mainboard/google/poppy…
PS2, Line 335: early_gpio_table
Are you planning to requal a new RO for this change?
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Hello build bot (Jenkins), Nico Huber, Furquan Shaikh, Subrata Banik, Aamir Bohra, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45957
to look at the new patch set (#24).
Change subject: [UNTESTED] soc/intel/{icl,tgl,jsl,ehl,adl}: set PM ACPI timer state from Kconfig
......................................................................
[UNTESTED] soc/intel/{icl,tgl,jsl,ehl,adl}: set PM ACPI timer state from Kconfig
Set the FSP option for PM ACPI timer enablement from the Kconfig
option, to be able to disable the timer for power savings.
Change-Id: Iaf1eee9297034b29b7250f6c752e6f7f52b4b908
Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de>
---
M src/soc/intel/alderlake/fsp_params.c
M src/soc/intel/elkhartlake/fsp_params.c
M src/soc/intel/icelake/fsp_params.c
M src/soc/intel/jasperlake/fsp_params.c
M src/soc/intel/tigerlake/fsp_params.c
5 files changed, 10 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/45957/24
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Hello build bot (Jenkins), Nico Huber, Furquan Shaikh, Subrata Banik, Aamir Bohra, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
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Change subject: soc/intel/common: add Kconfig to enable/disable the ACPI PM timer
......................................................................
soc/intel/common: add Kconfig to enable/disable the ACPI PM timer
Currently, the ACPI PM timer state gets set in devicetree by the option
PmTimerDisabled. However, it is not board design dependent. Thus, add a
user-selectable Kconfig option.
Also, make the TCO SMI option depend on ACPI PM timer, since it won't
work without it.
The Kconfig option depends on CTC (Common Timer Copy), which the SoC has
to support to do PM ACPI timer emulation.
This new Kconfig gets used in the follow-up commits of this series.
Note: On Apollolake USE_PM_ACPI_TIMER gets selected statically to avoid
confing the user in menuconfig, where the option is shown due to using
the common code for PM Timer emulation. Currently, there is no FSP
option and no coreboot code to disable the PM ACPI Timer and it is
unknown if that is desireable on that platform.
Change-Id: I7f607f277eb14f84a7370ffb25a13226e7ccc917
Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de>
---
M src/soc/intel/apollolake/Kconfig
M src/soc/intel/common/block/pmc/Kconfig
M src/soc/intel/common/block/smm/Kconfig
3 files changed, 18 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/45952/19
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I'd like you to reexamine a change. Please visit
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Change subject: soc/intel: deduplicate ACPI timer emulation
......................................................................
soc/intel: deduplicate ACPI timer emulation
The code for enabling ACPI timer emulation is the same for the SoCs
APL, SKL, CNL, ICL, TGL, JSL and EHL. Deduplicate it by moving it to
common code.
Note: The ACPI timer emulation can only be used by SoCs with microcode
supporting CTC (Common Timer Copy) / ACPI timer emulation.
Change-Id: Ied4b312b6d53e80e71c55f4d1ca78a8cb2799793
Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de>
---
M src/soc/intel/alderlake/cpu.c
M src/soc/intel/apollolake/Makefile.inc
M src/soc/intel/apollolake/include/soc/pm.h
M src/soc/intel/apollolake/pmutil.c
M src/soc/intel/cannonlake/cpu.c
M src/soc/intel/common/block/cpu/Makefile.inc
A src/soc/intel/common/block/cpu/pm_timer_emulation.c
M src/soc/intel/common/block/include/intelblocks/cpulib.h
M src/soc/intel/elkhartlake/cpu.c
M src/soc/intel/icelake/cpu.c
M src/soc/intel/jasperlake/cpu.c
M src/soc/intel/skylake/cpu.c
M src/soc/intel/tigerlake/cpu.c
13 files changed, 41 insertions(+), 169 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/45951/17
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I'd like you to reexamine a change. Please visit
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Change subject: soc/intel: convert XTAL frequency constant to Kconfig
......................................................................
soc/intel: convert XTAL frequency constant to Kconfig
This converts the constant for the XTAL frequency to a Kconfig option.
Change-Id: I1382dd274eeb9cb748f94c34f5d9a83880624c18
Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de>
---
M src/soc/intel/alderlake/Kconfig
M src/soc/intel/alderlake/cpu.c
M src/soc/intel/alderlake/include/soc/cpu.h
M src/soc/intel/apollolake/Kconfig
M src/soc/intel/apollolake/include/soc/cpu.h
M src/soc/intel/apollolake/pmutil.c
M src/soc/intel/cannonlake/Kconfig
M src/soc/intel/cannonlake/cpu.c
M src/soc/intel/cannonlake/include/soc/cpu.h
M src/soc/intel/common/block/cpu/Kconfig
M src/soc/intel/elkhartlake/Kconfig
M src/soc/intel/elkhartlake/cpu.c
M src/soc/intel/elkhartlake/include/soc/cpu.h
M src/soc/intel/icelake/Kconfig
M src/soc/intel/icelake/cpu.c
M src/soc/intel/icelake/include/soc/cpu.h
M src/soc/intel/jasperlake/Kconfig
M src/soc/intel/jasperlake/cpu.c
M src/soc/intel/jasperlake/include/soc/cpu.h
M src/soc/intel/skylake/Kconfig
M src/soc/intel/skylake/cpu.c
M src/soc/intel/skylake/include/soc/cpu.h
M src/soc/intel/tigerlake/Kconfig
M src/soc/intel/tigerlake/cpu.c
M src/soc/intel/tigerlake/include/soc/cpu.h
25 files changed, 85 insertions(+), 63 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/46018/10
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I'd like you to reexamine a change. Please visit
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to look at the new patch set (#8).
Change subject: soc/intel/common: add Kconfig for PM Timer emulation support
......................................................................
soc/intel/common: add Kconfig for PM Timer emulation support
Add a Kconfig for SoCs to indicate PM ACPI timer emulation support and
select it by the appropriate SoCs.
This Kconfig gets used in the follow-up changes.
Change-Id: I6ded79221a01655f298ff92b8bd2afabd1d2a3ff
Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de>
---
M src/soc/intel/alderlake/Kconfig
M src/soc/intel/apollolake/Kconfig
M src/soc/intel/cannonlake/Kconfig
M src/soc/intel/common/block/cpu/Kconfig
M src/soc/intel/elkhartlake/Kconfig
M src/soc/intel/icelake/Kconfig
M src/soc/intel/jasperlake/Kconfig
M src/soc/intel/skylake/Kconfig
M src/soc/intel/tigerlake/Kconfig
9 files changed, 16 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/46017/8
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Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45901 )
Change subject: soc/intel/jasperlake: Set the GpioOverride configuration
......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45901/6/src/soc/intel/jasperlake/r…
File src/soc/intel/jasperlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/45901/6/src/soc/intel/jasperlake/r…
PS6, Line 120: /* Set GpioOverride */
I think it would be helpful to have a comment that explains what setting this UPD does.
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Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46040 )
Change subject: drivers/wifi/generic: Do not generate SAR tables for non-Intel WiFi
......................................................................
drivers/wifi/generic: Do not generate SAR tables for non-Intel WiFi
CBFS SAR and SAR tables in ACPI are currently supported only by Intel
WiFi devices. This change adds a check in `emit_sar_acpi_structures()`
to ensure that the PCI vendor for the device is Intel before
generating the SAR tables.
BUG=b:169802515
BRANCH=zork
Change-Id: Ibff437893a61ac9557cff243a70230f101089834
Signed-off-by: Furquan Shaikh <furquan(a)google.com>
---
M src/drivers/wifi/generic/generic.c
1 file changed, 6 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/46040/1
diff --git a/src/drivers/wifi/generic/generic.c b/src/drivers/wifi/generic/generic.c
index 48201fc..c7a32bd 100644
--- a/src/drivers/wifi/generic/generic.c
+++ b/src/drivers/wifi/generic/generic.c
@@ -44,12 +44,16 @@
return -1;
}
-static void emit_sar_acpi_structures(void)
+static void emit_sar_acpi_structures(const struct device *dev)
{
int i, j, package_size;
struct wifi_sar_limits sar_limits;
struct wifi_sar_delta_table *wgds;
+ /* CBFS SAR and SAR ACPI tables are currently used only by Intel WiFi devices. */
+ if (dev->vendor != PCI_VENDOR_ID_INTEL)
+ return;
+
/* Retrieve the sar limits data */
if (get_wifi_sar_limits(&sar_limits) < 0) {
printk(BIOS_ERR, "Error: failed from getting SAR limits!\n");
@@ -217,7 +221,7 @@
/* Fill Wifi sar related ACPI structures */
if (CONFIG(USE_SAR))
- emit_sar_acpi_structures();
+ emit_sar_acpi_structures(dev);
acpigen_pop_len(); /* Device */
acpigen_pop_len(); /* Scope */
--
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