coreboot-gerrit October 2020

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Change in coreboot[master]: soc/intel/common/block: Add common support for USB4/Thunderbolt
by Duncan Laurie (Code Review) 14 Oct '20

14 Oct '20

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44916 ) Change subject: soc/intel/common/block: Add common support for USB4/Thunderbolt ...................................................................... soc/intel/common/block: Add common support for USB4/Thunderbolt This common intel driver will add the requried ACPI _DSD entries for USB4/Thunderbolt ports that are enabled into the SSDT instead of using hardcoded values in the DSDT. Signed-off-by: Duncan Laurie <dlaurie(a)google.com> Change-Id: Ic4a58202d4569cf092ea21a4a83a3af6c42ce9d0 --- A src/soc/intel/common/block/usb4/Kconfig A src/soc/intel/common/block/usb4/Makefile.inc A src/soc/intel/common/block/usb4/usb4.c 3 files changed, 61 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/44916/1 diff --git a/src/soc/intel/common/block/usb4/Kconfig b/src/soc/intel/common/block/usb4/Kconfig new file mode 100644 index 0000000..f588b27 --- /dev/null +++ b/src/soc/intel/common/block/usb4/Kconfig @@ -0,0 +1,4 @@ +config SOC_INTEL_COMMON_BLOCK_USB4 + bool + help + Intel Processor common USB4/Thunderbolt support diff --git a/src/soc/intel/common/block/usb4/Makefile.inc b/src/soc/intel/common/block/usb4/Makefile.inc new file mode 100644 index 0000000..7dad4ba --- /dev/null +++ b/src/soc/intel/common/block/usb4/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_USB4) += usb4.c diff --git a/src/soc/intel/common/block/usb4/usb4.c b/src/soc/intel/common/block/usb4/usb4.c new file mode 100644 index 0000000..b33d774 --- /dev/null +++ b/src/soc/intel/common/block/usb4/usb4.c @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpigen.h> +#include <acpi/acpi_device.h> +#include <device/pci.h> +#include <device/pci_def.h> +#include <device/pci_ids.h> + +#define INTEL_TBT_IMR_VALID_UUID "C44D002F-69F9-4E7D-A904-A7BAABDF43F7" +#define INTEL_TBT_WAKE_SUPPORTED_UUID "6C501103-C189-4296-BA72-9BF5A26EBE5D" + +static void usb4_fill_ssdt(const struct device *dev) +{ + struct acpi_dp *dsd, *pkg; + + if (!dev->enabled) + return; + + acpigen_write_scope(acpi_device_path(dev)); + + dsd = acpi_dp_new_table("_DSD"); + + /* Indicate that device has valid IMR. */ + pkg = acpi_dp_new_table(INTEL_TBT_IMR_VALID_UUID); + acpi_dp_add_integer(pkg, "IMR_VALID", 1); + acpi_dp_add_package(dsd, pkg); + + /* Indicate that device is wake capable. */ + pkg = acpi_dp_new_table(INTEL_TBT_WAKE_SUPPORTED_UUID); + acpi_dp_add_integer(pkg, "WAKE_SUPPORTED", 1); + + acpi_dp_add_package(dsd, pkg); + acpi_dp_write(dsd); + + acpigen_pop_len(); /* Scope */ +} + +static struct device_operations device_ops = { + .read_resources = pci_bus_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_bus_enable_resources, + .scan_bus = scan_static_bus, + .acpi_fill_ssdt = usb4_fill_ssdt, +}; + +static const unsigned short pcie_device_ids[] = { + PCI_DEVICE_ID_INTEL_TGL_TBT_DMA0, + PCI_DEVICE_ID_INTEL_TGL_TBT_DMA1, + 0 +}; + +static const struct pci_driver intel_usb4_driver __pci_driver = { + .ops = &device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = pcie_device_ids, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/44916 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic4a58202d4569cf092ea21a4a83a3af6c42ce9d0 Gerrit-Change-Number: 44916 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common: Add PCI driver for USB4 ports
by Tim Wawrzynczak (Code Review) 14 Oct '20

14 Oct '20

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46141 ) Change subject: soc/intel/common: Add PCI driver for USB4 ports ...................................................................... soc/intel/common: Add PCI driver for USB4 ports In order to enable SSDT generation for Intel USB4 ports, a minimal PCI driver is required. Change-Id: Ib9da051307b883eb99e500114378c9fd842ffc92 Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- A src/soc/intel/common/block/usb4/Kconfig A src/soc/intel/common/block/usb4/Makefile.inc A src/soc/intel/common/block/usb4/usb4.c 3 files changed, 32 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/46141/1 diff --git a/src/soc/intel/common/block/usb4/Kconfig b/src/soc/intel/common/block/usb4/Kconfig new file mode 100644 index 0000000..f68c5a7 --- /dev/null +++ b/src/soc/intel/common/block/usb4/Kconfig @@ -0,0 +1,6 @@ +config SOC_INTEL_COMMON_BLOCK_USB4 + bool + default n + help + Minimal PCI Driver for enabling SSDT generation for Intel + Thunderbolt/USB4 ports. diff --git a/src/soc/intel/common/block/usb4/Makefile.inc b/src/soc/intel/common/block/usb4/Makefile.inc new file mode 100644 index 0000000..7dad4ba --- /dev/null +++ b/src/soc/intel/common/block/usb4/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_USB4) += usb4.c diff --git a/src/soc/intel/common/block/usb4/usb4.c b/src/soc/intel/common/block/usb4/usb4.c new file mode 100644 index 0000000..3fc1159 --- /dev/null +++ b/src/soc/intel/common/block/usb4/usb4.c @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> + +static const unsigned short pci_device_ids[] = { + PCI_DEVICE_ID_INTEL_TGL_TBT_DMA0, + PCI_DEVICE_ID_INTEL_TGL_TBT_DMA1, + 0 +}; + +static struct device_operations usb4_dev_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .scan_bus = scan_generic_bus, + .ops_pci = &pci_dev_ops_pci, +}; + +static const struct pci_driver usb4_driver __pci_driver = { + .ops = &usb4_dev_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = pci_device_ids, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/46141 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib9da051307b883eb99e500114378c9fd842ffc92 Gerrit-Change-Number: 46141 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/puff/var/dooly: Enable Ambient Light Sensor (ALS)
by Tony Huang (Code Review) 14 Oct '20

14 Oct '20

Tony Huang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46061 ) Change subject: mb/google/puff/var/dooly: Enable Ambient Light Sensor (ALS) ...................................................................... mb/google/puff/var/dooly: Enable Ambient Light Sensor (ALS) Enable ALS ACPI devices for dooly. BUG=b:168426118 BRANCH=puff TEST=Ensure that ALS devices are enabled in ACPI tables. Change-Id: Idd44d6ae1e7b62939fdfc3a0ab01924d2c1714aa Signed-off-by: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> --- M src/mainboard/google/hatch/variants/dooly/include/variant/ec.h 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/46061/1 diff --git a/src/mainboard/google/hatch/variants/dooly/include/variant/ec.h b/src/mainboard/google/hatch/variants/dooly/include/variant/ec.h index 59fb378..7d280c6 100644 --- a/src/mainboard/google/hatch/variants/dooly/include/variant/ec.h +++ b/src/mainboard/google/hatch/variants/dooly/include/variant/ec.h @@ -5,4 +5,7 @@ #include <puff/ec.h> +/* Enable EC backed ALS device in ACPI */ +#define EC_ENABLE_ALS_DEVICE + #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/46061 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idd44d6ae1e7b62939fdfc3a0ab01924d2c1714aa Gerrit-Change-Number: 46061 Gerrit-PatchSet: 1 Gerrit-Owner: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/{cnl,icl,tgl,jsl,ehl,adl}/acpi: generate CPPC entries
by Michael Niewöhner (Code Review) 14 Oct '20

14 Oct '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45536 ) Change subject: soc/intel/{cnl,icl,tgl,jsl,ehl,adl}/acpi: generate CPPC entries ...................................................................... Patch Set 10: (1 comment) https://review.coreboot.org/c/coreboot/+/45536/10/src/soc/intel/alderlake/a… File src/soc/intel/alderlake/acpi.c: https://review.coreboot.org/c/coreboot/+/45536/10/src/soc/intel/alderlake/a… PS10, Line 162: generate_cppc_entries(core_id); > > Why jump through so many hoops here? soc calls generate_cpu_entries(), calls […] Well, all that jumping was not my idea \o/ that's what sock/intel/common/acpi does already in other cases as well :S -- To view, visit https://review.coreboot.org/c/coreboot/+/45536 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I40d47d18a35002bc9ec55473e94277d89fc5797e Gerrit-Change-Number: 45536 Gerrit-PatchSet: 10 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Elyes HAOUAS Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Tue, 13 Oct 2020 23:32:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/block/acpi: add code for CPPC entries generation
by Michael Niewöhner (Code Review) 14 Oct '20

14 Oct '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45535 ) Change subject: soc/intel/common/block/acpi: add code for CPPC entries generation ...................................................................... Patch Set 8: (2 comments) https://review.coreboot.org/c/coreboot/+/45535/8/src/soc/intel/common/block… File src/soc/intel/common/block/acpi/acpi.c: https://review.coreboot.org/c/coreboot/+/45535/8/src/soc/intel/common/block… PS8, Line 370: core > Is this `virtual core` aka. thread? Otherwise it would seem that this is […] Well, that naming scheme is a bit... unclear, but that's what common/block/acpi already does. We can clarify that ofc. TBH I'm not yet convinced that the loop generate_cpu_entries is correct at all. Anyway, the global CPPC entry shall get added once per package only. The (logical) cores each get a _CPC method returning that CPPC (GCPC in cb) entry. `core` is the `core_id` from generate_cpu_entries() which *should* be the APIC id (total number of cores for the loop comes from dev_count_cpu()). https://review.coreboot.org/c/coreboot/+/45535/8/src/soc/intel/common/block… PS8, Line 372: /* version 2 */ > Is the comment really necessary? If you want to name arguments, you could pass […] yay, copy-pasta! came from the original version in skl; will drop that... -- To view, visit https://review.coreboot.org/c/coreboot/+/45535 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1fcc2d0d7c6b6f35f8dd011f55dab8469be99d47 Gerrit-Change-Number: 45535 Gerrit-PatchSet: 8 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Elyes HAOUAS Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-Comment-Date: Tue, 13 Oct 2020 23:30:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/icl: enable common CPU code
by Michael Niewöhner (Code Review) 14 Oct '20

14 Oct '20

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Change in coreboot[master]: soc/intel/icl: enable common CPU code
by Michael Niewöhner (Code Review) 14 Oct '20

14 Oct '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45826 ) Change subject: soc/intel/icl: enable common CPU code ...................................................................... Patch Set 5: (1 comment) https://review.coreboot.org/c/coreboot/+/45826/5//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/45826/5//COMMIT_MSG@13 PS5, Line 13: like done for SKL,ICL,... already. > This isn't quite clear, IMHO. "like done for [...]ICL"? but this is ICL. > I see that the config value is already used in code. That could be clearer. Oops, I meant CNL here ofc. > Also, there is another Kconfig prompt (locking) enabled by this which is > not used, AFAICS. If that is the case, its prompt should be disabled. Either > via another Kconfig (HAVE...LOCKING_OPTION?) or at least select it (prompt > would show but can't be changed, which I assume is what the code does). Yes, the feature lock. I haven't mentioned it here yet, because it's not clear to me yet how we want to handle ICL due to SkipMpInit missing. Have a look at this, please: https://review.coreboot.org/c/coreboot/+/45826/2/src/soc/intel/icelake/roms… In case we want to just rely on FSP, I'd just select SET_IA32_FC_LOCK_BIT by ENABLE_VMX on ICL, to make it clear in menuconfig. ICL Kconfig: config ENABLE_VMX select SET_IA32_FC_LOCK_BIT -- To view, visit https://review.coreboot.org/c/coreboot/+/45826 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I58e86021687fc0a836324f70071f7ea80242b3cb Gerrit-Change-Number: 45826 Gerrit-PatchSet: 5 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 13 Oct 2020 22:55:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/{cnl,icl,tgl,jsl,ehl,adl}/acpi: generate CPPC entries
by Tim Wawrzynczak (Code Review) 14 Oct '20

14 Oct '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45536 ) Change subject: soc/intel/{cnl,icl,tgl,jsl,ehl,adl}/acpi: generate CPPC entries ...................................................................... Patch Set 10: (1 comment) https://review.coreboot.org/c/coreboot/+/45536/10/src/soc/intel/alderlake/a… File src/soc/intel/alderlake/acpi.c: https://review.coreboot.org/c/coreboot/+/45536/10/src/soc/intel/alderlake/a… PS10, Line 162: generate_cppc_entries(core_id); > Why jump through so many hoops here? soc calls generate_cpu_entries(), calls > back here, calls back there. I guess the hardware involves the soc-specific > config struct, but then again, why is it a devicetree config? I think it's another uCode-version related issue... see comments in e3f564988b as an example. -- To view, visit https://review.coreboot.org/c/coreboot/+/45536 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I40d47d18a35002bc9ec55473e94277d89fc5797e Gerrit-Change-Number: 45536 Gerrit-PatchSet: 10 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Elyes HAOUAS Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Tue, 13 Oct 2020 22:47:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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Change in coreboot[master]: libpayload/x86: Try to discover invariant TSC rate
by Michael Niewöhner (Code Review) 14 Oct '20

14 Oct '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34170 ) Change subject: libpayload/x86: Try to discover invariant TSC rate ...................................................................... Patch Set 4: (3 comments) https://review.coreboot.org/c/coreboot/+/34170/4/payloads/libpayload/arch/x… File payloads/libpayload/arch/x86/timer.c: https://review.coreboot.org/c/coreboot/+/34170/4/payloads/libpayload/arch/x… PS4, Line 172: /* newline above https://review.coreboot.org/c/coreboot/+/34170/4/payloads/libpayload/arch/x… PS4, Line 176: _rdmsr(MSR_PLATFORM_INFO) >> 8 nit: brackets for readability? https://review.coreboot.org/c/coreboot/+/34170/4/payloads/libpayload/arch/x… PS4, Line 186: cpu_khz hm, somehow I seem to miss what this global variable is useful for (yeah I know, it was there before but...) -- To view, visit https://review.coreboot.org/c/coreboot/+/34170 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic6607ee2a8b41c2be9dc1bb4f1e23e652bb33889 Gerrit-Change-Number: 34170 Gerrit-PatchSet: 4 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 13 Oct 2020 22:46:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: sc7180: Enable bootblock compression
by Julius Werner (Code Review) 14 Oct '20

14 Oct '20

Hello Philip Chen, mturney mturney, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/45855 to review the following change. Change subject: sc7180: Enable bootblock compression ...................................................................... sc7180: Enable bootblock compression This patch enables bootblock compression on SC7180. In my tests, that makes it boot roughly 10ms faster (which isn't much, but... might as well take it). Signed-off-by: Julius Werner <jwerner(a)chromium.org> Change-Id: Ibbe06eeb05347cc77395681969e6eaf1598b4260 --- M src/arch/arm64/Makefile.inc M src/soc/qualcomm/sc7180/Kconfig M src/soc/qualcomm/sc7180/Makefile.inc M src/soc/qualcomm/sc7180/bootblock.c A src/soc/qualcomm/sc7180/decompressor.c M src/soc/qualcomm/sc7180/memlayout.ld 6 files changed, 16 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/45855/1 diff --git a/src/arch/arm64/Makefile.inc b/src/arch/arm64/Makefile.inc index 920ff5d..44517cb 100644 --- a/src/arch/arm64/Makefile.inc +++ b/src/arch/arm64/Makefile.inc @@ -31,6 +31,7 @@ $(call src-to-obj,decompressor,$(dir)/id.S): $(obj)/build.h $(call src-to-obj,bootblock,$(dir)/id.S): $(obj)/build.h +decompressor-$(CONFIG_ARM64_USE_ARCH_TIMER) += arch_timer.c bootblock-$(CONFIG_ARM64_USE_ARCH_TIMER) += arch_timer.c bootblock-y += transition.c transition_asm.S diff --git a/src/soc/qualcomm/sc7180/Kconfig b/src/soc/qualcomm/sc7180/Kconfig index d543ef5..addb49d 100644 --- a/src/soc/qualcomm/sc7180/Kconfig +++ b/src/soc/qualcomm/sc7180/Kconfig @@ -17,6 +17,7 @@ select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_FORCE_NATIVE_VGA_INIT select HAVE_LINEAR_FRAMEBUFFER + select COMPRESS_BOOTBLOCK if SOC_QUALCOMM_SC7180 diff --git a/src/soc/qualcomm/sc7180/Makefile.inc b/src/soc/qualcomm/sc7180/Makefile.inc index a0d3bc6..7f52a9a 100644 --- a/src/soc/qualcomm/sc7180/Makefile.inc +++ b/src/soc/qualcomm/sc7180/Makefile.inc @@ -1,6 +1,10 @@ ifeq ($(CONFIG_SOC_QUALCOMM_SC7180),y) +decompressor-y += decompressor.c +decompressor-y += mmu.c +decompressor-y += timer.c + ################################################################################ bootblock-y += bootblock.c bootblock-y += mmu.c diff --git a/src/soc/qualcomm/sc7180/bootblock.c b/src/soc/qualcomm/sc7180/bootblock.c index 7dbaeec..cfeb6f9 100644 --- a/src/soc/qualcomm/sc7180/bootblock.c +++ b/src/soc/qualcomm/sc7180/bootblock.c @@ -2,13 +2,11 @@ #include <bootblock_common.h> #include <soc/clock.h> -#include <soc/mmu.h> #include <soc/qspi.h> #include <soc/qupv3_config.h> void bootblock_soc_init(void) { - sc7180_mmu_init(); clock_init(); quadspi_init(37500 * KHz); qupv3_fw_init(); diff --git a/src/soc/qualcomm/sc7180/decompressor.c b/src/soc/qualcomm/sc7180/decompressor.c new file mode 100644 index 0000000..ac55150 --- /dev/null +++ b/src/soc/qualcomm/sc7180/decompressor.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> +#include <soc/mmu.h> + +void decompressor_soc_init(void) +{ + sc7180_mmu_init(); +} diff --git a/src/soc/qualcomm/sc7180/memlayout.ld b/src/soc/qualcomm/sc7180/memlayout.ld index 0142242..ea9a451 100644 --- a/src/soc/qualcomm/sc7180/memlayout.ld +++ b/src/soc/qualcomm/sc7180/memlayout.ld @@ -22,7 +22,7 @@ AOPSRAM_END(0x0B100000) SSRAM_START(0x14680000) - OVERLAP_VERSTAGE_ROMSTAGE(0x14680000, 100K) + OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0x14680000, 100K) REGION(qcsdi, 0x14699000, 52K, 4K) SSRAM_END(0x146AE000) -- To view, visit https://review.coreboot.org/c/coreboot/+/45855 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibbe06eeb05347cc77395681969e6eaf1598b4260 Gerrit-Change-Number: 45855 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Philip Chen <philipchen(a)chromium.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-MessageType: newchange

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coreboot-gerrit October 2020