coreboot-gerrit October 2020

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Change in coreboot[master]: soc/intel/alderlake: Enable TME for Alder Lake
by Subrata Banik (Code Review) 14 Oct '20

14 Oct '20

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46296 ) Change subject: soc/intel/alderlake: Enable TME for Alder Lake ...................................................................... soc/intel/alderlake: Enable TME for Alder Lake List of changes: 1. Select CONFIG_INTEL_TME from SoC Kconfig 2. Set TmeEnable FSP-M UPD based on Kconfig. TEST=Able to build and boot ADLRVP and verified from Chrome OS that TME is enable. Change-Id: I6992957bd2999a2efbae7b6d9c825c43bd118f72 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/alderlake/Kconfig M src/soc/intel/alderlake/romstage/fsp_params.c 2 files changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/46296/1 diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 3f500f3..2d21a61 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -25,6 +25,7 @@ select INTEL_GMA_ACPI select INTEL_GMA_ADD_VBT if RUN_FSP_GOP select IOAPIC + select INTEL_TME select MRC_SETTINGS_PROTECT select PARALLEL_MP select PARALLEL_MP_AP_WORK diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c index 80420f0..b96222c 100644 --- a/src/soc/intel/alderlake/romstage/fsp_params.c +++ b/src/soc/intel/alderlake/romstage/fsp_params.c @@ -155,6 +155,9 @@ /* Skip CPU side PCIe enablement in FSP if device is disabled in devicetree */ dev = pcidev_path_on_root(SA_DEVFN_CPU_PCIE); m_cfg->CpuPcieRpEnableMask = is_dev_enabled(dev); + + /* Change TmeEnable UPD value according to INTEL_TME Kconfig */ + m_cfg->TmeEnable = CONFIG(INTEL_TME); } void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) -- To view, visit https://review.coreboot.org/c/coreboot/+/46296 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6992957bd2999a2efbae7b6d9c825c43bd118f72 Gerrit-Change-Number: 46296 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 7

Change in coreboot[master]: vendorcode/intel/fsp/fsp2_0/adl: Update FSP header file version 1332.01
by Subrata Banik (Code Review) 14 Oct '20

14 Oct '20

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46295 ) Change subject: vendorcode/intel/fsp/fsp2_0/adl: Update FSP header file version 1332.01 ...................................................................... vendorcode/intel/fsp/fsp2_0/adl: Update FSP header file version 1332.01 List of changes: - Add FSP-M UPD 'TmeEnable' TEST=Build and boot ADLRVP platform. Change-Id: Ic5fad998e880e9302b068fc78c28074fa432f1ba Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h 1 file changed, 32 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/46295/1 diff --git a/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h index a42f014..8c4582a 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h @@ -586,7 +586,17 @@ /** Offset 0x037C - Reserved **/ - UINT8 Reserved20[34]; + UINT8 Reserved20[20]; + +/** Offset 0x0390 - Enable or Disable TME + Enable or Disable TME; <b>0: Disable</b>; 1: Enable. + $EN_DIS +**/ + UINT8 TmeEnable; + +/** Offset 0x0391 - Reserved +**/ + UINT8 Reserved21[13]; /** Offset 0x039E - BiosGuard Enable/Disable. 0: Disable, Enable/Disable BIOS Guard feature, 1: enable @@ -600,7 +610,7 @@ /** Offset 0x03A0 - Reserved **/ - UINT8 Reserved21[4]; + UINT8 Reserved22[4]; /** Offset 0x03A4 - PrmrrSize Enable/Disable. 0: Disable, define default value of PrmrrSize , 1: enable @@ -614,7 +624,7 @@ /** Offset 0x03AC - Reserved **/ - UINT8 Reserved22[12]; + UINT8 Reserved23[12]; /** Offset 0x03B8 - TxtHeapMemorySize Enable/Disable. 0: Disable, define default value of TxtHeapMemorySize , 1: enable @@ -628,7 +638,7 @@ /** Offset 0x03C0 - Reserved **/ - UINT8 Reserved23[614]; + UINT8 Reserved24[614]; /** Offset 0x0626 - Number of RsvdSmbusAddressTable. The number of elements in the RsvdSmbusAddressTable. @@ -637,7 +647,7 @@ /** Offset 0x0627 - Reserved **/ - UINT8 Reserved24[4]; + UINT8 Reserved25[4]; /** Offset 0x062B - Usage type for ClkSrc 0-23: PCH rootport, 0x40-0x43: PEG port, 0x70:LAN, 0x80: unspecified but in use @@ -647,7 +657,7 @@ /** Offset 0x063D - Reserved **/ - UINT8 Reserved25[14]; + UINT8 Reserved26[14]; /** Offset 0x064B - ClkReq-to-ClkSrc mapping Number of ClkReq signal assigned to ClkSrc @@ -656,7 +666,7 @@ /** Offset 0x065D - Reserved **/ - UINT8 Reserved26[19]; + UINT8 Reserved27[19]; /** Offset 0x0670 - Enable PCIE RP Mask Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0 @@ -666,7 +676,7 @@ /** Offset 0x0674 - Reserved **/ - UINT8 Reserved27[2]; + UINT8 Reserved28[2]; /** Offset 0x0676 - Enable HD Audio Link Enable/disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1. @@ -676,7 +686,7 @@ /** Offset 0x0677 - Reserved **/ - UINT8 Reserved28[3]; + UINT8 Reserved29[3]; /** Offset 0x067A - Enable HD Audio DMIC_N Link Enable/disable HD Audio DMIC1 link. Muxed with SNDW3. @@ -701,7 +711,7 @@ /** Offset 0x068D - Reserved **/ - UINT8 Reserved29[3]; + UINT8 Reserved30[3]; /** Offset 0x0690 - DMIC<N> Data Pin Muxing Determines DMIC<N> Data Pin muxing. See GPIO_*_MUXING_DMIC<N>_DATA_* @@ -751,7 +761,7 @@ /** Offset 0x06A7 - Reserved **/ - UINT8 Reserved30[13]; + UINT8 Reserved31[13]; /** Offset 0x06B4 - ISA Serial Base selection Select ISA Serial Base address. Default is 0x3F8. @@ -761,7 +771,7 @@ /** Offset 0x06B5 - Reserved **/ - UINT8 Reserved31[4]; + UINT8 Reserved32[4]; /** Offset 0x06B9 - MRC Safe Config Enables/Disable MRC Safe Config @@ -819,7 +829,7 @@ /** Offset 0x06C2 - Reserved **/ - UINT8 Reserved32[2]; + UINT8 Reserved33[2]; /** Offset 0x06C4 - Early Command Training Enables/Disable Early Command Training @@ -829,7 +839,7 @@ /** Offset 0x06C5 - Reserved **/ - UINT8 Reserved33[65]; + UINT8 Reserved34[65]; /** Offset 0x0706 - Ch Hash Mask Set the BIT(s) to be included in the XOR function. NOTE BIT mask corresponds to @@ -839,7 +849,7 @@ /** Offset 0x0708 - Reserved **/ - UINT8 Reserved34[64]; + UINT8 Reserved35[64]; /** Offset 0x0748 - PcdSerialDebugLevel Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load, @@ -852,7 +862,7 @@ /** Offset 0x0749 - Reserved **/ - UINT8 Reserved35[2]; + UINT8 Reserved36[2]; /** Offset 0x074B - Safe Mode Support This option configures the varous items in the IO and MC to be more conservative.(def=Disable) @@ -862,7 +872,7 @@ /** Offset 0x074C - Reserved **/ - UINT8 Reserved36[2]; + UINT8 Reserved37[2]; /** Offset 0x074E - TCSS USB Port Enable Bitmap for per port enabling @@ -871,7 +881,7 @@ /** Offset 0x074F - Reserved **/ - UINT8 Reserved37[50]; + UINT8 Reserved38[50]; /** Offset 0x0781 - Skip external display device scanning Enable: Do not scan for external display device, Disable (Default): Scan external @@ -882,7 +892,7 @@ /** Offset 0x0782 - Reserved **/ - UINT8 Reserved38; + UINT8 Reserved39; /** Offset 0x0783 - Lock PCU Thermal Management registers Lock PCU Thermal Management registers. Enable(Default)=1, Disable=0 @@ -892,7 +902,7 @@ /** Offset 0x0784 - Reserved **/ - UINT8 Reserved39[129]; + UINT8 Reserved40[129]; /** Offset 0x0805 - Skip CPU replacement check Test, 0: disable, 1: enable, Setting this option to skip CPU replacement check @@ -902,7 +912,7 @@ /** Offset 0x0806 - Reserved **/ - UINT8 Reserved40[292]; + UINT8 Reserved41[292]; /** Offset 0x092A - Serial Io Uart Debug Mode Select SerialIo Uart Controller mode @@ -913,7 +923,7 @@ /** Offset 0x092B - Reserved **/ - UINT8 Reserved41[517]; + UINT8 Reserved42[517]; } FSP_M_CONFIG; /** Fsp M UPD Configuration -- To view, visit https://review.coreboot.org/c/coreboot/+/46295 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic5fad998e880e9302b068fc78c28074fa432f1ba Gerrit-Change-Number: 46295 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

4 6

Change in coreboot[master]: soc/intel/common/block: Add common support for USB4/Thunderbolt
by Duncan Laurie (Code Review) 14 Oct '20

14 Oct '20

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44916 ) Change subject: soc/intel/common/block: Add common support for USB4/Thunderbolt ...................................................................... soc/intel/common/block: Add common support for USB4/Thunderbolt This common intel driver will add the requried ACPI _DSD entries for USB4/Thunderbolt ports that are enabled into the SSDT instead of using hardcoded values in the DSDT. Signed-off-by: Duncan Laurie <dlaurie(a)google.com> Change-Id: Ic4a58202d4569cf092ea21a4a83a3af6c42ce9d0 --- A src/soc/intel/common/block/usb4/Kconfig A src/soc/intel/common/block/usb4/Makefile.inc A src/soc/intel/common/block/usb4/usb4.c 3 files changed, 61 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/44916/1 diff --git a/src/soc/intel/common/block/usb4/Kconfig b/src/soc/intel/common/block/usb4/Kconfig new file mode 100644 index 0000000..f588b27 --- /dev/null +++ b/src/soc/intel/common/block/usb4/Kconfig @@ -0,0 +1,4 @@ +config SOC_INTEL_COMMON_BLOCK_USB4 + bool + help + Intel Processor common USB4/Thunderbolt support diff --git a/src/soc/intel/common/block/usb4/Makefile.inc b/src/soc/intel/common/block/usb4/Makefile.inc new file mode 100644 index 0000000..7dad4ba --- /dev/null +++ b/src/soc/intel/common/block/usb4/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_USB4) += usb4.c diff --git a/src/soc/intel/common/block/usb4/usb4.c b/src/soc/intel/common/block/usb4/usb4.c new file mode 100644 index 0000000..b33d774 --- /dev/null +++ b/src/soc/intel/common/block/usb4/usb4.c @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpigen.h> +#include <acpi/acpi_device.h> +#include <device/pci.h> +#include <device/pci_def.h> +#include <device/pci_ids.h> + +#define INTEL_TBT_IMR_VALID_UUID "C44D002F-69F9-4E7D-A904-A7BAABDF43F7" +#define INTEL_TBT_WAKE_SUPPORTED_UUID "6C501103-C189-4296-BA72-9BF5A26EBE5D" + +static void usb4_fill_ssdt(const struct device *dev) +{ + struct acpi_dp *dsd, *pkg; + + if (!dev->enabled) + return; + + acpigen_write_scope(acpi_device_path(dev)); + + dsd = acpi_dp_new_table("_DSD"); + + /* Indicate that device has valid IMR. */ + pkg = acpi_dp_new_table(INTEL_TBT_IMR_VALID_UUID); + acpi_dp_add_integer(pkg, "IMR_VALID", 1); + acpi_dp_add_package(dsd, pkg); + + /* Indicate that device is wake capable. */ + pkg = acpi_dp_new_table(INTEL_TBT_WAKE_SUPPORTED_UUID); + acpi_dp_add_integer(pkg, "WAKE_SUPPORTED", 1); + + acpi_dp_add_package(dsd, pkg); + acpi_dp_write(dsd); + + acpigen_pop_len(); /* Scope */ +} + +static struct device_operations device_ops = { + .read_resources = pci_bus_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_bus_enable_resources, + .scan_bus = scan_static_bus, + .acpi_fill_ssdt = usb4_fill_ssdt, +}; + +static const unsigned short pcie_device_ids[] = { + PCI_DEVICE_ID_INTEL_TGL_TBT_DMA0, + PCI_DEVICE_ID_INTEL_TGL_TBT_DMA1, + 0 +}; + +static const struct pci_driver intel_usb4_driver __pci_driver = { + .ops = &device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = pcie_device_ids, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/44916 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic4a58202d4569cf092ea21a4a83a3af6c42ce9d0 Gerrit-Change-Number: 44916 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 15

Change in coreboot[master]: soc/intel/common: Add PCI driver for USB4 ports
by Tim Wawrzynczak (Code Review) 14 Oct '20

14 Oct '20

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46141 ) Change subject: soc/intel/common: Add PCI driver for USB4 ports ...................................................................... soc/intel/common: Add PCI driver for USB4 ports In order to enable SSDT generation for Intel USB4 ports, a minimal PCI driver is required. Change-Id: Ib9da051307b883eb99e500114378c9fd842ffc92 Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- A src/soc/intel/common/block/usb4/Kconfig A src/soc/intel/common/block/usb4/Makefile.inc A src/soc/intel/common/block/usb4/usb4.c 3 files changed, 32 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/46141/1 diff --git a/src/soc/intel/common/block/usb4/Kconfig b/src/soc/intel/common/block/usb4/Kconfig new file mode 100644 index 0000000..f68c5a7 --- /dev/null +++ b/src/soc/intel/common/block/usb4/Kconfig @@ -0,0 +1,6 @@ +config SOC_INTEL_COMMON_BLOCK_USB4 + bool + default n + help + Minimal PCI Driver for enabling SSDT generation for Intel + Thunderbolt/USB4 ports. diff --git a/src/soc/intel/common/block/usb4/Makefile.inc b/src/soc/intel/common/block/usb4/Makefile.inc new file mode 100644 index 0000000..7dad4ba --- /dev/null +++ b/src/soc/intel/common/block/usb4/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_USB4) += usb4.c diff --git a/src/soc/intel/common/block/usb4/usb4.c b/src/soc/intel/common/block/usb4/usb4.c new file mode 100644 index 0000000..3fc1159 --- /dev/null +++ b/src/soc/intel/common/block/usb4/usb4.c @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> + +static const unsigned short pci_device_ids[] = { + PCI_DEVICE_ID_INTEL_TGL_TBT_DMA0, + PCI_DEVICE_ID_INTEL_TGL_TBT_DMA1, + 0 +}; + +static struct device_operations usb4_dev_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .scan_bus = scan_generic_bus, + .ops_pci = &pci_dev_ops_pci, +}; + +static const struct pci_driver usb4_driver __pci_driver = { + .ops = &usb4_dev_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = pci_device_ids, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/46141 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib9da051307b883eb99e500114378c9fd842ffc92 Gerrit-Change-Number: 46141 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/puff/var/dooly: Enable Ambient Light Sensor (ALS)
by Tony Huang (Code Review) 14 Oct '20

14 Oct '20

Tony Huang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46061 ) Change subject: mb/google/puff/var/dooly: Enable Ambient Light Sensor (ALS) ...................................................................... mb/google/puff/var/dooly: Enable Ambient Light Sensor (ALS) Enable ALS ACPI devices for dooly. BUG=b:168426118 BRANCH=puff TEST=Ensure that ALS devices are enabled in ACPI tables. Change-Id: Idd44d6ae1e7b62939fdfc3a0ab01924d2c1714aa Signed-off-by: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> --- M src/mainboard/google/hatch/variants/dooly/include/variant/ec.h 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/46061/1 diff --git a/src/mainboard/google/hatch/variants/dooly/include/variant/ec.h b/src/mainboard/google/hatch/variants/dooly/include/variant/ec.h index 59fb378..7d280c6 100644 --- a/src/mainboard/google/hatch/variants/dooly/include/variant/ec.h +++ b/src/mainboard/google/hatch/variants/dooly/include/variant/ec.h @@ -5,4 +5,7 @@ #include <puff/ec.h> +/* Enable EC backed ALS device in ACPI */ +#define EC_ENABLE_ALS_DEVICE + #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/46061 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idd44d6ae1e7b62939fdfc3a0ab01924d2c1714aa Gerrit-Change-Number: 46061 Gerrit-PatchSet: 1 Gerrit-Owner: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

3 6

Change in coreboot[master]: soc/intel/{cnl,icl,tgl,jsl,ehl,adl}/acpi: generate CPPC entries
by Michael Niewöhner (Code Review) 14 Oct '20

14 Oct '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45536 ) Change subject: soc/intel/{cnl,icl,tgl,jsl,ehl,adl}/acpi: generate CPPC entries ...................................................................... Patch Set 10: (1 comment) https://review.coreboot.org/c/coreboot/+/45536/10/src/soc/intel/alderlake/a… File src/soc/intel/alderlake/acpi.c: https://review.coreboot.org/c/coreboot/+/45536/10/src/soc/intel/alderlake/a… PS10, Line 162: generate_cppc_entries(core_id); > > Why jump through so many hoops here? soc calls generate_cpu_entries(), calls […] Well, all that jumping was not my idea \o/ that's what sock/intel/common/acpi does already in other cases as well :S -- To view, visit https://review.coreboot.org/c/coreboot/+/45536 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I40d47d18a35002bc9ec55473e94277d89fc5797e Gerrit-Change-Number: 45536 Gerrit-PatchSet: 10 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Elyes HAOUAS Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Tue, 13 Oct 2020 23:32:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/common/block/acpi: add code for CPPC entries generation
by Michael Niewöhner (Code Review) 14 Oct '20

14 Oct '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45535 ) Change subject: soc/intel/common/block/acpi: add code for CPPC entries generation ...................................................................... Patch Set 8: (2 comments) https://review.coreboot.org/c/coreboot/+/45535/8/src/soc/intel/common/block… File src/soc/intel/common/block/acpi/acpi.c: https://review.coreboot.org/c/coreboot/+/45535/8/src/soc/intel/common/block… PS8, Line 370: core > Is this `virtual core` aka. thread? Otherwise it would seem that this is […] Well, that naming scheme is a bit... unclear, but that's what common/block/acpi already does. We can clarify that ofc. TBH I'm not yet convinced that the loop generate_cpu_entries is correct at all. Anyway, the global CPPC entry shall get added once per package only. The (logical) cores each get a _CPC method returning that CPPC (GCPC in cb) entry. `core` is the `core_id` from generate_cpu_entries() which *should* be the APIC id (total number of cores for the loop comes from dev_count_cpu()). https://review.coreboot.org/c/coreboot/+/45535/8/src/soc/intel/common/block… PS8, Line 372: /* version 2 */ > Is the comment really necessary? If you want to name arguments, you could pass […] yay, copy-pasta! came from the original version in skl; will drop that... -- To view, visit https://review.coreboot.org/c/coreboot/+/45535 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1fcc2d0d7c6b6f35f8dd011f55dab8469be99d47 Gerrit-Change-Number: 45535 Gerrit-PatchSet: 8 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Elyes HAOUAS Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-Comment-Date: Tue, 13 Oct 2020 23:30:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/icl: enable common CPU code
by Michael Niewöhner (Code Review) 14 Oct '20

14 Oct '20

1 0

Change in coreboot[master]: soc/intel/icl: enable common CPU code
by Michael Niewöhner (Code Review) 14 Oct '20

14 Oct '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45826 ) Change subject: soc/intel/icl: enable common CPU code ...................................................................... Patch Set 5: (1 comment) https://review.coreboot.org/c/coreboot/+/45826/5//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/45826/5//COMMIT_MSG@13 PS5, Line 13: like done for SKL,ICL,... already. > This isn't quite clear, IMHO. "like done for [...]ICL"? but this is ICL. > I see that the config value is already used in code. That could be clearer. Oops, I meant CNL here ofc. > Also, there is another Kconfig prompt (locking) enabled by this which is > not used, AFAICS. If that is the case, its prompt should be disabled. Either > via another Kconfig (HAVE...LOCKING_OPTION?) or at least select it (prompt > would show but can't be changed, which I assume is what the code does). Yes, the feature lock. I haven't mentioned it here yet, because it's not clear to me yet how we want to handle ICL due to SkipMpInit missing. Have a look at this, please: https://review.coreboot.org/c/coreboot/+/45826/2/src/soc/intel/icelake/roms… In case we want to just rely on FSP, I'd just select SET_IA32_FC_LOCK_BIT by ENABLE_VMX on ICL, to make it clear in menuconfig. ICL Kconfig: config ENABLE_VMX select SET_IA32_FC_LOCK_BIT -- To view, visit https://review.coreboot.org/c/coreboot/+/45826 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I58e86021687fc0a836324f70071f7ea80242b3cb Gerrit-Change-Number: 45826 Gerrit-PatchSet: 5 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 13 Oct 2020 22:55:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/{cnl,icl,tgl,jsl,ehl,adl}/acpi: generate CPPC entries
by Tim Wawrzynczak (Code Review) 14 Oct '20

14 Oct '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45536 ) Change subject: soc/intel/{cnl,icl,tgl,jsl,ehl,adl}/acpi: generate CPPC entries ...................................................................... Patch Set 10: (1 comment) https://review.coreboot.org/c/coreboot/+/45536/10/src/soc/intel/alderlake/a… File src/soc/intel/alderlake/acpi.c: https://review.coreboot.org/c/coreboot/+/45536/10/src/soc/intel/alderlake/a… PS10, Line 162: generate_cppc_entries(core_id); > Why jump through so many hoops here? soc calls generate_cpu_entries(), calls > back here, calls back there. I guess the hardware involves the soc-specific > config struct, but then again, why is it a devicetree config? I think it's another uCode-version related issue... see comments in e3f564988b as an example. -- To view, visit https://review.coreboot.org/c/coreboot/+/45536 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I40d47d18a35002bc9ec55473e94277d89fc5797e Gerrit-Change-Number: 45536 Gerrit-PatchSet: 10 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Elyes HAOUAS Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Tue, 13 Oct 2020 22:47:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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coreboot-gerrit October 2020