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Change in coreboot[master]: nb/intel/x4x: Clean up DMIBAR/EPBAR definitions
by Angel Pons (Code Review) 14 Oct '20

14 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45422 ) Change subject: nb/intel/x4x: Clean up DMIBAR/EPBAR definitions ...................................................................... nb/intel/x4x: Clean up DMIBAR/EPBAR definitions Several registers have been copy-pasted from i945 and do not exist on Eagle Lake. Moreover, other register definitions were missing. Use the newly-added definitions in existing code, in place of numerical offsets. Tested with BUILD_TIMELESS=1, Asus P5QL PRO does not change. Change-Id: I9582d159aa2344bcf261f0e4b97b15787156f6e7 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/x4x/early_init.c M src/northbridge/intel/x4x/x4x.h 2 files changed, 93 insertions(+), 44 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/45422/1 diff --git a/src/northbridge/intel/x4x/early_init.c b/src/northbridge/intel/x4x/early_init.c index 81752cd..279a38f 100644 --- a/src/northbridge/intel/x4x/early_init.c +++ b/src/northbridge/intel/x4x/early_init.c @@ -60,59 +60,59 @@ u32 reg32; /* VC0: TC0 only */ - EPBAR8(0x14) = 1; - EPBAR8(0x4) = 1; + EPBAR8(EPVC0RCTL) = 1; + EPBAR8(EPPVCCAP1) = 1; switch (MCHBAR32(0xc00) & 0x7) { case 0x0: /* FSB 1066 */ - EPBAR32(0x2c) = 0x0001a6db; + EPBAR32(EPVC1ITC) = 0x0001a6db; break; case 0x2: /* FSB 800 */ - EPBAR32(0x2c) = 0x00014514; + EPBAR32(EPVC1ITC) = 0x00014514; break; default: case 0x4: /* FSB 1333 */ - EPBAR32(0x2c) = 0x00022861; + EPBAR32(EPVC1ITC) = 0x00022861; break; } - EPBAR32(0x28) = 0x0a0a0a0a; - EPBAR8(0xc) = (EPBAR8(0xc) & ~0xe) | 2; - EPBAR32(0x1c) = (EPBAR32(0x1c) & ~0x7f0000) | 0x0a0000; + EPBAR32(EPVC1MTS) = 0x0a0a0a0a; + EPBAR8(EPPVCCTL) = (EPBAR8(EPPVCCTL) & ~0xe) | 2; + EPBAR32(EPVC1RCAP) = (EPBAR32(EPVC1RCAP) & ~0x7f0000) | 0x0a0000; MCHBAR8(0x3c) = MCHBAR8(0x3c) | 0x7; /* VC1: ID1, TC7 */ - reg32 = (EPBAR32(0x20) & ~(7 << 24)) | (1 << 24); + reg32 = (EPBAR32(EPVC1RCTL) & ~(7 << 24)) | (1 << 24); reg32 = (reg32 & ~0xfe) | (1 << 7); - EPBAR32(0x20) = reg32; + EPBAR32(EPVC1RCTL) = reg32; /* Init VC1 port arbitration table */ - EPBAR32(0x100) = 0x001000001; - EPBAR32(0x104) = 0x000040000; - EPBAR32(0x108) = 0x000001000; - EPBAR32(0x10c) = 0x000000040; - EPBAR32(0x110) = 0x001000001; - EPBAR32(0x114) = 0x000040000; - EPBAR32(0x118) = 0x000001000; - EPBAR32(0x11c) = 0x000000040; + EPBAR32(EP_PORTARB(0)) = 0x001000001; + EPBAR32(EP_PORTARB(1)) = 0x000040000; + EPBAR32(EP_PORTARB(2)) = 0x000001000; + EPBAR32(EP_PORTARB(3)) = 0x000000040; + EPBAR32(EP_PORTARB(4)) = 0x001000001; + EPBAR32(EP_PORTARB(5)) = 0x000040000; + EPBAR32(EP_PORTARB(6)) = 0x000001000; + EPBAR32(EP_PORTARB(7)) = 0x000000040; /* Load table */ - reg32 = EPBAR32(0x20) | (1 << 16); - EPBAR32(0x20) = reg32; + reg32 = EPBAR32(EPVC1RCTL) | (1 << 16); + EPBAR32(EPVC1RCTL) = reg32; asm("nop"); - EPBAR32(0x20) = reg32; + EPBAR32(EPVC1RCTL) = reg32; /* Wait for table load */ - while ((EPBAR8(0x26) & (1 << 0)) != 0) + while ((EPBAR8(EPVC1RSTS) & (1 << 0)) != 0) ; /* VC1: enable */ - EPBAR32(0x20) |= 1 << 31; + EPBAR32(EPVC1RCTL) |= 1 << 31; /* Wait for VC1 */ - while ((EPBAR8(0x26) & (1 << 1)) != 0) + while ((EPBAR8(EPVC1RSTS) & (1 << 1)) != 0) ; printk(BIOS_DEBUG, "Done Egress Port\n"); @@ -125,12 +125,12 @@ /* Assume IGD present */ /* Clear error status */ - DMIBAR32(0x1c4) = 0xffffffff; - DMIBAR32(0x1d0) = 0xffffffff; + DMIBAR32(DMIUESTS) = 0xffffffff; + DMIBAR32(DMICESTS) = 0xffffffff; /* VC0: TC0 only */ DMIBAR8(DMIVC0RCTL) = 1; - DMIBAR8(0x4) = 1; + DMIBAR8(DMIPVCCAP1) = 1; /* VC1: ID1, TC7 */ reg32 = (DMIBAR32(DMIVC1RCTL) & ~(7 << 24)) | (1 << 24); @@ -203,17 +203,17 @@ /* Set up VC1 max time */ RCBA32(0x1c) = (RCBA32(0x1c) & ~0x7f0000) | 0x120000; - while ((DMIBAR32(0x26) & (1 << 1)) != 0) + while ((DMIBAR32(DMIVC1RSTS) & VC1NP) != 0) ; printk(BIOS_DEBUG, "Done DMI setup\n"); /* ASPM on DMI */ DMIBAR32(0x200) &= ~(0x3 << 26); DMIBAR16(0x210) = (DMIBAR16(0x210) & ~(0xff7)) | 0x101; - DMIBAR32(0x88) &= ~0x3; - DMIBAR32(0x88) |= 0x3; - /* FIXME: Do we need to read RCBA16(0x88)? */ - DMIBAR16(0x88); + DMIBAR32(DMILCTL) &= ~0x3; + DMIBAR32(DMILCTL) |= 0x3; + /* FIXME: Do we need to read RCBA16(DMILCTL)? Probably not. */ + DMIBAR16(DMILCTL); } static void x4x_prepare_resume(int s3resume) diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h index 6df661d..c97b511 100644 --- a/src/northbridge/intel/x4x/x4x.h +++ b/src/northbridge/intel/x4x/x4x.h @@ -93,14 +93,43 @@ #define DMIBAR16(x) (*((volatile u16 *)(DEFAULT_DMIBAR + (x)))) #define DMIBAR32(x) (*((volatile u32 *)(DEFAULT_DMIBAR + (x)))) -#define DMIVC0RCTL 0x14 -#define DMIVC1RCTL 0x20 -#define DMIVC1RSTS 0x26 -#define DMIESD 0x44 -#define DMILE1D 0x50 -#define DMILE1A 0x58 -#define DMILE2D 0x60 -#define DMILE2A 0x68 + +#define DMIVCECH 0x000 /* 32bit */ +#define DMIPVCCAP1 0x004 /* 32bit */ + +#define DMIVC0RCAP 0x010 /* 32bit */ +#define DMIVC0RCTL 0x014 /* 32bit */ +#define DMIVC0RSTS 0x01a /* 16bit */ +#define VC0NP (1 << 1) + +#define DMIVC1RCAP 0x01c /* 32bit */ +#define DMIVC1RCTL 0x020 /* 32bit */ +#define DMIVC1RSTS 0x026 /* 16bit */ +#define VC1NP (1 << 1) + +#define DMIVCPRCAP 0x028 /* 32bit */ +#define DMIVCPRCTL 0x02c /* 32bit */ +#define DMIVCPRSTS 0x032 /* 16bit */ +#define VCPNP (1 << 1) + +#define DMIVCMRCAP 0x034 /* 32bit */ +#define DMIVCMRCTL 0x038 /* 32bit */ +#define DMIVCMRSTS 0x03e /* 16bit */ +#define VCMNP (1 << 1) + +#define DMIESD 0x044 /* 32bit */ + +#define DMILE1D 0x050 /* 32bit */ +#define DMILE1A 0x058 /* 64bit */ +#define DMILE2D 0x060 /* 32bit */ +#define DMILE2A 0x068 /* 64bit */ + +#define DMILCAP 0x084 /* 32bit */ +#define DMILCTL 0x088 /* 16bit */ +#define DMILSTS 0x08a /* 16bit */ + +#define DMIUESTS 0x1c4 /* 32bit */ +#define DMICESTS 0x1d0 /* 32bit */ /* * EPBAR @@ -110,10 +139,30 @@ #define EPBAR16(x) (*((volatile u16 *)(DEFAULT_EPBAR + (x)))) #define EPBAR32(x) (*((volatile u32 *)(DEFAULT_EPBAR + (x)))) -#define EPESD 0x44 -#define EPLE1D 0x50 -#define EPLE1A 0x58 -#define EPLE2D 0x60 +#define EPPVCCAP1 0x004 /* 32bit */ +#define EPPVCCTL 0x00c /* 32bit */ + +#define EPVC0RCAP 0x010 /* 32bit */ +#define EPVC0RCTL 0x014 /* 32bit */ +#define EPVC0RSTS 0x01a /* 16bit */ + +#define EPVC1RCAP 0x01c /* 32bit */ +#define EPVC1RCTL 0x020 /* 32bit */ +#define EPVC1RSTS 0x026 /* 16bit */ + +#define EPVC1MTS 0x028 /* 32bit */ +#define EPVC1ITC 0x02c /* 32bit */ + +#define EPESD 0x044 /* 32bit */ + +#define EPLE1D 0x050 /* 32bit */ +#define EPLE1A 0x058 /* 64bit */ +#define EPLE2D 0x060 /* 32bit */ +#define EPLE2A 0x068 /* 64bit */ + +#define EP_PORTARB(x) (0x100 + 4 * (x)) /* 256bit */ + + #define NOP_CMD 0x2 #define PRECHARGE_CMD 0x4 -- To view, visit https://review.coreboot.org/c/coreboot/+/45422 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9582d159aa2344bcf261f0e4b97b15787156f6e7 Gerrit-Change-Number: 45422 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/broadwell/xhci.c: Align with Lynx Point
by Angel Pons (Code Review) 14 Oct '20

14 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45721 ) Change subject: soc/intel/broadwell/xhci.c: Align with Lynx Point ...................................................................... soc/intel/broadwell/xhci.c: Align with Lynx Point Change-Id: Idf40e2687b064c5ec7834e3c7d7ea9c8cb83c882 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/broadwell/xhci.c 1 file changed, 2 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/45721/1 diff --git a/src/soc/intel/broadwell/xhci.c b/src/soc/intel/broadwell/xhci.c index 319c9b1..6d824a5 100644 --- a/src/soc/intel/broadwell/xhci.c +++ b/src/soc/intel/broadwell/xhci.c @@ -138,18 +138,13 @@ return; /* Set D0 state */ - reg16 = pci_read_config16(dev, XHCI_PWR_CTL_STS); - reg16 &= ~XHCI_PWR_CTL_SET_MASK; - reg16 |= XHCI_PWR_CTL_SET_D0; - pci_write_config16(dev, XHCI_PWR_CTL_STS, reg16); + pci_update_config16(dev, XHCI_PWR_CTL_STS, ~PWR_CTL_SET_MASK, PWR_CTL_SET_D0); if (!is_broadwell) { /* This WA is only for lpt */ /* Clear PCI 0xB0[14:13] */ - reg32 = pci_read_config32(dev, 0xb0); - reg32 &= ~((1 << 14) | (1 << 13)); - pci_write_config32(dev, 0xb0, reg32); + pci_and_config32(dev, 0xb0, ~((1 << 14) | (1 << 13))); /* Clear MMIO 0x816c[14,2] */ reg32 = read32(mem_base + 0x816c); -- To view, visit https://review.coreboot.org/c/coreboot/+/45721 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idf40e2687b064c5ec7834e3c7d7ea9c8cb83c882 Gerrit-Change-Number: 45721 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 4

Change in coreboot[master]: soc/intel/broadwell/smi.c: Drop unused functions
by Angel Pons (Code Review) 14 Oct '20

14 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45716 ) Change subject: soc/intel/broadwell/smi.c: Drop unused functions ...................................................................... soc/intel/broadwell/smi.c: Drop unused functions These aren't used anywhere, so get rid of them. Change-Id: I267c0fd2e9d9d20ee852a73a9a916d85d6c65088 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/broadwell/smi.c 1 file changed, 0 insertions(+), 32 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/45716/1 diff --git a/src/soc/intel/broadwell/smi.c b/src/soc/intel/broadwell/smi.c index 317da0c..d7704fd 100644 --- a/src/soc/intel/broadwell/smi.c +++ b/src/soc/intel/broadwell/smi.c @@ -54,35 +54,3 @@ { smm_southbridge_enable(PWRBTN_EN | GBL_EN); } - -static void __unused southbridge_trigger_smi(void) -{ - /** - * There are several methods of raising a controlled SMI# via - * software, among them: - * - Writes to io 0xb2 (APMC) - * - Writes to the Local Apic ICR with Delivery mode SMI. - * - * Using the local APIC is a bit more tricky. According to - * AMD Family 11 Processor BKDG no destination shorthand must be - * used. - * The whole SMM initialization is quite a bit hardware specific, so - * I'm not too worried about the better of the methods at the moment - */ - - /* raise an SMI interrupt */ - printk(BIOS_SPEW, " ... raise SMI#\n"); - apm_control(APM_CNT_NOOP_SMI); -} - -static void __unused southbridge_clear_smi_status(void) -{ - /* Clear SMI status */ - clear_smi_status(); - - /* Clear PM1 status */ - clear_pm1_status(); - - /* Set EOS bit so other SMIs can occur. */ - enable_smi(EOS); -} -- To view, visit https://review.coreboot.org/c/coreboot/+/45716 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I267c0fd2e9d9d20ee852a73a9a916d85d6c65088 Gerrit-Change-Number: 45716 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 4

Change in coreboot[master]: soc/intel/broadwell/pcie.c: Add some null checks
by Angel Pons (Code Review) 14 Oct '20

14 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45715 ) Change subject: soc/intel/broadwell/pcie.c: Add some null checks ...................................................................... soc/intel/broadwell/pcie.c: Add some null checks These are present in Lynx Point. Change-Id: I381f3cbf5fd18c952622f757135c0bde9ed6ed0d Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/broadwell/pcie.c 1 file changed, 4 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/45715/1 diff --git a/src/soc/intel/broadwell/pcie.c b/src/soc/intel/broadwell/pcie.c index 01ee068..0d41d42 100644 --- a/src/soc/intel/broadwell/pcie.c +++ b/src/soc/intel/broadwell/pcie.c @@ -182,7 +182,7 @@ /* Determine the new devfn for this port */ new_devfn = PCI_DEVFN(PCH_DEV_SLOT_PCIE, pci_func); - if (dev->path.pci.devfn != new_devfn) { + if (dev && dev->path.pci.devfn != new_devfn) { printk(BIOS_DEBUG, "PCH: PCIe map %02x.%1x -> %02x.%1x\n", PCI_SLOT(dev->path.pci.devfn), @@ -204,6 +204,9 @@ int rp; dev = rpc.ports[i]; + if (!dev) + continue; + rp = root_port_number(dev); if (!dev->enabled) { -- To view, visit https://review.coreboot.org/c/coreboot/+/45715 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I381f3cbf5fd18c952622f757135c0bde9ed6ed0d Gerrit-Change-Number: 45715 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 4

Change in coreboot[master]: haswell/lynxpoint: Align cosmetics with Broadwell
by Angel Pons (Code Review) 14 Oct '20

14 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45698 ) Change subject: haswell/lynxpoint: Align cosmetics with Broadwell ...................................................................... haswell/lynxpoint: Align cosmetics with Broadwell Tested with BUILD_TIMELESS=1, Google Wolf does not change. Change-Id: Ibd8430352e860ffc0e2030fd7bc73582982f4695 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/cpu/intel/haswell/acpi.c M src/cpu/intel/haswell/smmrelocate.c M src/southbridge/intel/lynxpoint/acpi/globalnvs.asl M src/southbridge/intel/lynxpoint/acpi/lpc.asl M src/southbridge/intel/lynxpoint/acpi/pch.asl M src/southbridge/intel/lynxpoint/acpi/serialio.asl M src/southbridge/intel/lynxpoint/chip.h M src/southbridge/intel/lynxpoint/elog.c M src/southbridge/intel/lynxpoint/lpc.c M src/southbridge/intel/lynxpoint/me_status.c M src/southbridge/intel/lynxpoint/pcie.c M src/southbridge/intel/lynxpoint/pmutil.c M src/southbridge/intel/lynxpoint/smihandler.c 13 files changed, 152 insertions(+), 151 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/45698/1 diff --git a/src/cpu/intel/haswell/acpi.c b/src/cpu/intel/haswell/acpi.c index 676acce..6dd8559 100644 --- a/src/cpu/intel/haswell/acpi.c +++ b/src/cpu/intel/haswell/acpi.c @@ -65,50 +65,6 @@ acpigen_pop_len(); } -static void generate_C_state_entries(void) -{ - struct cpu_info *info; - struct cpu_driver *cpu; - struct device *lapic; - struct cpu_intel_haswell_config *conf = NULL; - - /* Find the SpeedStep CPU in the device tree using magic APIC ID */ - lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC); - if (!lapic) - return; - conf = lapic->chip_info; - if (!conf) - return; - - /* Find CPU map of supported C-states */ - info = cpu_info(); - if (!info) - return; - cpu = find_cpu_driver(info->cpu); - if (!cpu || !cpu->cstates) - return; - - acpigen_emit_byte(0x14); /* MethodOp */ - acpigen_write_len_f(); /* PkgLength */ - acpigen_emit_namestring("_CST"); - acpigen_emit_byte(0x00); /* No Arguments */ - - /* If running on AC power */ - acpigen_emit_byte(0xa0); /* IfOp */ - acpigen_write_len_f(); /* PkgLength */ - acpigen_emit_namestring("PWRS"); - acpigen_emit_byte(0xa4); /* ReturnOp */ - generate_cstate_entries(cpu->cstates, conf->c1_acpower, - conf->c2_acpower, conf->c3_acpower); - acpigen_pop_len(); - - /* Else on battery power */ - acpigen_emit_byte(0xa4); /* ReturnOp */ - generate_cstate_entries(cpu->cstates, conf->c1_battery, - conf->c2_battery, conf->c3_battery); - acpigen_pop_len(); -} - static acpi_tstate_t tss_table_fine[] = { { 100, 1000, 0, 0x00, 0 }, { 94, 940, 0, 0x1f, 0 }, @@ -161,6 +117,50 @@ ARRAY_SIZE(tss_table_coarse), tss_table_coarse); } +static void generate_C_state_entries(void) +{ + struct cpu_info *info; + struct cpu_driver *cpu; + struct device *lapic; + struct cpu_intel_haswell_config *conf = NULL; + + /* Find the SpeedStep CPU in the device tree using magic APIC ID */ + lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC); + if (!lapic) + return; + conf = lapic->chip_info; + if (!conf) + return; + + /* Find CPU map of supported C-states */ + info = cpu_info(); + if (!info) + return; + cpu = find_cpu_driver(info->cpu); + if (!cpu || !cpu->cstates) + return; + + acpigen_emit_byte(0x14); /* MethodOp */ + acpigen_write_len_f(); /* PkgLength */ + acpigen_emit_namestring("_CST"); + acpigen_emit_byte(0x00); /* No Arguments */ + + /* If running on AC power */ + acpigen_emit_byte(0xa0); /* IfOp */ + acpigen_write_len_f(); /* PkgLength */ + acpigen_emit_namestring("PWRS"); + acpigen_emit_byte(0xa4); /* ReturnOp */ + generate_cstate_entries(cpu->cstates, conf->c1_acpower, + conf->c2_acpower, conf->c3_acpower); + acpigen_pop_len(); + + /* Else on battery power */ + acpigen_emit_byte(0xa4); /* ReturnOp */ + generate_cstate_entries(cpu->cstates, conf->c1_battery, + conf->c2_battery, conf->c3_battery); + acpigen_pop_len(); +} + static int calculate_power(int tdp, int p1_ratio, int ratio) { u32 m; @@ -307,19 +307,19 @@ /* Generate processor \_SB.CPUx */ acpigen_write_processor( - (cpuID-1)*cores_per_package+coreID-1, + (cpuID - 1) * cores_per_package+coreID - 1, pcontrol_blk, plen); /* Generate P-state tables */ generate_P_state_entries( - coreID-1, cores_per_package); + coreID - 1, cores_per_package); /* Generate C-state tables */ generate_C_state_entries(); /* Generate T-state tables */ generate_T_state_entries( - cpuID-1, cores_per_package); + cpuID - 1, cores_per_package); acpigen_pop_len(); } diff --git a/src/cpu/intel/haswell/smmrelocate.c b/src/cpu/intel/haswell/smmrelocate.c index 39e71fe..3f9345f 100644 --- a/src/cpu/intel/haswell/smmrelocate.c +++ b/src/cpu/intel/haswell/smmrelocate.c @@ -156,7 +156,6 @@ { uintptr_t tseg_base; size_t tseg_size; - u32 prmrr_base; u32 prmrr_size; int phys_bits; @@ -197,7 +196,7 @@ params->uncore_prmrr_base.lo = prmrr_base; params->uncore_prmrr_base.hi = 0; params->uncore_prmrr_mask.lo = (~(prmrr_size - 1) & rmask) | - MTRR_PHYS_MASK_VALID; + MTRR_PHYS_MASK_VALID; params->uncore_prmrr_mask.hi = (1 << (39 - 32)) - 1; } @@ -282,6 +281,5 @@ * make the SMM registers writable again. */ printk(BIOS_DEBUG, "Locking SMM.\n"); - pci_write_config8(pcidev_on_root(0, 0), SMRAM, - D_LCK | G_SMRAME | C_BASE_SEG); + pci_write_config8(pcidev_on_root(0, 0), SMRAM, D_LCK | G_SMRAME | C_BASE_SEG); } diff --git a/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl b/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl index 16c4b75..ee2d800 100644 --- a/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl +++ b/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl @@ -2,9 +2,10 @@ /* Global Variables */ -Name(\PICM, 0) // IOAPIC/8259 +Name (\PICM, 0) // IOAPIC/8259 -/* Global ACPI memory region. This region is used for passing information +/* + * Global ACPI memory region. This region is used for passing information * between coreboot (aka "the system bios"), ACPI, and the SMI handler. * Since we don't know where this will end up in memory at ACPI compile time, * we have to fix it up in coreboot's ACPI creation phase. @@ -31,9 +32,9 @@ PWRS, 8, // 0x10 - Power State (AC = 1) /* Thermal policy */ Offset (0x11), - TLVL, 8, // 0x11 - Throttle Level Limit + TLVL, 8, // 0x11 - Throttle Level Limit FLVL, 8, // 0x12 - Current FAN Level - TCRT, 8, // 0x13 - Critical Threshold + TCRT, 8, // 0x13 - Critical Threshold TPSV, 8, // 0x14 - Passive Threshold TMAX, 8, // 0x15 - CPU Tj_max F0OF, 8, // 0x16 - FAN 0 OFF Threshold @@ -51,7 +52,7 @@ F4OF, 8, // 0x22 - FAN 4 OFF Threshold F4ON, 8, // 0x23 - FAN 4 ON Threshold F4PW, 8, // 0x24 - FAN 4 PWM value - TMPS, 8, // 0x25 - Temperature Sensor ID + TMPS, 8, // 0x25 - Temperature Sensor ID /* Processor Identification */ Offset (0x28), APIC, 8, // 0x28 - APIC Enabled by coreboot diff --git a/src/southbridge/intel/lynxpoint/acpi/lpc.asl b/src/southbridge/intel/lynxpoint/acpi/lpc.asl index 1e9de3c..bc1d73c 100644 --- a/src/southbridge/intel/lynxpoint/acpi/lpc.asl +++ b/src/southbridge/intel/lynxpoint/acpi/lpc.asl @@ -4,7 +4,7 @@ Device (LPCB) { - Name(_ADR, 0x001f0000) + Name (_ADR, 0x001f0000) OperationRegion(LPC0, PCI_Config, 0x00, 0x100) Field (LPC0, AnyAcc, NoLock, Preserve) @@ -14,7 +14,7 @@ Offset (0x40), PMBS, 16, // PMBASE Offset (0x48), - GPBS, 16, // GPIOBASE + GPBS, 16, // GPIOBASE Offset (0x60), // Interrupt Routing Registers PRTA, 8, PRTB, 8, @@ -40,10 +40,10 @@ #include "acpi/ec.asl" - Device (DMAC) // DMA Controller + Device (DMAC) // DMA Controller { - Name(_HID, EISAID("PNP0200")) - Name(_CRS, ResourceTemplate() + Name (_HID, EISAID("PNP0200")) + Name (_CRS, ResourceTemplate() { IO (Decode16, 0x00, 0x00, 0x01, 0x20) IO (Decode16, 0x81, 0x81, 0x01, 0x11) @@ -53,7 +53,7 @@ }) } - Device (FWH) // Firmware Hub + Device (FWH) // Firmware Hub { Name (_HID, EISAID("INT0800")) Name (_CRS, ResourceTemplate() @@ -67,7 +67,7 @@ Name (_HID, EISAID("PNP0103")) Name (_CID, 0x010CD041) - Name(BUF0, ResourceTemplate() + Name (BUF0, ResourceTemplate() { Memory32Fixed(ReadOnly, CONFIG_HPET_ADDRESS, 0x400, FED0) }) @@ -90,7 +90,7 @@ Method (_CRS, 0, Serialized) // Current resources { If (HPTE) { - CreateDWordField(BUF0, \_SB.PCI0.LPCB.HPET.FED0._BAS, HPT0) + CreateDWordField (BUF0, \_SB.PCI0.LPCB.HPET.FED0._BAS, HPT0) If (Lequal(HPAS, 1)) { Add(CONFIG_HPET_ADDRESS, 0x1000, HPT0) } @@ -110,8 +110,8 @@ Device(PIC) // 8259 Interrupt Controller { - Name(_HID,EISAID("PNP0000")) - Name(_CRS, ResourceTemplate() + Name (_HID,EISAID("PNP0000")) + Name (_CRS, ResourceTemplate() { IO (Decode16, 0x20, 0x20, 0x01, 0x02) IO (Decode16, 0x24, 0x24, 0x01, 0x02) @@ -160,8 +160,7 @@ IO (Decode16, 0x80, 0x80, 0x1, 0x01) // Port 80 Post IO (Decode16, 0x92, 0x92, 0x1, 0x01) // CPU Reserved IO (Decode16, 0xb2, 0xb2, 0x1, 0x02) // SWSMI - IO (Decode16, DEFAULT_PMBASE, DEFAULT_PMBASE, - 0x1, 0xff) + IO (Decode16, DEFAULT_PMBASE, DEFAULT_PMBASE, 0x1, 0xff) // GPIO region may be 128 bytes or 4096 bytes IO (Decode16, 0x0000, 0x0000, 0x1, 0x00, GPR1) @@ -197,9 +196,8 @@ Device (TIMR) // Intel 8254 timer { - Name(_HID, EISAID("PNP0100")) - Name(_CRS, ResourceTemplate() - { + Name (_HID, EISAID("PNP0100")) + Name (_CRS, ResourceTemplate() { IO (Decode16, 0x40, 0x40, 0x01, 0x04) IO (Decode16, 0x50, 0x50, 0x10, 0x04) IRQNoFlags() {0} diff --git a/src/southbridge/intel/lynxpoint/acpi/pch.asl b/src/southbridge/intel/lynxpoint/acpi/pch.asl index 154633d..4101985 100644 --- a/src/southbridge/intel/lynxpoint/acpi/pch.asl +++ b/src/southbridge/intel/lynxpoint/acpi/pch.asl @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* Intel Cougar Point PCH support */ +/* Intel Lynx Point PCH support */ -Scope(\) +Scope (\) { // Return TRUE if chipset is LynxPoint-LP Method (ISLP, 0, NotSerialized) @@ -11,17 +11,16 @@ } // IO-Trap at 0x800. This is the ACPI->SMI communication interface. - - OperationRegion(IO_T, SystemIO, 0x800, 0x10) - Field(IO_T, ByteAcc, NoLock, Preserve) + OperationRegion (IO_T, SystemIO, 0x800, 0x10) + Field (IO_T, ByteAcc, NoLock, Preserve) { - Offset(0x8), + Offset (0x8), TRP0, 8 // IO-Trap at 0x808 } - // ICH7 Root Complex Register Block. Memory Mapped through RCBA) - OperationRegion(RCRB, SystemMemory, DEFAULT_RCBA, 0x4000) - Field(RCRB, DWordAcc, Lock, Preserve) + // Root Complex Register Block + OperationRegion (RCRB, SystemMemory, DEFAULT_RCBA, 0x4000) + Field (RCRB, DWordAcc, Lock, Preserve) { Offset(0x0000), // Backbone Offset(0x1000), // Chipset diff --git a/src/southbridge/intel/lynxpoint/acpi/serialio.asl b/src/southbridge/intel/lynxpoint/acpi/serialio.asl index 83bc6eb..7acd30d 100644 --- a/src/southbridge/intel/lynxpoint/acpi/serialio.asl +++ b/src/southbridge/intel/lynxpoint/acpi/serialio.asl @@ -116,7 +116,7 @@ Name (RBUF, ResourceTemplate () { Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0) - Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , ,) {7} + Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) {7} }) Method (_CRS, 0, NotSerialized) @@ -156,7 +156,7 @@ Name (RBUF, ResourceTemplate () { Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0) - Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , ,) {7} + Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) {7} }) // DMA channels are only used if Serial IO DMA controller is enabled @@ -237,7 +237,7 @@ Name (RBUF, ResourceTemplate () { Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0) - Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , ,) {7} + Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) {7} }) // DMA channels are only used if Serial IO DMA controller is enabled @@ -315,7 +315,7 @@ Name (RBUF, ResourceTemplate () { Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0) - Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , ,) {7} + Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) {7} }) Method (_CRS, 0, NotSerialized) @@ -352,7 +352,7 @@ Name (RBUF, ResourceTemplate () { Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0) - Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , ,) {7} + Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) {7} }) // DMA channels are only used if Serial IO DMA controller is enabled @@ -402,7 +402,7 @@ Name (RBUF, ResourceTemplate () { Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0) - Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , ,) {13} + Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) {13} }) // DMA channels are only used if Serial IO DMA controller is enabled @@ -452,7 +452,7 @@ Name (RBUF, ResourceTemplate () { Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0) - Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , ,) {13} + Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) {13} }) Method (_CRS, 0, NotSerialized) @@ -489,7 +489,7 @@ Name (RBUF, ResourceTemplate () { Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0) - Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , ,) {5} + Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) {5} }) Method (_CRS, 0, NotSerialized) diff --git a/src/southbridge/intel/lynxpoint/chip.h b/src/southbridge/intel/lynxpoint/chip.h index e30d4b4..40d0460 100644 --- a/src/southbridge/intel/lynxpoint/chip.h +++ b/src/southbridge/intel/lynxpoint/chip.h @@ -47,7 +47,8 @@ uint32_t sata_port0_gen3_dtle; uint32_t sata_port1_gen3_dtle; - /* SATA DEVSLP Mux + /* + * SATA DEVSLP Mux * 0 = port 0 DEVSLP on DEVSLP0/GPIO33 * 1 = port 3 DEVSLP on DEVSLP0/GPIO33 */ @@ -67,12 +68,13 @@ /* Enable linear PCIe Root Port function numbers starting at zero */ uint8_t pcie_port_coalesce; + /* Force root port ASPM configuration with port bitmap */ uint8_t pcie_port_force_aspm; - /* Serial IO configuration */ - /* Put devices into ACPI mode instead of a PCI device */ + /* Put SerialIO devices into ACPI mode instead of a PCI device */ uint8_t sio_acpi_mode; + /* I2C voltage select: 0=3.3V 1=1.8V */ uint8_t sio_i2c0_voltage; uint8_t sio_i2c1_voltage; @@ -91,4 +93,4 @@ bool docking_supported; }; -#endif /* SOUTHBRIDGE_INTEL_LYNXPOINT_CHIP_H */ +#endif /* SOUTHBRIDGE_INTEL_LYNXPOINT_CHIP_H */ diff --git a/src/southbridge/intel/lynxpoint/elog.c b/src/southbridge/intel/lynxpoint/elog.c index 8146794..3ce765d 100644 --- a/src/southbridge/intel/lynxpoint/elog.c +++ b/src/southbridge/intel/lynxpoint/elog.c @@ -46,7 +46,7 @@ u16 pmbase = get_pmbase(); u32 gpe0_sts, gpe0_en; int gpe0_high_gpios[] = { - [0] = 27, + [0] = 27, [24] = 17, [25] = 19, [26] = 21, diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index e561430..fad83b1 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -115,7 +115,7 @@ */ for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { - u8 int_pin=0, int_line=0; + u8 int_pin = 0, int_line = 0; if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI) continue; @@ -446,7 +446,7 @@ reg32 &= ~(1 << 29); // LPC Dynamic else reg32 |= (1 << 29); // LPC Dynamic - reg32 |= (1UL << 31); // LP LPC + reg32 |= (1 << 31); // LP LPC reg32 |= (1 << 30); // LP BLA reg32 |= (1 << 28); // GPIO Dynamic reg32 |= (1 << 27); // HPET Dynamic @@ -565,7 +565,7 @@ res->base = (resource_t)(uintptr_t)DEFAULT_RCBA; res->size = 16 * 1024; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | - IORESOURCE_FIXED | IORESOURCE_RESERVE; + IORESOURCE_FIXED | IORESOURCE_RESERVE; } /* Check LPC Memory Decode register. */ @@ -577,7 +577,7 @@ res->base = reg; res->size = 16 * 1024; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | - IORESOURCE_FIXED | IORESOURCE_RESERVE; + IORESOURCE_FIXED | IORESOURCE_RESERVE; } } } @@ -645,8 +645,7 @@ res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; /* GPIOBASE */ - pch_lpc_add_io_resource(dev, get_gpiobase(), DEFAULT_GPIOSIZE, - GPIO_BASE); + pch_lpc_add_io_resource(dev, get_gpiobase(), DEFAULT_GPIOSIZE, GPIO_BASE); /* PMBASE */ pch_lpc_add_io_resource(dev, get_pmbase(), 256, PMBASE); diff --git a/src/southbridge/intel/lynxpoint/me_status.c b/src/southbridge/intel/lynxpoint/me_status.c index 045d960..82a8f8e 100644 --- a/src/southbridge/intel/lynxpoint/me_status.c +++ b/src/southbridge/intel/lynxpoint/me_status.c @@ -11,7 +11,7 @@ [ME_HFS_CWS_NORMAL] = "Normal", [ME_HFS_CWS_WAIT] = "Platform Disable Wait", [ME_HFS_CWS_TRANS] = "OP State Transition", - [ME_HFS_CWS_INVALID] = "Invalid CPU Plugged In" + [ME_HFS_CWS_INVALID] = "Invalid CPU Plugged In", }; /* HFS1[8:6] Current Operation State Values */ diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c index 35ce5c47..5e69fca 100644 --- a/src/southbridge/intel/lynxpoint/pcie.c +++ b/src/southbridge/intel/lynxpoint/pcie.c @@ -502,14 +502,10 @@ static void pch_pcie_early(struct device *dev) { - int rp; - int do_aspm; - int is_lp; struct southbridge_intel_lynxpoint_config *config = dev->chip_info; - - rp = root_port_number(dev); - do_aspm = 0; - is_lp = pch_is_lp(); + int do_aspm = 0; + int rp = root_port_number(dev); + int is_lp = pch_is_lp(); if (is_lp) { switch (rp) { @@ -517,18 +513,24 @@ case 2: case 3: case 4: - /* Bits 31:28 of b0d28f0 0x32c register correspnd to - * Root Ports 4:1. */ + /* + * Bits 31:28 of b0d28f0 0x32c register correspond to + * Root Ports 4:1. + */ do_aspm = !!(rpc.b0d28f0_32c & (1 << (28 + rp - 1))); break; case 5: - /* Bit 28 of b0d28f4 0x32c register correspnd to - * Root Ports 4:1. */ + /* + * Bit 28 of b0d28f4 0x32c register correspond to + * Root Ports 4:1. + */ do_aspm = !!(rpc.b0d28f4_32c & (1 << 28)); break; case 6: - /* Bit 28 of b0d28f5 0x32c register correspnd to - * Root Ports 4:1. */ + /* + * Bit 28 of b0d28f5 0x32c register correspond to + * Root Ports 4:1. + */ do_aspm = !!(rpc.b0d28f5_32c & (1 << 28)); break; } @@ -538,16 +540,20 @@ case 2: case 3: case 4: - /* Bits 31:28 of b0d28f0 0x32c register correspnd to - * Root Ports 4:1. */ + /* + * Bits 31:28 of b0d28f0 0x32c register correspond to + * Root Ports 4:1. + */ do_aspm = !!(rpc.b0d28f0_32c & (1 << (28 + rp - 1))); break; case 5: case 6: case 7: case 8: - /* Bit 31:28 of b0d28f4 0x32c register correspnd to - * Root Ports 8:5. */ + /* + * Bits 31:28 of b0d28f4 0x32c register correspond to + * Root Ports 8:5. + */ do_aspm = !!(rpc.b0d28f4_32c & (1 << (28 + rp - 5))); break; } @@ -644,7 +650,7 @@ pci_or_config32(dev, 0x64, 1 << 11); pci_update_config32(dev, 0x68, ~(1 << 10), (1 << 10)); - pci_update_config32(dev, 0x318, ~(0xffffUL << 16), (0x1414UL << 16)); + pci_update_config32(dev, 0x318, ~(0xffff << 16), (0x1414 << 16)); /* Set L1 exit latency in LCAP register. */ if (!do_aspm && (pci_read_config8(dev, 0xf5) & 0x1)) @@ -659,7 +665,7 @@ pci_update_config32(dev, 0x33c, ~0x00ffffff, 0x854c74); - /* Set Invalid Recieve Range Check Enable in MPC register. */ + /* Set Invalid Receive Range Check Enable in MPC register. */ pci_or_config32(dev, 0xd8, 1 << 25); pci_and_config8(dev, 0xf5, 0x3f); @@ -683,7 +689,7 @@ pci_update_config32(dev, 0x90, ~0, 0); } -static void pci_init(struct device *dev) +static void pch_pcie_init(struct device *dev) { printk(BIOS_DEBUG, "Initializing PCH PCIe bridge.\n"); @@ -728,7 +734,7 @@ .read_resources = pci_bus_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_bus_enable_resources, - .init = pci_init, + .init = pch_pcie_init, .enable = pch_pcie_enable, .scan_bus = pciexp_scan_bridge, .ops_pci = &pci_dev_ops_pci, diff --git a/src/southbridge/intel/lynxpoint/pmutil.c b/src/southbridge/intel/lynxpoint/pmutil.c index af7a2b2..7b84689 100644 --- a/src/southbridge/intel/lynxpoint/pmutil.c +++ b/src/southbridge/intel/lynxpoint/pmutil.c @@ -33,8 +33,8 @@ if (!status) return; - for (i=31; i>=0; i--) { - if (status & (1UL << i)) { + for (i = 31; i >= 0; i--) { + if (status & (1 << i)) { if (bit_names[i]) printk(BIOS_DEBUG, "%s ", bit_names[i]); else @@ -51,7 +51,7 @@ if (!status) return; - for (i=31; i>=0; i--) { + for (i = 31; i >= 0; i--) { if (status & (1 << i)) printk(BIOS_DEBUG, "GPIO%d ", start + i); } diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c index f5c5f2a..9a5e5c0 100644 --- a/src/southbridge/intel/lynxpoint/smihandler.c +++ b/src/southbridge/intel/lynxpoint/smihandler.c @@ -86,7 +86,7 @@ u8 s5pwr = CONFIG_MAINBOARD_POWER_FAILURE_STATE; u16 pmbase = get_pmbase(); - // save and recover RTC port values + /* save and recover RTC port values */ u8 tmp70, tmp72; tmp70 = inb(0x70); tmp72 = inb(0x72); @@ -145,11 +145,10 @@ * "KEEP", switch to "OFF" - KEEP is software emulated */ reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3); - if (s5pwr == MAINBOARD_POWER_ON) { + if (s5pwr == MAINBOARD_POWER_ON) reg8 &= ~1; - } else { + else reg8 |= 1; - } pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8); /* also iterates over all bridges on bus 0 */ @@ -160,7 +159,8 @@ break; } - /* Write back to the SLP register to cause the originally intended + /* + * Write back to the SLP register to cause the originally intended * event again. We need to set BIT13 (SLP_EN) though to make the * sleep happen. */ @@ -170,7 +170,8 @@ if (slp_typ >= ACPI_S3) halt(); - /* In most sleep states, the code flow of this function ends at + /* + * In most sleep states, the code flow of this function ends at * the line above. However, if we entered sleep state S1 and wake * up again, we will continue to execute code in this function. */ @@ -228,11 +229,11 @@ return; /* Command and return value in EAX */ - ret = (u32*)&io_smi->rax; + ret = (u32 *)&io_smi->rax; sub_command = (u8)(*ret >> 8); /* Parameter buffer in EBX */ - param = (u32*)&io_smi->rbx; + param = (u32 *)&io_smi->rbx; /* drivers/elog/gsmi.c */ *ret = gsmi_exec(sub_command, param); @@ -345,7 +346,7 @@ * on a power button event. */ if (pm1_sts & PWRBTN_STS) { - // power button pressed + /* power button pressed */ elog_gsmi_add_event(ELOG_TYPE_POWER_BUTTON); disable_pm1_control(-1UL); enable_pm1_control(SLP_EN | (SLP_TYP_S5 << 10)); @@ -367,9 +368,7 @@ static void southbridge_smi_mc(void) { - u32 reg32; - - reg32 = inl(get_pmbase() + SMI_EN); + u32 reg32 = inl(get_pmbase() + SMI_EN); /* Are microcontroller SMIs enabled? */ if ((reg32 & MCSMI_EN) == 0) @@ -386,17 +385,16 @@ if (!tco_sts) return; - if (tco_sts & (1 << 8)) { // BIOSWR - u8 bios_cntl; - - bios_cntl = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0xdc); + // BIOSWR + if (tco_sts & (1 << 8)) { + u8 bios_cntl = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0xdc); if (bios_cntl & 1) { - /* BWE is RW, so the SMI was caused by a + /* + * BWE is RW, so the SMI was caused by a * write to BWE, not by a write to the BIOS - */ - - /* This is the place where we notice someone + * + * This is the place where we notice someone * is trying to tinker with the BIOS. We are * trying to be nice and just ignore it. A more * resolute answer would be to power down the @@ -413,9 +411,7 @@ static void southbridge_smi_periodic(void) { - u32 reg32; - - reg32 = inl(get_pmbase() + SMI_EN); + u32 reg32 = inl(get_pmbase() + SMI_EN); /* Are periodic SMIs enabled? */ if ((reg32 & PERIODIC_EN) == 0) @@ -435,7 +431,7 @@ RCBA32(0x1e00) = trap_sts; // Clear trap(s) in TRSR trap_cycle = RCBA32(0x1e10); - for (i=16; i<20; i++) { + for (i = 16; i < 20; i++) { if (trap_cycle & (1 << i)) mask |= (0xff << ((i - 16) << 2)); } @@ -452,7 +448,8 @@ /* IOTRAP(0) SMIC */ if (IOTRAP(0)) { - if (!(trap_cycle & (1 << 24))) { // It's a write + // It's a write + if (!(trap_cycle & (1 << 24))) { printk(BIOS_DEBUG, "SMI1 command\n"); (void)RCBA32(0x1e18); // data = RCBA32(0x1e18); @@ -466,8 +463,9 @@ printk(BIOS_DEBUG, " trapped io address = 0x%x\n", trap_cycle & 0xfffc); - for (i=0; i < 4; i++) - if (IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i); + for (i = 0; i < 4; i++) + if (IOTRAP(i)) + printk(BIOS_DEBUG, " TRAP = %d\n", i); printk(BIOS_DEBUG, " AHBE = %x\n", (trap_cycle >> 16) & 0xf); printk(BIOS_DEBUG, " MASK = 0x%08x\n", mask); printk(BIOS_DEBUG, " read/write: %s\n", -- To view, visit https://review.coreboot.org/c/coreboot/+/45698 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibd8430352e860ffc0e2030fd7bc73582982f4695 Gerrit-Change-Number: 45698 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

5 5

Change in coreboot[master]: soc/intel/broadwell: Align cosmetics with Haswell/Lynx Point
by Angel Pons (Code Review) 14 Oct '20

14 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45697 ) Change subject: soc/intel/broadwell: Align cosmetics with Haswell/Lynx Point ...................................................................... soc/intel/broadwell: Align cosmetics with Haswell/Lynx Point Tested with BUILD_TIMELESS=1, Purism Librem 13v1 does not change. Change-Id: Icf41d9db20e492ec77a83f8413ac99a654d6c8ed Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/broadwell/acpi/lpc.asl M src/soc/intel/broadwell/fadt.c M src/soc/intel/broadwell/memmap.c M src/soc/intel/broadwell/minihd.c M src/soc/intel/broadwell/pch.c M src/soc/intel/broadwell/pcie.c M src/soc/intel/broadwell/pmutil.c M src/soc/intel/broadwell/smbus.c M src/soc/intel/broadwell/smihandler.c 9 files changed, 59 insertions(+), 75 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/45697/1 diff --git a/src/soc/intel/broadwell/acpi/lpc.asl b/src/soc/intel/broadwell/acpi/lpc.asl index 33c8dc9..5bdfea2 100644 --- a/src/soc/intel/broadwell/acpi/lpc.asl +++ b/src/soc/intel/broadwell/acpi/lpc.asl @@ -81,9 +81,7 @@ Method (_CRS, 0, Serialized) // Current resources { If (HPTE) { - CreateDWordField (BUF0, - \_SB.PCI0.LPCB.HPET.FED0._BAS, HPT0) - + CreateDWordField (BUF0, \_SB.PCI0.LPCB.HPET.FED0._BAS, HPT0) If (Lequal(HPAS, 1)) { Add(CONFIG_HPET_ADDRESS, 0x1000, HPT0) } @@ -153,8 +151,7 @@ IO (Decode16, 0x80, 0x80, 0x1, 0x01) // Port 80 Post IO (Decode16, 0x92, 0x92, 0x1, 0x01) // CPU Reserved IO (Decode16, 0xb2, 0xb2, 0x1, 0x02) // SWSMI - IO (Decode16, ACPI_BASE_ADDRESS, ACPI_BASE_ADDRESS, - 0x1, 0xff) + IO (Decode16, ACPI_BASE_ADDRESS, ACPI_BASE_ADDRESS, 0x1, 0xff) }) Method (_CRS, 0, NotSerialized) @@ -169,7 +166,6 @@ Name (_CRS, ResourceTemplate() { IO (Decode16, 0x70, 0x70, 1, 8) - //IRQNoFlags() { 8 } }) } diff --git a/src/soc/intel/broadwell/fadt.c b/src/soc/intel/broadwell/fadt.c index f39ad80..8fbd0c4 100644 --- a/src/soc/intel/broadwell/fadt.c +++ b/src/soc/intel/broadwell/fadt.c @@ -38,10 +38,13 @@ fadt->century = 0x00; fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; - fadt->flags |= ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | - ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | - ACPI_FADT_SEALED_CASE | ACPI_FADT_S4_RTC_WAKE | - ACPI_FADT_PLATFORM_CLOCK; + fadt->flags |= ACPI_FADT_WBINVD | + ACPI_FADT_C1_SUPPORTED | + ACPI_FADT_C2_MP_SUPPORTED | + ACPI_FADT_SLEEP_BUTTON | + ACPI_FADT_SEALED_CASE | + ACPI_FADT_S4_RTC_WAKE | + ACPI_FADT_PLATFORM_CLOCK; fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8; @@ -82,5 +85,5 @@ fadt->x_gpe0_blk.bit_offset = 0; fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; fadt->x_gpe0_blk.addrl = fadt->gpe0_blk; - fadt->x_gpe0_blk.addrh = 0; + fadt->x_gpe0_blk.addrh = 0x0; } diff --git a/src/soc/intel/broadwell/memmap.c b/src/soc/intel/broadwell/memmap.c index 4673cce..fb9a834 100644 --- a/src/soc/intel/broadwell/memmap.c +++ b/src/soc/intel/broadwell/memmap.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +/* Use simple device model for this file even in ramstage */ #define __SIMPLE_DEVICE__ #include <cbmem.h> diff --git a/src/soc/intel/broadwell/minihd.c b/src/soc/intel/broadwell/minihd.c index b91d73d..a39c496 100644 --- a/src/soc/intel/broadwell/minihd.c +++ b/src/soc/intel/broadwell/minihd.c @@ -12,30 +12,30 @@ static const u32 minihd_verb_table[] = { /* coreboot specific header */ - 0x80862808, // Codec Vendor / Device ID: Intel Broadwell Mini-HD - 0x80860101, // Subsystem ID - 0x00000004, // Number of jacks + 0x80862808, /* Codec Vendor / Device ID: Intel Broadwell Mini-HD */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of jacks */ /* Enable 3rd Pin and Converter Widget */ 0x00878101, /* Pin Widget 5 - PORT B */ - 0x00571C10, - 0x00571D00, - 0x00571E56, - 0x00571F18, + 0x00571c10, + 0x00571d00, + 0x00571e56, + 0x00571f18, /* Pin Widget 6 - PORT C */ - 0x00671C20, - 0x00671D00, - 0x00671E56, - 0x00671F18, + 0x00671c20, + 0x00671d00, + 0x00671e56, + 0x00671f18, /* Pin Widget 7 - PORT D */ - 0x00771C30, - 0x00771D00, - 0x00771E56, - 0x00771F18, + 0x00771c30, + 0x00771d00, + 0x00771e56, + 0x00771f18, /* Disable 3rd Pin and Converter Widget */ 0x00878100, @@ -48,8 +48,8 @@ static void minihd_init(struct device *dev) { struct resource *res; - u8 *base; u32 reg32; + u8 *base; int codec_mask, i; /* Find base address */ @@ -80,8 +80,7 @@ if (codec_mask) { for (i = 3; i >= 0; i--) { if (codec_mask & (1 << i)) - hda_codec_init(base, i, - sizeof(minihd_verb_table), + hda_codec_init(base, i, sizeof(minihd_verb_table), minihd_verb_table); } } @@ -92,10 +91,10 @@ } static struct device_operations minihd_ops = { - .read_resources = &pci_dev_read_resources, - .set_resources = &pci_dev_set_resources, - .enable_resources = &pci_dev_enable_resources, - .init = &minihd_init, + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = minihd_init, .ops_pci = &broadwell_pci_ops, }; diff --git a/src/soc/intel/broadwell/pch.c b/src/soc/intel/broadwell/pch.c index 479323d..2a27d92 100644 --- a/src/soc/intel/broadwell/pch.c +++ b/src/soc/intel/broadwell/pch.c @@ -64,9 +64,7 @@ /* Put device in D3Hot Power State */ static void pch_enable_d3hot(struct device *dev) { - u32 reg32 = pci_read_config32(dev, PCH_PCS); - reg32 |= PCH_PCS_PS_D3HOT; - pci_write_config32(dev, PCH_PCS, reg32); + pci_or_config32(dev, PCH_PCS, PCH_PCS_PS_D3HOT); } /* RCBA function disable and posting read to flush the transaction */ diff --git a/src/soc/intel/broadwell/pcie.c b/src/soc/intel/broadwell/pcie.c index 00a8595..01ee068 100644 --- a/src/soc/intel/broadwell/pcie.c +++ b/src/soc/intel/broadwell/pcie.c @@ -18,7 +18,7 @@ #include <delay.h> /* Low Power variant has 6 root ports. */ -#define NUM_ROOT_PORTS 6 +#define MAX_NUM_ROOT_PORTS 6 struct root_port_config { /* RPFN is a write-once register so keep a copy until it is written */ @@ -34,7 +34,7 @@ int coalesce; int gbe_port; int num_ports; - struct device *ports[NUM_ROOT_PORTS]; + struct device *ports[MAX_NUM_ROOT_PORTS]; }; static struct root_port_config rpc; @@ -110,7 +110,7 @@ if (root_port_is_first(dev)) { rpc.orig_rpfn = RCBA32(RPFN); rpc.new_rpfn = rpc.orig_rpfn; - rpc.num_ports = NUM_ROOT_PORTS; + rpc.num_ports = MAX_NUM_ROOT_PORTS; rpc.gbe_port = -1; /* RP0 f5[3:0] = 0101b*/ pci_update_config8(dev, 0xf5, ~0xa, 0x5); @@ -473,8 +473,7 @@ if (do_aspm) { /* Set ASPM bits in MPC2 register. */ - pci_update_config32(dev, 0xd4, ~(0x3 << 2), - (1 << 4) | (0x2 << 2)); + pci_update_config32(dev, 0xd4, ~(0x3 << 2), (1 << 4) | (0x2 << 2)); /* Set unique clock exit latency in MPC register. */ pci_update_config32(dev, 0xd8, ~(0x7 << 18), (0x7 << 18)); @@ -526,7 +525,7 @@ else pci_update_config32(dev, 0x4c, ~(0x7 << 15), (0x2 << 15)); - pci_update_config32(dev, 0x314, 0x0, 0x743a361b); + pci_update_config32(dev, 0x314, 0, 0x743a361b); /* Set Common Clock Exit Latency in MPC register. */ pci_update_config32(dev, 0xd8, ~(0x7 << 15), (0x3 << 15)); @@ -572,8 +571,6 @@ static void pch_pcie_init(struct device *dev) { - u16 reg16; - printk(BIOS_DEBUG, "Initializing PCH PCIe bridge.\n"); /* Enable SERR */ @@ -585,15 +582,11 @@ /* Set Cache Line Size to 0x10 */ pci_write_config8(dev, 0x0c, 0x10); - reg16 = pci_read_config16(dev, PCI_BRIDGE_CONTROL); - reg16 &= ~PCI_BRIDGE_CTL_PARITY; - pci_write_config16(dev, PCI_BRIDGE_CONTROL, reg16); + pci_and_config16(dev, PCI_BRIDGE_CONTROL, ~PCI_BRIDGE_CTL_PARITY); /* Clear errors in status registers */ - reg16 = pci_read_config16(dev, 0x06); - pci_write_config16(dev, 0x06, reg16); - reg16 = pci_read_config16(dev, 0x1e); - pci_write_config16(dev, 0x1e, reg16); + pci_update_config16(dev, 0x06, ~0, 0); + pci_update_config16(dev, 0x1e, ~0, 0); } static void pch_pcie_enable(struct device *dev) diff --git a/src/soc/intel/broadwell/pmutil.c b/src/soc/intel/broadwell/pmutil.c index 92cf363..c96ed18 100644 --- a/src/soc/intel/broadwell/pmutil.c +++ b/src/soc/intel/broadwell/pmutil.c @@ -312,7 +312,7 @@ */ /* Clear a GPE0 status and return events that are enabled and active */ -static u32 reset_gpe(u16 sts_reg, u16 en_reg) +static u32 reset_gpe_status(u16 sts_reg, u16 en_reg) { u32 gpe0_sts = inl(ACPI_BASE_ADDRESS + sts_reg); u32 gpe0_en = inl(ACPI_BASE_ADDRESS + en_reg); @@ -366,10 +366,10 @@ [18] = "WADT" }; - print_gpe_gpio(reset_gpe(GPE0_STS(GPE_31_0), GPE0_EN(GPE_31_0)), 0); - print_gpe_gpio(reset_gpe(GPE0_STS(GPE_63_32), GPE0_EN(GPE_63_32)), 32); - print_gpe_gpio(reset_gpe(GPE0_STS(GPE_94_64), GPE0_EN(GPE_94_64)), 64); - return print_gpe_status(reset_gpe(GPE0_STS(GPE_STD), GPE0_EN(GPE_STD)), + print_gpe_gpio(reset_gpe_status(GPE0_STS(GPE_31_0), GPE0_EN(GPE_31_0)), 0); + print_gpe_gpio(reset_gpe_status(GPE0_STS(GPE_63_32), GPE0_EN(GPE_63_32)), 32); + print_gpe_gpio(reset_gpe_status(GPE0_STS(GPE_94_64), GPE0_EN(GPE_94_64)), 64); + return print_gpe_status(reset_gpe_status(GPE0_STS(GPE_STD), GPE0_EN(GPE_STD)), gpe0_sts_3_bits); } diff --git a/src/soc/intel/broadwell/smbus.c b/src/soc/intel/broadwell/smbus.c index 562db4e..31715c7 100644 --- a/src/soc/intel/broadwell/smbus.c +++ b/src/soc/intel/broadwell/smbus.c @@ -18,6 +18,7 @@ u16 reg16; /* Enable clock gating */ + /* FIXME: Using 32-bit ops with a 16-bit variable is a bug! These should be 16-bit! */ reg16 = pci_read_config32(dev, 0x80); reg16 &= ~((1 << 8)|(1 << 10)|(1 << 12)|(1 << 14)); pci_write_config32(dev, 0x80, reg16); diff --git a/src/soc/intel/broadwell/smihandler.c b/src/soc/intel/broadwell/smihandler.c index 1732ef7..4a12d78 100644 --- a/src/soc/intel/broadwell/smihandler.c +++ b/src/soc/intel/broadwell/smihandler.c @@ -58,25 +58,22 @@ for (slot = 0; slot < 0x20; slot++) { for (func = 0; func < 8; func++) { - u16 reg16; - pci_devfn_t dev = PCI_DEV(bus, slot, func); + val = pci_read_config32(dev, PCI_VENDOR_ID); if (val == 0xffffffff || val == 0x00000000 || - val == 0x0000ffff || val == 0xffff0000) + val == 0x0000ffff || val == 0xffff0000) continue; /* Disable Bus Mastering for this one device */ - reg16 = pci_read_config16(dev, PCI_COMMAND); - reg16 &= ~PCI_COMMAND_MASTER; - pci_write_config16(dev, PCI_COMMAND, reg16); + pci_and_config16(dev, PCI_COMMAND, ~PCI_COMMAND_MASTER); /* If this is a bridge, then follow it. */ hdr = pci_read_config8(dev, PCI_HEADER_TYPE); hdr &= 0x7f; if (hdr == PCI_HEADER_TYPE_BRIDGE || - hdr == PCI_HEADER_TYPE_CARDBUS) { + hdr == PCI_HEADER_TYPE_CARDBUS) { unsigned int buses; buses = pci_read_config32(dev, PCI_PRIMARY_BUS); busmaster_disable_on_bus((buses >> 8) & 0xff); @@ -249,11 +246,11 @@ for (node = 0; node < CONFIG_MAX_CPUS; node++) { state = smm_get_save_state(node); - /* Check for Synchronous IO (bit0==1) */ + /* Check for Synchronous IO (bit0 == 1) */ if (!(state->io_misc_info & (1 << 0))) continue; - /* Make sure it was a write (bit4==0) */ + /* Make sure it was a write (bit4 == 0) */ if (state->io_misc_info & (1 << 4)) continue; @@ -429,8 +426,7 @@ * box. */ printk(BIOS_DEBUG, "Switching back to RO\n"); - pci_write_config32(PCH_DEV_LPC, BIOS_CNTL, - (bios_cntl & ~1)); + pci_write_config32(PCH_DEV_LPC, BIOS_CNTL, (bios_cntl & ~1)); } /* No else for now? */ } else if (tco_sts & (1 << 3)) { /* TIMEOUT */ /* Handle TCO timeout */ @@ -453,7 +449,7 @@ { #define IOTRAP(x) (trap_sts & (1 << x)) u32 trap_sts, trap_cycle; - u32 data, mask = 0; + u32 mask = 0; int i; trap_sts = RCBA32(0x1e00); // TRSR - Trap Status Register @@ -480,8 +476,9 @@ // It's a write if (!(trap_cycle & (1 << 24))) { printk(BIOS_DEBUG, "SMI1 command\n"); - data = RCBA32(0x1e18); - data &= mask; + (void)RCBA32(0x1e18); + // data = RCBA32(0x1e18); + // data &= mask; // if (smi1) // southbridge_smi_command(data); // return; @@ -501,8 +498,7 @@ if (!(trap_cycle & (1 << 24))) { /* Write Cycle */ - data = RCBA32(0x1e18); - printk(BIOS_DEBUG, " iotrap written data = 0x%08x\n", data); + printk(BIOS_DEBUG, " iotrap written data = 0x%08x\n", RCBA32(0x1e18)); } #undef IOTRAP } @@ -546,10 +542,7 @@ /** * @brief Interrupt handler for SMI# - * - * @param smm_revision revision of the smm state save map */ - void southbridge_smi_handler(void) { int i; -- To view, visit https://review.coreboot.org/c/coreboot/+/45697 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icf41d9db20e492ec77a83f8413ac99a654d6c8ed Gerrit-Change-Number: 45697 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

4 4

Change in coreboot[master]: soc/intel/broadwell/igd.c: Rename to gma.c
by Angel Pons (Code Review) 14 Oct '20

14 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46323 ) Change subject: soc/intel/broadwell/igd.c: Rename to gma.c ...................................................................... soc/intel/broadwell/igd.c: Rename to gma.c This makes comparisons against Haswell a bit simpler. Change-Id: If1c937628f702c6765a5f36b6eaf4a3c3516359a Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/broadwell/Makefile.inc R src/soc/intel/broadwell/gma.c 2 files changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/46323/1 diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc index 28b7c29..786fe2a 100644 --- a/src/soc/intel/broadwell/Makefile.inc +++ b/src/soc/intel/broadwell/Makefile.inc @@ -28,7 +28,7 @@ romstage-y += gpio.c smm-y += gpio.c ramstage-y += hda.c -ramstage-y += igd.c +ramstage-y += gma.c ramstage-y += iobp.c romstage-y += iobp.c ramstage-y += fadt.c diff --git a/src/soc/intel/broadwell/igd.c b/src/soc/intel/broadwell/gma.c similarity index 100% rename from src/soc/intel/broadwell/igd.c rename to src/soc/intel/broadwell/gma.c -- To view, visit https://review.coreboot.org/c/coreboot/+/46323 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If1c937628f702c6765a5f36b6eaf4a3c3516359a Gerrit-Change-Number: 46323 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/skylake: Rename PcieRpAspm devicetree config
by Angel Pons (Code Review) 14 Oct '20

14 Oct '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45001 ) Change subject: soc/intel/skylake: Rename PcieRpAspm devicetree config ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/45001 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id74f043ecd549bde4501320bff1dc080bde64057 Gerrit-Change-Number: 45001 Gerrit-PatchSet: 5 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 14 Oct 2020 08:26:47 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/common: drop default to enable the PIT if SeaBIOS is chosen
by Gerd Hoffmann (Code Review) 14 Oct '20

14 Oct '20

Gerd Hoffmann has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46301 ) Change subject: soc/intel/common: drop default to enable the PIT if SeaBIOS is chosen ...................................................................... Patch Set 1: Well. Sure that actually works? The pmtimer is used in case seabios runs on qemu and initializes the (virtual) acpi pci device. I doubt this also happens when running as coreboot payload. The TSC needs calibration, and seabios uses the PIT for that I think. Except when running virtualized on KVM, in that case (new enough) seabios can use kvmclock to figure the TSC frequency. -- To view, visit https://review.coreboot.org/c/coreboot/+/46301 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd75800678707a92110682347c7cfb93e25109a4 Gerrit-Change-Number: 46301 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Gerd Hoffmann <kraxel(a)redhat.com> Gerrit-Reviewer: Kevin O'Connor <kevin(a)koconnor.net> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 14 Oct 2020 08:17:25 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: nb/intel/haswell: Account for DPR region in memory map
by Arthur Heymans (Code Review) 14 Oct '20

14 Oct '20

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45712 ) Change subject: nb/intel/haswell: Account for DPR region in memory map ...................................................................... Patch Set 10: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/45712 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I11f23fd43188f987e35fd61f52587e567496cd78 Gerrit-Change-Number: 45712 Gerrit-PatchSet: 10 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 14 Oct 2020 07:31:00 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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