Change in coreboot[master]: haswell/lynxpoint: Align cosmetics with Broadwell - coreboot-gerrit

24 Sep 2020

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45698 )
Change subject: haswell/lynxpoint: Align cosmetics with Broadwell
......................................................................
haswell/lynxpoint: Align cosmetics with Broadwell
Tested with BUILD_TIMELESS=1, Google Wolf does not change.
Change-Id: Ibd8430352e860ffc0e2030fd7bc73582982f4695
Signed-off-by: Angel Pons th3fanbus@gmail.com
---
M src/cpu/intel/haswell/acpi.c
M src/cpu/intel/haswell/smmrelocate.c
M src/southbridge/intel/lynxpoint/acpi/globalnvs.asl
M src/southbridge/intel/lynxpoint/acpi/lpc.asl
M src/southbridge/intel/lynxpoint/acpi/pch.asl
M src/southbridge/intel/lynxpoint/acpi/serialio.asl
M src/southbridge/intel/lynxpoint/chip.h
M src/southbridge/intel/lynxpoint/elog.c
M src/southbridge/intel/lynxpoint/lpc.c
M src/southbridge/intel/lynxpoint/me_status.c
M src/southbridge/intel/lynxpoint/pcie.c
M src/southbridge/intel/lynxpoint/pmutil.c
M src/southbridge/intel/lynxpoint/smihandler.c
13 files changed, 152 insertions(+), 151 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/45698/1

diff --git a/src/cpu/intel/haswell/acpi.c b/src/cpu/intel/haswell/acpi.c
index 676acce..6dd8559 100644
--- a/src/cpu/intel/haswell/acpi.c
+++ b/src/cpu/intel/haswell/acpi.c
@@ -65,50 +65,6 @@
    acpigen_pop_len();
 }
-static void generate_C_state_entries(void)
-{
-	struct cpu_info *info;
-	struct cpu_driver *cpu;
-	struct device *lapic;
-	struct cpu_intel_haswell_config *conf = NULL;
-
-	/* Find the SpeedStep CPU in the device tree using magic APIC ID */
-	lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC);
-	if (!lapic)
-		return;
-	conf = lapic->chip_info;
-	if (!conf)
-		return;
-
-	/* Find CPU map of supported C-states */
-	info = cpu_info();
-	if (!info)
-		return;
-	cpu = find_cpu_driver(info->cpu);
-	if (!cpu || !cpu->cstates)
-		return;
-
-	acpigen_emit_byte(0x14);		/* MethodOp */
-	acpigen_write_len_f();		/* PkgLength */
-	acpigen_emit_namestring("_CST");
-	acpigen_emit_byte(0x00);		/* No Arguments */
-
-	/* If running on AC power */
-	acpigen_emit_byte(0xa0);		/* IfOp */
-	acpigen_write_len_f();		/* PkgLength */
-	acpigen_emit_namestring("PWRS");
-	acpigen_emit_byte(0xa4);	/* ReturnOp */
-	generate_cstate_entries(cpu->cstates, conf->c1_acpower,
-					 conf->c2_acpower, conf->c3_acpower);
-	acpigen_pop_len();
-
-	/* Else on battery power */
-	acpigen_emit_byte(0xa4);	/* ReturnOp */
-	generate_cstate_entries(cpu->cstates, conf->c1_battery,
-					conf->c2_battery, conf->c3_battery);
-	acpigen_pop_len();
-}
-
 static acpi_tstate_t tss_table_fine[] = {
    { 100, 1000, 0, 0x00, 0 },
    { 94, 940, 0, 0x1f, 0 },
@@ -161,6 +117,50 @@
    		ARRAY_SIZE(tss_table_coarse), tss_table_coarse);
 }
+static void generate_C_state_entries(void)
+{
+	struct cpu_info *info;
+	struct cpu_driver *cpu;
+	struct device *lapic;
+	struct cpu_intel_haswell_config *conf = NULL;
+
+	/* Find the SpeedStep CPU in the device tree using magic APIC ID */
+	lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC);
+	if (!lapic)
+		return;
+	conf = lapic->chip_info;
+	if (!conf)
+		return;
+
+	/* Find CPU map of supported C-states */
+	info = cpu_info();
+	if (!info)
+		return;
+	cpu = find_cpu_driver(info->cpu);
+	if (!cpu || !cpu->cstates)
+		return;
+
+	acpigen_emit_byte(0x14);		/* MethodOp */
+	acpigen_write_len_f();		/* PkgLength */
+	acpigen_emit_namestring("_CST");
+	acpigen_emit_byte(0x00);		/* No Arguments */
+
+	/* If running on AC power */
+	acpigen_emit_byte(0xa0);		/* IfOp */
+	acpigen_write_len_f();		/* PkgLength */
+	acpigen_emit_namestring("PWRS");
+	acpigen_emit_byte(0xa4);	/* ReturnOp */
+	generate_cstate_entries(cpu->cstates, conf->c1_acpower,
+					 conf->c2_acpower, conf->c3_acpower);
+	acpigen_pop_len();
+
+	/* Else on battery power */
+	acpigen_emit_byte(0xa4);	/* ReturnOp */
+	generate_cstate_entries(cpu->cstates, conf->c1_battery,
+					conf->c2_battery, conf->c3_battery);
+	acpigen_pop_len();
+}
+
 static int calculate_power(int tdp, int p1_ratio, int ratio)
 {
    u32 m;
@@ -307,19 +307,19 @@
/* Generate processor _SB.CPUx */
    		acpigen_write_processor(
-				(cpuID-1)*cores_per_package+coreID-1,
+				(cpuID - 1) * cores_per_package+coreID - 1,
    			pcontrol_blk, plen);
/* Generate P-state tables */
    		generate_P_state_entries(
-				coreID-1, cores_per_package);
+				coreID - 1, cores_per_package);
/* Generate C-state tables */
    		generate_C_state_entries();
/* Generate T-state tables */
    		generate_T_state_entries(
-				cpuID-1, cores_per_package);
+				cpuID - 1, cores_per_package);
acpigen_pop_len();
    	}
diff --git a/src/cpu/intel/haswell/smmrelocate.c b/src/cpu/intel/haswell/smmrelocate.c
index 39e71fe..3f9345f 100644
--- a/src/cpu/intel/haswell/smmrelocate.c
+++ b/src/cpu/intel/haswell/smmrelocate.c
@@ -156,7 +156,6 @@
 {
    uintptr_t tseg_base;
    size_t tseg_size;
-
    u32 prmrr_base;
    u32 prmrr_size;
    int phys_bits;
@@ -197,7 +196,7 @@
    params->uncore_prmrr_base.lo = prmrr_base;
    params->uncore_prmrr_base.hi = 0;
    params->uncore_prmrr_mask.lo = (~(prmrr_size - 1) & rmask) |
-				      MTRR_PHYS_MASK_VALID;
+					MTRR_PHYS_MASK_VALID;
    params->uncore_prmrr_mask.hi = (1 << (39 - 32)) - 1;
 }
@@ -282,6 +281,5 @@
     * make the SMM registers writable again.
     */
    printk(BIOS_DEBUG, "Locking SMM.\n");
-	pci_write_config8(pcidev_on_root(0, 0), SMRAM,
-			D_LCK | G_SMRAME | C_BASE_SEG);
+	pci_write_config8(pcidev_on_root(0, 0), SMRAM, D_LCK | G_SMRAME | C_BASE_SEG);
 }
diff --git a/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl b/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl
index 16c4b75..ee2d800 100644
--- a/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl
+++ b/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl
@@ -2,9 +2,10 @@
/* Global Variables */
-Name(\PICM, 0)		// IOAPIC/8259
+Name (\PICM, 0)		// IOAPIC/8259
-/* Global ACPI memory region. This region is used for passing information
+/*
+ * Global ACPI memory region. This region is used for passing information
  * between coreboot (aka "the system bios"), ACPI, and the SMI handler.
  * Since we don't know where this will end up in memory at ACPI compile time,
  * we have to fix it up in coreboot's ACPI creation phase.
@@ -31,9 +32,9 @@
    PWRS,	 8,	// 0x10 - Power State (AC = 1)
    /* Thermal policy */
    Offset (0x11),
-	TLVL,    8,	// 0x11 - Throttle Level Limit
+	TLVL,	 8,	// 0x11 - Throttle Level Limit
    FLVL,	 8,	// 0x12 - Current FAN Level
-	TCRT,    8,	// 0x13 - Critical Threshold
+	TCRT,	 8,	// 0x13 - Critical Threshold
    TPSV,	 8,	// 0x14 - Passive Threshold
    TMAX,	 8,	// 0x15 - CPU Tj_max
    F0OF,	 8,	// 0x16 - FAN 0 OFF Threshold
@@ -51,7 +52,7 @@
    F4OF,	 8,	// 0x22 - FAN 4 OFF Threshold
    F4ON,	 8,	// 0x23 - FAN 4 ON Threshold
    F4PW,	 8,	// 0x24 - FAN 4 PWM value
-	TMPS,    8,	// 0x25 - Temperature Sensor ID
+	TMPS,	 8,	// 0x25 - Temperature Sensor ID
    /* Processor Identification */
    Offset (0x28),
    APIC,	 8,	// 0x28 - APIC Enabled by coreboot
diff --git a/src/southbridge/intel/lynxpoint/acpi/lpc.asl b/src/southbridge/intel/lynxpoint/acpi/lpc.asl
index 1e9de3c..bc1d73c 100644
--- a/src/southbridge/intel/lynxpoint/acpi/lpc.asl
+++ b/src/southbridge/intel/lynxpoint/acpi/lpc.asl
@@ -4,7 +4,7 @@
Device (LPCB)
 {
-	Name(_ADR, 0x001f0000)
+	Name (_ADR, 0x001f0000)
OperationRegion(LPC0, PCI_Config, 0x00, 0x100)
    Field (LPC0, AnyAcc, NoLock, Preserve)
@@ -14,7 +14,7 @@
    	Offset (0x40),
    	PMBS,	16,	// PMBASE
    	Offset (0x48),
-		GPBS,   16,	// GPIOBASE
+		GPBS,	16,	// GPIOBASE
    	Offset (0x60),	// Interrupt Routing Registers
    	PRTA,	8,
    	PRTB,	8,
@@ -40,10 +40,10 @@
#include "acpi/ec.asl"
-	Device (DMAC)		// DMA Controller
+	Device (DMAC)	// DMA Controller
    {
-		Name(_HID, EISAID("PNP0200"))
-		Name(_CRS, ResourceTemplate()
+		Name (_HID, EISAID("PNP0200"))
+		Name (_CRS, ResourceTemplate()
    	{
    		IO (Decode16, 0x00, 0x00, 0x01, 0x20)
    		IO (Decode16, 0x81, 0x81, 0x01, 0x11)
@@ -53,7 +53,7 @@
    	})
    }
-	Device (FWH)		// Firmware Hub
+	Device (FWH)	// Firmware Hub
    {
    	Name (_HID, EISAID("INT0800"))
    	Name (_CRS, ResourceTemplate()
@@ -67,7 +67,7 @@
    	Name (_HID, EISAID("PNP0103"))
    	Name (_CID, 0x010CD041)
-		Name(BUF0, ResourceTemplate()
+		Name (BUF0, ResourceTemplate()
    	{
    		Memory32Fixed(ReadOnly, CONFIG_HPET_ADDRESS, 0x400, FED0)
    	})
@@ -90,7 +90,7 @@
    	Method (_CRS, 0, Serialized) // Current resources
    	{
    		If (HPTE) {
-				CreateDWordField(BUF0, _SB.PCI0.LPCB.HPET.FED0._BAS, HPT0)
+				CreateDWordField (BUF0, _SB.PCI0.LPCB.HPET.FED0._BAS, HPT0)
    			If (Lequal(HPAS, 1)) {
    				Add(CONFIG_HPET_ADDRESS, 0x1000, HPT0)
    			}
@@ -110,8 +110,8 @@
Device(PIC)	// 8259 Interrupt Controller
    {
-		Name(_HID,EISAID("PNP0000"))
-		Name(_CRS, ResourceTemplate()
+		Name (_HID,EISAID("PNP0000"))
+		Name (_CRS, ResourceTemplate()
    	{
    		IO (Decode16, 0x20, 0x20, 0x01, 0x02)
    		IO (Decode16, 0x24, 0x24, 0x01, 0x02)
@@ -160,8 +160,7 @@
    		IO (Decode16, 0x80, 0x80, 0x1, 0x01) // Port 80 Post
    		IO (Decode16, 0x92, 0x92, 0x1, 0x01) // CPU Reserved
    		IO (Decode16, 0xb2, 0xb2, 0x1, 0x02) // SWSMI
-			IO (Decode16, DEFAULT_PMBASE, DEFAULT_PMBASE,
-			    0x1, 0xff)
+			IO (Decode16, DEFAULT_PMBASE, DEFAULT_PMBASE, 0x1, 0xff)
// GPIO region may be 128 bytes or 4096 bytes
    		IO (Decode16, 0x0000, 0x0000, 0x1, 0x00, GPR1)
@@ -197,9 +196,8 @@
Device (TIMR)	// Intel 8254 timer
    {
-		Name(_HID, EISAID("PNP0100"))
-		Name(_CRS, ResourceTemplate()
-		{
+		Name (_HID, EISAID("PNP0100"))
+		Name (_CRS, ResourceTemplate() {
    		IO (Decode16, 0x40, 0x40, 0x01, 0x04)
    		IO (Decode16, 0x50, 0x50, 0x10, 0x04)
    		IRQNoFlags() {0}
diff --git a/src/southbridge/intel/lynxpoint/acpi/pch.asl b/src/southbridge/intel/lynxpoint/acpi/pch.asl
index 154633d..4101985 100644
--- a/src/southbridge/intel/lynxpoint/acpi/pch.asl
+++ b/src/southbridge/intel/lynxpoint/acpi/pch.asl
@@ -1,8 +1,8 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
-/* Intel Cougar Point PCH support */
+/* Intel Lynx Point PCH support */
-Scope()
+Scope ()
 {
    // Return TRUE if chipset is LynxPoint-LP
    Method (ISLP, 0, NotSerialized)
@@ -11,17 +11,16 @@
    }
// IO-Trap at 0x800. This is the ACPI->SMI communication interface.
-
-	OperationRegion(IO_T, SystemIO, 0x800, 0x10)
-	Field(IO_T, ByteAcc, NoLock, Preserve)
+	OperationRegion (IO_T, SystemIO, 0x800, 0x10)
+	Field (IO_T, ByteAcc, NoLock, Preserve)
    {
-		Offset(0x8),
+		Offset (0x8),
    	TRP0, 8		// IO-Trap at 0x808
    }
-	// ICH7 Root Complex Register Block. Memory Mapped through RCBA)
-	OperationRegion(RCRB, SystemMemory, DEFAULT_RCBA, 0x4000)
-	Field(RCRB, DWordAcc, Lock, Preserve)
+	// Root Complex Register Block
+	OperationRegion (RCRB, SystemMemory, DEFAULT_RCBA, 0x4000)
+	Field (RCRB, DWordAcc, Lock, Preserve)
    {
    	Offset(0x0000), // Backbone
    	Offset(0x1000), // Chipset
diff --git a/src/southbridge/intel/lynxpoint/acpi/serialio.asl b/src/southbridge/intel/lynxpoint/acpi/serialio.asl
index 83bc6eb..7acd30d 100644
--- a/src/southbridge/intel/lynxpoint/acpi/serialio.asl
+++ b/src/southbridge/intel/lynxpoint/acpi/serialio.asl
@@ -116,7 +116,7 @@
    Name (RBUF, ResourceTemplate ()
    {
    	Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0)
-		Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , ,) {7}
+		Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) {7}
    })
Method (_CRS, 0, NotSerialized)
@@ -156,7 +156,7 @@
    Name (RBUF, ResourceTemplate ()
    {
    	Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0)
-		Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , ,) {7}
+		Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) {7}
    })
// DMA channels are only used if Serial IO DMA controller is enabled
@@ -237,7 +237,7 @@
    Name (RBUF, ResourceTemplate ()
    {
    	Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0)
-		Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , ,) {7}
+		Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) {7}
    })
// DMA channels are only used if Serial IO DMA controller is enabled
@@ -315,7 +315,7 @@
    Name (RBUF, ResourceTemplate ()
    {
    	Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0)
-		Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , ,) {7}
+		Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) {7}
    })
Method (_CRS, 0, NotSerialized)
@@ -352,7 +352,7 @@
    Name (RBUF, ResourceTemplate ()
    {
    	Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0)
-		Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , ,) {7}
+		Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) {7}
    })
// DMA channels are only used if Serial IO DMA controller is enabled
@@ -402,7 +402,7 @@
    Name (RBUF, ResourceTemplate ()
    {
    	Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0)
-		Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , ,) {13}
+		Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) {13}
    })
// DMA channels are only used if Serial IO DMA controller is enabled
@@ -452,7 +452,7 @@
    Name (RBUF, ResourceTemplate ()
    {
    	Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0)
-		Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , ,) {13}
+		Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) {13}
    })
Method (_CRS, 0, NotSerialized)
@@ -489,7 +489,7 @@
    Name (RBUF, ResourceTemplate ()
    {
    	Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0)
-		Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , ,) {5}
+		Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) {5}
    })
Method (_CRS, 0, NotSerialized)
diff --git a/src/southbridge/intel/lynxpoint/chip.h b/src/southbridge/intel/lynxpoint/chip.h
index e30d4b4..40d0460 100644
--- a/src/southbridge/intel/lynxpoint/chip.h
+++ b/src/southbridge/intel/lynxpoint/chip.h
@@ -47,7 +47,8 @@
    uint32_t sata_port0_gen3_dtle;
    uint32_t sata_port1_gen3_dtle;
-	/* SATA DEVSLP Mux
+	/*
+	 * SATA DEVSLP Mux
     * 0 = port 0 DEVSLP on DEVSLP0/GPIO33
     * 1 = port 3 DEVSLP on DEVSLP0/GPIO33
     */
@@ -67,12 +68,13 @@
/* Enable linear PCIe Root Port function numbers starting at zero */
    uint8_t pcie_port_coalesce;
+
    /* Force root port ASPM configuration with port bitmap */
    uint8_t pcie_port_force_aspm;
-	/* Serial IO configuration */
-	/* Put devices into ACPI mode instead of a PCI device */
+	/* Put SerialIO devices into ACPI mode instead of a PCI device */
    uint8_t sio_acpi_mode;
+
    /* I2C voltage select: 0=3.3V 1=1.8V */
    uint8_t sio_i2c0_voltage;
    uint8_t sio_i2c1_voltage;
@@ -91,4 +93,4 @@
    bool docking_supported;
 };
-#endif				/* SOUTHBRIDGE_INTEL_LYNXPOINT_CHIP_H */
+#endif	/* SOUTHBRIDGE_INTEL_LYNXPOINT_CHIP_H */
diff --git a/src/southbridge/intel/lynxpoint/elog.c b/src/southbridge/intel/lynxpoint/elog.c
index 8146794..3ce765d 100644
--- a/src/southbridge/intel/lynxpoint/elog.c
+++ b/src/southbridge/intel/lynxpoint/elog.c
@@ -46,7 +46,7 @@
    u16 pmbase = get_pmbase();
    u32 gpe0_sts, gpe0_en;
    int gpe0_high_gpios[] = {
-		[0] = 27,
+		[0]  = 27,
    	[24] = 17,
    	[25] = 19,
    	[26] = 21,
diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c
index e561430..fad83b1 100644
--- a/src/southbridge/intel/lynxpoint/lpc.c
+++ b/src/southbridge/intel/lynxpoint/lpc.c
@@ -115,7 +115,7 @@
     */
for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
-		u8 int_pin=0, int_line=0;
+		u8 int_pin = 0, int_line = 0;
if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI)
    		continue;
@@ -446,7 +446,7 @@
    	reg32 &= ~(1 << 29); // LPC Dynamic
    else
    	reg32 |= (1 << 29); // LPC Dynamic
-	reg32 |= (1UL << 31); // LP LPC
+	reg32 |= (1 << 31); // LP LPC
    reg32 |= (1 << 30); // LP BLA
    reg32 |= (1 << 28); // GPIO Dynamic
    reg32 |= (1 << 27); // HPET Dynamic
@@ -565,7 +565,7 @@
    	res->base = (resource_t)(uintptr_t)DEFAULT_RCBA;
    	res->size = 16 * 1024;
    	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED |
-		             IORESOURCE_FIXED | IORESOURCE_RESERVE;
+			     IORESOURCE_FIXED | IORESOURCE_RESERVE;
    }
/* Check LPC Memory Decode register. */
@@ -577,7 +577,7 @@
    		res->base = reg;
    		res->size = 16 * 1024;
    		res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED |
-			             IORESOURCE_FIXED | IORESOURCE_RESERVE;
+				     IORESOURCE_FIXED | IORESOURCE_RESERVE;
    	}
    }
 }
@@ -645,8 +645,7 @@
    res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
/* GPIOBASE */
-	pch_lpc_add_io_resource(dev, get_gpiobase(), DEFAULT_GPIOSIZE,
-	                        GPIO_BASE);
+	pch_lpc_add_io_resource(dev, get_gpiobase(), DEFAULT_GPIOSIZE, GPIO_BASE);
/* PMBASE */
    pch_lpc_add_io_resource(dev, get_pmbase(), 256, PMBASE);
diff --git a/src/southbridge/intel/lynxpoint/me_status.c b/src/southbridge/intel/lynxpoint/me_status.c
index 045d960..82a8f8e 100644
--- a/src/southbridge/intel/lynxpoint/me_status.c
+++ b/src/southbridge/intel/lynxpoint/me_status.c
@@ -11,7 +11,7 @@
    [ME_HFS_CWS_NORMAL]	= "Normal",
    [ME_HFS_CWS_WAIT]	= "Platform Disable Wait",
    [ME_HFS_CWS_TRANS]	= "OP State Transition",
-	[ME_HFS_CWS_INVALID]	= "Invalid CPU Plugged In"
+	[ME_HFS_CWS_INVALID]	= "Invalid CPU Plugged In",
 };
/* HFS1[8:6] Current Operation State Values */
diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c
index 35ce5c47..5e69fca 100644
--- a/src/southbridge/intel/lynxpoint/pcie.c
+++ b/src/southbridge/intel/lynxpoint/pcie.c
@@ -502,14 +502,10 @@
static void pch_pcie_early(struct device *dev)
 {
-	int rp;
-	int do_aspm;
-	int is_lp;
    struct southbridge_intel_lynxpoint_config *config = dev->chip_info;
-
-	rp = root_port_number(dev);
-	do_aspm = 0;
-	is_lp = pch_is_lp();
+	int do_aspm = 0;
+	int rp = root_port_number(dev);
+	int is_lp = pch_is_lp();
if (is_lp) {
    	switch (rp) {
@@ -517,18 +513,24 @@
    	case 2:
    	case 3:
    	case 4:
-			/* Bits 31:28 of b0d28f0 0x32c register correspnd to
-			 * Root Ports 4:1. */
+			/*
+			 * Bits 31:28 of b0d28f0 0x32c register correspond to
+			 * Root Ports 4:1.
+			 */
    		do_aspm = !!(rpc.b0d28f0_32c & (1 << (28 + rp - 1)));
    		break;
    	case 5:
-			/* Bit 28 of b0d28f4 0x32c register correspnd to
-			 * Root Ports 4:1. */
+			/*
+			 * Bit 28 of b0d28f4 0x32c register correspond to
+			 * Root Ports 4:1.
+			 */
    		do_aspm = !!(rpc.b0d28f4_32c & (1 << 28));
    		break;
    	case 6:
-			/* Bit 28 of b0d28f5 0x32c register correspnd to
-			 * Root Ports 4:1. */
+			/*
+			 * Bit 28 of b0d28f5 0x32c register correspond to
+			 * Root Ports 4:1.
+			 */
    		do_aspm = !!(rpc.b0d28f5_32c & (1 << 28));
    		break;
    	}
@@ -538,16 +540,20 @@
    	case 2:
    	case 3:
    	case 4:
-			/* Bits 31:28 of b0d28f0 0x32c register correspnd to
-			 * Root Ports 4:1. */
+			/*
+			 * Bits 31:28 of b0d28f0 0x32c register correspond to
+			 * Root Ports 4:1.
+			 */
    		do_aspm = !!(rpc.b0d28f0_32c & (1 << (28 + rp - 1)));
    		break;
    	case 5:
    	case 6:
    	case 7:
    	case 8:
-			/* Bit 31:28 of b0d28f4 0x32c register correspnd to
-			 * Root Ports 8:5. */
+			/*
+			 * Bits 31:28 of b0d28f4 0x32c register correspond to
+			 * Root Ports 8:5.
+			 */
    		do_aspm = !!(rpc.b0d28f4_32c & (1 << (28 + rp - 5)));
    		break;
    	}
@@ -644,7 +650,7 @@
    pci_or_config32(dev, 0x64, 1 << 11);
    pci_update_config32(dev, 0x68, ~(1 << 10), (1 << 10));
-	pci_update_config32(dev, 0x318, ~(0xffffUL << 16), (0x1414UL << 16));
+	pci_update_config32(dev, 0x318, ~(0xffff << 16), (0x1414 << 16));
/* Set L1 exit latency in LCAP register. */
    if (!do_aspm && (pci_read_config8(dev, 0xf5) & 0x1))
@@ -659,7 +665,7 @@
pci_update_config32(dev, 0x33c, ~0x00ffffff, 0x854c74);
-	/* Set Invalid Recieve Range Check Enable in MPC register. */
+	/* Set Invalid Receive Range Check Enable in MPC register. */
    pci_or_config32(dev, 0xd8, 1 << 25);
pci_and_config8(dev, 0xf5, 0x3f);
@@ -683,7 +689,7 @@
    pci_update_config32(dev, 0x90, ~0, 0);
 }
-static void pci_init(struct device *dev)
+static void pch_pcie_init(struct device *dev)
 {
    printk(BIOS_DEBUG, "Initializing PCH PCIe bridge.\n");
@@ -728,7 +734,7 @@
    .read_resources		= pci_bus_read_resources,
    .set_resources		= pci_dev_set_resources,
    .enable_resources	= pci_bus_enable_resources,
-	.init			= pci_init,
+	.init			= pch_pcie_init,
    .enable			= pch_pcie_enable,
    .scan_bus		= pciexp_scan_bridge,
    .ops_pci		= &pci_dev_ops_pci,
diff --git a/src/southbridge/intel/lynxpoint/pmutil.c b/src/southbridge/intel/lynxpoint/pmutil.c
index af7a2b2..7b84689 100644
--- a/src/southbridge/intel/lynxpoint/pmutil.c
+++ b/src/southbridge/intel/lynxpoint/pmutil.c
@@ -33,8 +33,8 @@
    if (!status)
    	return;
-	for (i=31; i>=0; i--) {
-		if (status & (1UL << i)) {
+	for (i = 31; i >= 0; i--) {
+		if (status & (1 << i)) {
    		if (bit_names[i])
    			printk(BIOS_DEBUG, "%s ", bit_names[i]);
    		else
@@ -51,7 +51,7 @@
    if (!status)
    	return;
-	for (i=31; i>=0; i--) {
+	for (i = 31; i >= 0; i--) {
    	if (status & (1 << i))
    		printk(BIOS_DEBUG, "GPIO%d ", start + i);
    }
diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c
index f5c5f2a..9a5e5c0 100644
--- a/src/southbridge/intel/lynxpoint/smihandler.c
+++ b/src/southbridge/intel/lynxpoint/smihandler.c
@@ -86,7 +86,7 @@
    u8 s5pwr = CONFIG_MAINBOARD_POWER_FAILURE_STATE;
    u16 pmbase = get_pmbase();
-	// save and recover RTC port values
+	/* save and recover RTC port values */
    u8 tmp70, tmp72;
    tmp70 = inb(0x70);
    tmp72 = inb(0x72);
@@ -145,11 +145,10 @@
    	 * "KEEP", switch to "OFF" - KEEP is software emulated
    	 */
    	reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3);
-		if (s5pwr == MAINBOARD_POWER_ON) {
+		if (s5pwr == MAINBOARD_POWER_ON)
    		reg8 &= ~1;
-		} else {
+		else
    		reg8 |= 1;
-		}
    	pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8);
/* also iterates over all bridges on bus 0 */
@@ -160,7 +159,8 @@
    	break;
    }
-	/* Write back to the SLP register to cause the originally intended
+	/*
+	 * Write back to the SLP register to cause the originally intended
     * event again. We need to set BIT13 (SLP_EN) though to make the
     * sleep happen.
     */
@@ -170,7 +170,8 @@
    if (slp_typ >= ACPI_S3)
    	halt();
-	/* In most sleep states, the code flow of this function ends at
+	/*
+	 * In most sleep states, the code flow of this function ends at
     * the line above. However, if we entered sleep state S1 and wake
     * up again, we will continue to execute code in this function.
     */
@@ -228,11 +229,11 @@
    	return;
/* Command and return value in EAX */
-	ret = (u32*)&io_smi->rax;
+	ret = (u32 *)&io_smi->rax;
    sub_command = (u8)(*ret >> 8);
/* Parameter buffer in EBX */
-	param = (u32*)&io_smi->rbx;
+	param = (u32 *)&io_smi->rbx;
/* drivers/elog/gsmi.c */
    *ret = gsmi_exec(sub_command, param);
@@ -345,7 +346,7 @@
     * on a power button event.
     */
    if (pm1_sts & PWRBTN_STS) {
-		// power button pressed
+		/* power button pressed */
    	elog_gsmi_add_event(ELOG_TYPE_POWER_BUTTON);
    	disable_pm1_control(-1UL);
    	enable_pm1_control(SLP_EN | (SLP_TYP_S5 << 10));
@@ -367,9 +368,7 @@
static void southbridge_smi_mc(void)
 {
-	u32 reg32;
-
-	reg32 = inl(get_pmbase() + SMI_EN);
+	u32 reg32 = inl(get_pmbase() + SMI_EN);
/* Are microcontroller SMIs enabled? */
    if ((reg32 & MCSMI_EN) == 0)
@@ -386,17 +385,16 @@
    if (!tco_sts)
    	return;
-	if (tco_sts & (1 << 8)) { // BIOSWR
-		u8 bios_cntl;
-
-		bios_cntl = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0xdc);
+	// BIOSWR
+	if (tco_sts & (1 << 8)) {
+		u8 bios_cntl = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0xdc);
if (bios_cntl & 1) {
-			/* BWE is RW, so the SMI was caused by a
+			/*
+			 * BWE is RW, so the SMI was caused by a
    		 * write to BWE, not by a write to the BIOS
-			 */
-
-			/* This is the place where we notice someone
+			 *
+			 * This is the place where we notice someone
    		 * is trying to tinker with the BIOS. We are
    		 * trying to be nice and just ignore it. A more
    		 * resolute answer would be to power down the
@@ -413,9 +411,7 @@
static void southbridge_smi_periodic(void)
 {
-	u32 reg32;
-
-	reg32 = inl(get_pmbase() + SMI_EN);
+	u32 reg32 = inl(get_pmbase() + SMI_EN);
/* Are periodic SMIs enabled? */
    if ((reg32 & PERIODIC_EN) == 0)
@@ -435,7 +431,7 @@
    RCBA32(0x1e00) = trap_sts; // Clear trap(s) in TRSR
trap_cycle = RCBA32(0x1e10);
-	for (i=16; i<20; i++) {
+	for (i = 16; i < 20; i++) {
    	if (trap_cycle & (1 << i))
    		mask |= (0xff << ((i - 16) << 2));
    }
@@ -452,7 +448,8 @@
/* IOTRAP(0) SMIC */
    if (IOTRAP(0)) {
-		if (!(trap_cycle & (1 << 24))) { // It's a write
+		// It's a write
+		if (!(trap_cycle & (1 << 24))) {
    		printk(BIOS_DEBUG, "SMI1 command\n");
    		(void)RCBA32(0x1e18);
    		// data = RCBA32(0x1e18);
@@ -466,8 +463,9 @@
printk(BIOS_DEBUG, "  trapped io address = 0x%x\n",
           trap_cycle & 0xfffc);
-	for (i=0; i < 4; i++)
-		if (IOTRAP(i)) printk(BIOS_DEBUG, "  TRAP = %d\n", i);
+	for (i = 0; i < 4; i++)
+		if (IOTRAP(i))
+			printk(BIOS_DEBUG, "  TRAP = %d\n", i);
    printk(BIOS_DEBUG, "  AHBE = %x\n", (trap_cycle >> 16) & 0xf);
    printk(BIOS_DEBUG, "  MASK = 0x%08x\n", mask);
    printk(BIOS_DEBUG, "  read/write: %s\n",
-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ibd8430352e860ffc0e2030fd7bc73582982f4695
Gerrit-Change-Number: 45698
Gerrit-PatchSet: 1
Gerrit-Owner: Angel Pons th3fanbus@gmail.com
Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org
Gerrit-MessageType: newchange



    