coreboot-gerrit October 2020

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Change in coreboot[master]: soc/intel: deduplicate ACPI timer emulation
by Michael Niewöhner (Code Review) 14 Oct '20

14 Oct '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45951 ) Change subject: soc/intel: deduplicate ACPI timer emulation ...................................................................... Patch Set 18: (2 comments) https://review.coreboot.org/c/coreboot/+/45951/17/src/soc/intel/alderlake/c… File src/soc/intel/alderlake/cpu.c: https://review.coreboot.org/c/coreboot/+/45951/17/src/soc/intel/alderlake/c… PS17, Line 148: if ACPI PM timer is disabled > Will need in update if we decide to drop the condition. There is no condition anymore https://review.coreboot.org/c/coreboot/+/45951/17/src/soc/intel/apollolake/… File src/soc/intel/apollolake/Makefile.inc: https://review.coreboot.org/c/coreboot/+/45951/17/src/soc/intel/apollolake/… PS17, Line 13: ../../soc/intel/ > > err, why is it done in the bootblock? We might want to move it later. > That's a very good question. In APL it is done 1) in early core init in bootblock AND 2) in core init in ramstage The code in APL mentions this in cpu.c, maybe that is the reason it's also done in early init: " Enable ACPI PM timer emulation, which also lets microcode know location of ACPI_BASE_ADDRESS. This also enables other features implemented in microcode." Would be good to know, *what* features that are and if other platforms need this, too in early cpu init... Andrey, Furquan, Subrata: any idea? -- To view, visit https://review.coreboot.org/c/coreboot/+/45951 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ied4b312b6d53e80e71c55f4d1ca78a8cb2799793 Gerrit-Change-Number: 45951 Gerrit-PatchSet: 18 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 14 Oct 2020 11:45:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel: deduplicate ACPI timer emulation
by Michael Niewöhner (Code Review) 14 Oct '20

14 Oct '20

Hello build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth, Furquan Shaikh, Subrata Banik, Aamir Bohra, Andrey Petrov, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/45951 to look at the new patch set (#18). Change subject: soc/intel: deduplicate ACPI timer emulation ...................................................................... soc/intel: deduplicate ACPI timer emulation The code for enabling ACPI timer emulation is the same for the SoCs APL, SKL, CNL, ICL, TGL, JSL and EHL. Deduplicate it by moving it to common code. Note: The ACPI timer emulation can only be used by SoCs with microcode supporting CTC (Common Timer Copy) / ACPI timer emulation. Change-Id: Ied4b312b6d53e80e71c55f4d1ca78a8cb2799793 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/soc/intel/alderlake/cpu.c M src/soc/intel/apollolake/Makefile.inc M src/soc/intel/apollolake/include/soc/pm.h M src/soc/intel/apollolake/pmutil.c M src/soc/intel/cannonlake/cpu.c M src/soc/intel/common/block/cpu/Makefile.inc A src/soc/intel/common/block/cpu/pm_timer_emulation.c M src/soc/intel/common/block/include/intelblocks/cpulib.h M src/soc/intel/elkhartlake/cpu.c M src/soc/intel/icelake/cpu.c M src/soc/intel/jasperlake/cpu.c M src/soc/intel/skylake/cpu.c M src/soc/intel/tigerlake/cpu.c 13 files changed, 39 insertions(+), 167 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/45951/18 -- To view, visit https://review.coreboot.org/c/coreboot/+/45951 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ied4b312b6d53e80e71c55f4d1ca78a8cb2799793 Gerrit-Change-Number: 45951 Gerrit-PatchSet: 18 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel: convert XTAL frequency constant to Kconfig
by Michael Niewöhner (Code Review) 14 Oct '20

14 Oct '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46018 ) Change subject: soc/intel: convert XTAL frequency constant to Kconfig ...................................................................... Patch Set 11: (1 comment) https://review.coreboot.org/c/coreboot/+/46018/10/src/soc/intel/common/bloc… File src/soc/intel/common/block/cpu/Kconfig: https://review.coreboot.org/c/coreboot/+/46018/10/src/soc/intel/common/bloc… PS10, Line 102: config SOC_INTEL_COMMON_BLOCK_XTAL_CLOCK_HZ > I named it like SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ, but yes, XTAL is about the cpu, while gspi is […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/46018 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1382dd274eeb9cb748f94c34f5d9a83880624c18 Gerrit-Change-Number: 46018 Gerrit-PatchSet: 11 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 14 Oct 2020 11:45:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel: convert XTAL frequency constant to Kconfig
by Michael Niewöhner (Code Review) 14 Oct '20

14 Oct '20

Hello build bot (Jenkins), Nico Huber, Paul Menzel, Subrata Banik, Andrey Petrov, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/46018 to look at the new patch set (#11). Change subject: soc/intel: convert XTAL frequency constant to Kconfig ...................................................................... soc/intel: convert XTAL frequency constant to Kconfig This converts the constant for the XTAL frequency to a Kconfig option. Change-Id: I1382dd274eeb9cb748f94c34f5d9a83880624c18 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/soc/intel/alderlake/Kconfig M src/soc/intel/alderlake/cpu.c M src/soc/intel/alderlake/include/soc/cpu.h M src/soc/intel/apollolake/Kconfig M src/soc/intel/apollolake/include/soc/cpu.h M src/soc/intel/apollolake/pmutil.c M src/soc/intel/cannonlake/Kconfig M src/soc/intel/cannonlake/cpu.c M src/soc/intel/cannonlake/include/soc/cpu.h M src/soc/intel/common/block/cpu/Kconfig M src/soc/intel/elkhartlake/Kconfig M src/soc/intel/elkhartlake/cpu.c M src/soc/intel/elkhartlake/include/soc/cpu.h M src/soc/intel/icelake/Kconfig M src/soc/intel/icelake/cpu.c M src/soc/intel/icelake/include/soc/cpu.h M src/soc/intel/jasperlake/Kconfig M src/soc/intel/jasperlake/cpu.c M src/soc/intel/jasperlake/include/soc/cpu.h M src/soc/intel/skylake/Kconfig M src/soc/intel/skylake/cpu.c M src/soc/intel/skylake/include/soc/cpu.h M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/cpu.c M src/soc/intel/tigerlake/include/soc/cpu.h 25 files changed, 85 insertions(+), 63 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/46018/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/46018 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1382dd274eeb9cb748f94c34f5d9a83880624c18 Gerrit-Change-Number: 46018 Gerrit-PatchSet: 11 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: {cpu,soc}/intel: deduplicate cpu code
by Michael Niewöhner (Code Review) 14 Oct '20

14 Oct '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46274 ) Change subject: {cpu,soc}/intel: deduplicate cpu code ...................................................................... Patch Set 10: (1 comment) https://review.coreboot.org/c/coreboot/+/46274/9/src/soc/intel/cannonlake/c… File src/soc/intel/cannonlake/cpu.c: https://review.coreboot.org/c/coreboot/+/46274/9/src/soc/intel/cannonlake/c… PS9, Line 109: /* : * The emulated ACPI timer allows replacing of the ACPI timer : * (PM1_TMR) to have no impart on the system. : */ : static void enable_pm_timer_emulation(void) : { : const struct soc_intel_cannonlake_config *config; : msr_t msr; : : config = config_of_soc(); : : /* Enable PM timer emulation only if ACPI PM timer is disabled */ : if (!config->PmTimerDisabled) : return; : /* : * The derived frequency is calculated as follows: : * (CTC_FREQ * msr[63:32]) >> 32 = target frequency. : * Back solve the multiplier so the 3.579545MHz ACPI timer : * frequency is used. : */ : msr.hi = (3579545ULL << 32) / CTC_FREQ; : /* Set PM1 timer IO port and enable */ : msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) | : EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR); : wrmsr(MSR_EMULATE_PM_TIMER, msr); : } that was unintended and is done in a separate patch series. see CB:45951 -- To view, visit https://review.coreboot.org/c/coreboot/+/46274 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib0cc834de8492d59c423317598e1c11847a0b1ab Gerrit-Change-Number: 46274 Gerrit-PatchSet: 10 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 14 Oct 2020 11:18:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: add Kconfig to enable/disable the ACPI PM timer
by Michael Niewöhner (Code Review) 14 Oct '20

14 Oct '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45952 ) Change subject: soc/intel/common: add Kconfig to enable/disable the ACPI PM timer ...................................................................... Patch Set 19: (1 comment) https://review.coreboot.org/c/coreboot/+/45952/19//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/45952/19//COMMIT_MSG@25 PS19, Line 25: unknown if that is desireable on that platform. > Any clue if APL has that timer? yup, see intel doc #334818 -- To view, visit https://review.coreboot.org/c/coreboot/+/45952 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7f607f277eb14f84a7370ffb25a13226e7ccc917 Gerrit-Change-Number: 45952 Gerrit-PatchSet: 19 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 14 Oct 2020 11:17:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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Change in coreboot[master]: {cpu,soc}/intel: deduplicate cpu code
by Michael Niewöhner (Code Review) 14 Oct '20

14 Oct '20

Hello Felix Singer, build bot (Jenkins), Nico Huber, Paul Menzel, Subrata Banik, Angel Pons, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/46274 to look at the new patch set (#10). Change subject: {cpu,soc}/intel: deduplicate cpu code ...................................................................... {cpu,soc}/intel: deduplicate cpu code Move a whole bunch of copy-pasta code from soc/intel/{bdw,skl,cnl,icl, tgl,ehl,jsl,adl} and cpu/intel/{hsw,model_*} to cpu/intel/common. Change-Id: Ib0cc834de8492d59c423317598e1c11847a0b1ab Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/cpu/intel/common/common.h M src/cpu/intel/common/common_init.c M src/cpu/intel/haswell/haswell_init.c M src/cpu/intel/model_2065x/model_2065x_init.c M src/cpu/intel/model_206ax/model_206ax_init.c M src/include/cpu/intel/msr.h M src/soc/intel/alderlake/cpu.c M src/soc/intel/broadwell/cpu.c M src/soc/intel/cannonlake/cpu.c M src/soc/intel/elkhartlake/cpu.c M src/soc/intel/icelake/Kconfig M src/soc/intel/icelake/cpu.c M src/soc/intel/jasperlake/cpu.c M src/soc/intel/skylake/cpu.c M src/soc/intel/tigerlake/cpu.c 15 files changed, 57 insertions(+), 412 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/46274/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/46274 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib0cc834de8492d59c423317598e1c11847a0b1ab Gerrit-Change-Number: 46274 Gerrit-PatchSet: 10 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: {cpu,soc}/intel: replace AES-NI locking by common implemenation call
by Michael Niewöhner (Code Review) 14 Oct '20

14 Oct '20

Hello Felix Singer, build bot (Jenkins), Nico Huber, Furquan Shaikh, David Guckian, Paul Menzel, Tim Wawrzynczak, Vanessa Eusebio, Subrata Banik, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/46278 to look at the new patch set (#5). Change subject: {cpu,soc}/intel: replace AES-NI locking by common implemenation call ...................................................................... {cpu,soc}/intel: replace AES-NI locking by common implemenation call Deduplicate code by using the new common cpu code implementation of AES-NI locking. For model_2065x and model_206ax locking was moved from SMM to core init because the MSR is core-scoped, not package-scoped. Change-Id: I7ab2d3839ecb758335ef8cc6a0c0c7103db0fa50 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/cpu/intel/common/common_init.c M src/cpu/intel/model_2065x/Kconfig M src/cpu/intel/model_2065x/finalize.c M src/cpu/intel/model_2065x/model_2065x_init.c M src/cpu/intel/model_206ax/Kconfig M src/cpu/intel/model_206ax/finalize.c M src/cpu/intel/model_206ax/model_206ax_init.c M src/include/cpu/intel/msr.h M src/soc/intel/apollolake/cpu.c M src/soc/intel/common/block/cpu/cpulib.c M src/soc/intel/common/block/include/intelblocks/msr.h M src/soc/intel/denverton_ns/Kconfig M src/soc/intel/denverton_ns/cpu.c M src/soc/intel/skylake/cpu.c 14 files changed, 22 insertions(+), 45 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/46278/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/46278 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7ab2d3839ecb758335ef8cc6a0c0c7103db0fa50 Gerrit-Change-Number: 46278 Gerrit-PatchSet: 5 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: include/cpu/x86: introduce new helper for (un)setting MSRs
by Michael Niewöhner (Code Review) 14 Oct '20

14 Oct '20

Hello Felix Singer, build bot (Jenkins), Nico Huber, Furquan Shaikh, Paul Menzel, Tim Wawrzynczak, Subrata Banik, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/46354 to look at the new patch set (#3). Change subject: include/cpu/x86: introduce new helper for (un)setting MSRs ...................................................................... include/cpu/x86: introduce new helper for (un)setting MSRs msr_set_bit can only set single bits in MSRs and causes mixing of bit positions and bitmasks in the MRS header files. Thus, replace the helper by a version which can unset and set whole MSR bitmasks, just like the "and-or"-helper, but in the way CB:42134 was done (inversion done in the helper). This helps keeping the MSR macros unified in bitmask style. The few uses of msr_set_bit have been replaced by the new macro, while the used macros have been converted accordingly. Change-Id: Idfe9b66e7cfe78ec295a44a2a193f530349f7689 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/cpu/intel/haswell/finalize.c M src/cpu/intel/model_2065x/finalize.c M src/cpu/intel/model_206ax/finalize.c M src/include/cpu/x86/msr.h M src/soc/intel/common/block/cpu/cpulib.c M src/soc/intel/common/block/include/intelblocks/msr.h 6 files changed, 23 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/46354/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/46354 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idfe9b66e7cfe78ec295a44a2a193f530349f7689 Gerrit-Change-Number: 46354 Gerrit-PatchSet: 3 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: nb/intel/haswell: Account for DPR region in memory map
by Angel Pons (Code Review) 14 Oct '20

14 Oct '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45712 ) Change subject: nb/intel/haswell: Account for DPR region in memory map ...................................................................... Patch Set 10: (1 comment) https://review.coreboot.org/c/coreboot/+/45712/10/src/northbridge/intel/has… File src/northbridge/intel/haswell/northbridge.c: https://review.coreboot.org/c/coreboot/+/45712/10/src/northbridge/intel/has… PS10, Line 339: resource->base = (dpr.top - dpr.size) << 10; : resource->size = (dpr.size << 10); this needs to be in bytes -- To view, visit https://review.coreboot.org/c/coreboot/+/45712 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I11f23fd43188f987e35fd61f52587e567496cd78 Gerrit-Change-Number: 45712 Gerrit-PatchSet: 10 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 14 Oct 2020 10:04:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit October 2020