Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46273 )
Change subject: soc/intel/cnl: lock AES-NI feature if selected
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Patch Set 6: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/46273/6/src/soc/intel/cannonlake/K…
File src/soc/intel/cannonlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/46273/6/src/soc/intel/cannonlake/K…
PS6, Line 81: select CPU_INTEL_COMMON_HYPERTHREADING
Wondering why we have that, i.e. would there be any harm if we'd assume it's `y`?
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Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46275 )
Change subject: cpu/intel/common: rework AES-NI locking
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Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/46275/3/src/cpu/intel/common/commo…
File src/cpu/intel/common/common_init.c:
https://review.coreboot.org/c/coreboot/+/46275/3/src/cpu/intel/common/commo…
PS3, Line 279: msr_unset_and_set(MSR_FEATURE_CONFIG, 0, AESNI_LOCK);
I'm not 100% sure about this. Sometimes registers that are already locked
take a wrmsr() as a serious offense. So why drop the check? I'd have to
ask to test it on all affected platforms.
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Hello build bot (Jenkins), Angel Pons, Michael Niewöhner,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46345
to look at the new patch set (#3).
Change subject: libpayload/libpci: Return pointer to allocated memory directly
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libpayload/libpci: Return pointer to allocated memory directly
Change-Id: Ib2ee8dbfaabbf7a824b4fd75ad7c779393af2900
Signed-off-by: Felix Singer <felix.singer(a)secunet.com>
---
M payloads/libpayload/libpci/libpci.c
1 file changed, 1 insertion(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/46345/3
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Gerrit-MessageType: newpatchset
Hello build bot (Jenkins), Arthur Heymans, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45712
to look at the new patch set (#12).
Change subject: nb/intel/haswell: Account for DPR region in memory map
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nb/intel/haswell: Account for DPR region in memory map
While MRC.bin does not allocate any memory for DPR by default, it can be
patched to do so. However, the current northbridge code does not account
for DPR and will, among other things, place CBMEM inside it. Even though
this may seem like a good thing, it renders TianoCore unable to boot and
clashes with Intel TXT support (the reason to enable DPR to begin with).
Update memmap.c so that CBMEM top does not fall within DPR. Also, report
DPR as reserved, so that OSes know that the DPR memory is not to be used.
Change-Id: I11f23fd43188f987e35fd61f52587e567496cd78
Signed-off-by: Angel Pons <th3fanbus(a)gmail.com>
---
M src/northbridge/intel/haswell/memmap.c
M src/northbridge/intel/haswell/northbridge.c
M src/northbridge/intel/haswell/registers/host_bridge.h
3 files changed, 62 insertions(+), 11 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/45712/12
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