coreboot-gerrit October 2020

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Change in coreboot[master]: nb/intel/haswell: Account for DPR region in memory map
by Philipp Deppenwiese (Code Review) 15 Oct '20

15 Oct '20

Philipp Deppenwiese has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45712 ) Change subject: nb/intel/haswell: Account for DPR region in memory map ...................................................................... nb/intel/haswell: Account for DPR region in memory map While MRC.bin does not allocate any memory for DPR by default, it can be patched to do so. However, the current northbridge code does not account for DPR and will, among other things, place CBMEM inside it. Even though this may seem like a good thing, it renders TianoCore unable to boot and clashes with Intel TXT support (the reason to enable DPR to begin with). Update memmap.c so that CBMEM top does not fall within DPR. Also, report DPR as reserved, so that OSes know that the DPR memory is not to be used. Change-Id: I11f23fd43188f987e35fd61f52587e567496cd78 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45712 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/haswell/memmap.c M src/northbridge/intel/haswell/northbridge.c M src/northbridge/intel/haswell/registers/host_bridge.h 3 files changed, 62 insertions(+), 11 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved diff --git a/src/northbridge/intel/haswell/memmap.c b/src/northbridge/intel/haswell/memmap.c index 807ee2a..ac36e25 100644 --- a/src/northbridge/intel/haswell/memmap.c +++ b/src/northbridge/intel/haswell/memmap.c @@ -9,27 +9,56 @@ #include <cpu/x86/smm.h> #include <device/pci_ops.h> #include <cbmem.h> +#include <security/intel/txt/txt_register.h> + #include "haswell.h" -static uintptr_t smm_region_start(void) +static uintptr_t northbridge_get_tseg_base(void) +{ + return ALIGN_DOWN(pci_read_config32(HOST_BRIDGE, TSEG), 1 * MiB); +} + +static size_t northbridge_get_tseg_size(void) +{ + return CONFIG_SMM_TSEG_SIZE; +} + +/* + * Return the topmost memory address below 4 GiB available for general + * use, from software's view of memory. Do not confuse this with TOLUD, + * which applies to the DRAM as viewed by the memory controller itself. + */ +static uintptr_t top_of_low_usable_memory(void) { /* - * Base of TSEG is top of usable DRAM below 4GiB. The register has - * 1 MiB alignment. + * Base of DPR is top of usable DRAM below 4 GiB. However, DPR + * isn't always enabled. Unlike most memory map registers, the + * DPR register stores top of DPR instead of its base address. + * Unless binary-patched, Haswell MRC.bin does not enable DPR. + * Top of DPR is R/O, and mirrored from TSEG base by hardware. */ - uintptr_t tom = pci_read_config32(HOST_BRIDGE, TSEG); - return ALIGN_DOWN(tom, 1 * MiB); + uintptr_t tolum = northbridge_get_tseg_base(); + + const union dpr_register dpr = { + .raw = pci_read_config32(HOST_BRIDGE, DPR), + }; + + /* Subtract DMA Protected Range size if enabled */ + if (dpr.epm) + tolum -= dpr.size * MiB; + + return tolum; } void *cbmem_top_chipset(void) { - return (void *)smm_region_start(); + return (void *)top_of_low_usable_memory(); } void smm_region(uintptr_t *start, size_t *size) { - *start = smm_region_start(); - *size = CONFIG_SMM_TSEG_SIZE; + *start = northbridge_get_tseg_base(); + *size = northbridge_get_tseg_size(); } void fill_postcar_frame(struct postcar_frame *pcf) diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index e1c26d1..5619d95 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -12,6 +12,7 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> #include <boot/tables.h> +#include <security/intel/txt/txt_register.h> #include "chip.h" #include "haswell.h" @@ -162,7 +163,8 @@ } } -/* Host Memory Map: +/* + * Host Memory Map: * * +--------------------------+ TOUUD * | | @@ -175,6 +177,8 @@ * +--------------------------+ BGSM * | TSEG | * +--------------------------+ TSEGMB + * | DPR | + * +--------------------------+ (DPR top - DPR size) * | Usage DRAM | * +--------------------------+ 0 * @@ -285,6 +289,12 @@ mc_read_map_entries(dev, &mc_values[0]); mc_report_map_entries(dev, &mc_values[0]); + /* The DPR register is special */ + const union dpr_register dpr = { + .raw = pci_read_config32(dev, DPR), + }; + printk(BIOS_DEBUG, "MC MAP: DPR: 0x%x\n", dpr.raw); + /* * These are the host memory ranges that should be added: * - 0 -> 0xa0000: cacheable @@ -318,11 +328,20 @@ size_k = (0xa0000 >> 10) - base_k; ram_resource(dev, index++, base_k, size_k); - /* 0xc0000 -> TSEG */ + /* 0xc0000 -> DPR base */ base_k = 0xc0000 >> 10; - size_k = (unsigned long)(mc_values[TSEG_REG] >> 10) - base_k; + size_k = (unsigned long)(mc_values[TSEG_REG] >> 10) - (base_k + dpr.size); ram_resource(dev, index++, base_k, size_k); + /* DPR base -> TSEG */ + if (dpr.size) { + resource = new_resource(dev, index++); + resource->base = (dpr.top - dpr.size) * MiB; + resource->size = dpr.size * MiB; + resource->flags = IORESOURCE_MEM | IORESOURCE_STORED | IORESOURCE_CACHEABLE | + IORESOURCE_RESERVE | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + } + /* TSEG -> BGSM */ resource = new_resource(dev, index++); resource->base = mc_values[TSEG_REG]; diff --git a/src/northbridge/intel/haswell/registers/host_bridge.h b/src/northbridge/intel/haswell/registers/host_bridge.h index d348fd4..7746801 100644 --- a/src/northbridge/intel/haswell/registers/host_bridge.h +++ b/src/northbridge/intel/haswell/registers/host_bridge.h @@ -25,6 +25,9 @@ #define PAVPC 0x58 #define DPR 0x5c +#define DPR_EPM (1 << 2) +#define DPR_PRS (1 << 1) +#define DPR_SIZE_MASK 0xff0 #define PCIEXBAR 0x60 #define DMIBAR 0x68 -- To view, visit https://review.coreboot.org/c/coreboot/+/45712 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I11f23fd43188f987e35fd61f52587e567496cd78 Gerrit-Change-Number: 45712 Gerrit-PatchSet: 13 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: security/intel/txt: Use `smm_region()` to get TSEG base
by Angel Pons (Code Review) 15 Oct '20

15 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46055 ) Change subject: security/intel/txt: Use `smm_region()` to get TSEG base ...................................................................... security/intel/txt: Use `smm_region()` to get TSEG base This function is available for all TXT-capable platforms. Use it. Change-Id: I4b3dcbc61854fbdd42275bf9456eaa5ce783e8aa Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/security/intel/txt/logging.c M src/security/intel/txt/ramstage.c 2 files changed, 14 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/46055/1 diff --git a/src/security/intel/txt/logging.c b/src/security/intel/txt/logging.c index 9fe53c5..f2814a9 100644 --- a/src/security/intel/txt/logging.c +++ b/src/security/intel/txt/logging.c @@ -2,6 +2,7 @@ #include <arch/mmio.h> #include <console/console.h> +#include <cpu/x86/smm.h> #include <string.h> #include <types.h> @@ -211,7 +212,11 @@ void txt_dump_regions(void) { struct txt_biosdataregion *bdr = NULL; - uintptr_t tseg = 0; + + uintptr_t tseg_base, tseg_size; + + smm_region(&tseg_base, &tseg_size); + uint64_t reg64; reg64 = read64((void *)TXT_HEAP_BASE); @@ -219,7 +224,7 @@ (read64((void *)(uintptr_t)reg64) >= (sizeof(*bdr) + sizeof(uint64_t)))) bdr = (void *)((uintptr_t)reg64 + sizeof(uint64_t)); - printk(BIOS_DEBUG, "TEE-TXT: TSEG 0x%lx\n", tseg * MiB); + printk(BIOS_DEBUG, "TEE-TXT: TSEG 0x%lx\n", tseg_base * MiB); printk(BIOS_DEBUG, "TEE-TXT: TXT.HEAP.BASE 0x%llx\n", read64((void *)TXT_HEAP_BASE)); printk(BIOS_DEBUG, "TEE-TXT: TXT.HEAP.SIZE 0x%llx\n", read64((void *)TXT_HEAP_SIZE)); printk(BIOS_DEBUG, "TEE-TXT: TXT.SINIT.BASE 0x%llx\n", read64((void *)TXT_SINIT_BASE)); diff --git a/src/security/intel/txt/ramstage.c b/src/security/intel/txt/ramstage.c index bc30da5..2e13ad2 100644 --- a/src/security/intel/txt/ramstage.c +++ b/src/security/intel/txt/ramstage.c @@ -8,6 +8,7 @@ #include <console/console.h> #include <cpu/intel/common/common.h> #include <cpu/x86/msr.h> +#include <cpu/x86/smm.h> #include <device/pci_ops.h> #include <types.h> @@ -204,7 +205,10 @@ static void lockdown_intel_txt(void *unused) { const uint64_t status = read64((void *)TXT_SPAD); - uintptr_t tseg = 0; + + uintptr_t tseg_base, tseg_size; + + smm_region(&tseg_base, &tseg_size); if (status & ACMSTS_TXT_DISABLED) return; @@ -232,7 +236,7 @@ union dpr_register dpr = { .lock = 1, .size = 3, - .top = tseg, + .top = tseg_base, }; write64((void *)TXT_DPR, dpr.raw); @@ -248,7 +252,7 @@ */ write64((void *)TXT_HEAP_SIZE, 0xE0000); write64((void *)TXT_HEAP_BASE, - ALIGN_DOWN((tseg * MiB) - read64((void *)TXT_HEAP_SIZE), 4096)); + ALIGN_DOWN((tseg_base * MiB) - read64((void *)TXT_HEAP_SIZE), 4096)); /* * Document Number: 558294 -- To view, visit https://review.coreboot.org/c/coreboot/+/46055 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4b3dcbc61854fbdd42275bf9456eaa5ce783e8aa Gerrit-Change-Number: 46055 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/haswell: Account for DPR region in memory map
by Arthur Heymans (Code Review) 15 Oct '20

15 Oct '20

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45712 ) Change subject: nb/intel/haswell: Account for DPR region in memory map ...................................................................... Patch Set 12: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/45712 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I11f23fd43188f987e35fd61f52587e567496cd78 Gerrit-Change-Number: 45712 Gerrit-PatchSet: 12 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 15 Oct 2020 08:28:43 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/boldar: Set devicetree configuration
by Subrata Banik (Code Review) 15 Oct '20

15 Oct '20

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46245 ) Change subject: mb/google/boldar: Set devicetree configuration ...................................................................... Patch Set 5: Code-Review+1 (1 comment) https://review.coreboot.org/c/coreboot/+/46245/5/src/mainboard/google/volte… File src/mainboard/google/volteer/variants/boldar/overridetree.cb: https://review.coreboot.org/c/coreboot/+/46245/5/src/mainboard/google/volte… PS5, Line 7: use tab? -- To view, visit https://review.coreboot.org/c/coreboot/+/46245 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4fdf9410a5f06aac02240cd4e1f15e085b4d3b0c Gerrit-Change-Number: 46245 Gerrit-PatchSet: 5 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 15 Oct 2020 07:23:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/volteer: add generic DDR4 SPDs for Lindar
by Rasheed Hsueh (Code Review) 15 Oct '20

15 Oct '20

Rasheed Hsueh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46293 ) Change subject: mb/google/volteer: add generic DDR4 SPDs for Lindar ...................................................................... mb/google/volteer: add generic DDR4 SPDs for Lindar Add Makefile.inc to include six generic DDR4 SPDs for the following parts for Lindar: DRAM Part Name DRAM ID to assign MT53E512M32D2NP-046 WT:E 0 (0000) K4U6E3S4AA-MGCR 1 (0001) H9HCNNNBKMMLXR-NEE 2 (0010) MT53E512M32D2NP-046 WT:E 8 (1000) K4U6E3S4AA-MGCR 9 (1001) H9HCNNNBKMMLXR-NEE 10 (1010) BUG=b:161089195 TEST="FW_NAME=Lindar emerge-volteer coreboot" and verify it builds without error. Signed-off-by: rasheed.hsueh <rasheed.hsueh(a)lcfc.corp-partner.google.com> Change-Id: I088517090da0565e55ffa978cb90cb879f3b6702 --- M src/mainboard/google/volteer/variants/lindar/memory/Makefile.inc M src/mainboard/google/volteer/variants/lindar/memory/dram_id.generated.txt M src/mainboard/google/volteer/variants/lindar/memory/mem_list_variant.txt 3 files changed, 15 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/46293/1 diff --git a/src/mainboard/google/volteer/variants/lindar/memory/Makefile.inc b/src/mainboard/google/volteer/variants/lindar/memory/Makefile.inc index 8c96e06..8f17e14 100644 --- a/src/mainboard/google/volteer/variants/lindar/memory/Makefile.inc +++ b/src/mainboard/google/volteer/variants/lindar/memory/Makefile.inc @@ -2,4 +2,9 @@ ## This is an auto-generated file. Do not edit!! SPD_SOURCES = -SPD_SOURCES += lp4x-spd-1.hex # ID = 0(0b0000) Parts = K4U6E3S4AA-MGCL +SPD_SOURCES += lp4x-spd-1.hex # ID = 0(0b0000) Parts = MT53E512M32D2NP-046 WT:E +SPD_SOURCES += lp4x-spd-1.hex # ID = 1(0b0001) Parts = K4U6E3S4AA-MGCR +SPD_SOURCES += lp4x-spd-1.hex # ID = 2(0b0010) Parts = H9HCNNNBKMMLXR-NEE +SPD_SOURCES += lp4x-spd-1.hex # ID = 8(0b1000) Parts = MT53E512M32D2NP-046 WT:E +SPD_SOURCES += lp4x-spd-1.hex # ID = 9(0b1001) Parts = K4U6E3S4AA-MGCR +SPD_SOURCES += lp4x-spd-1.hex # ID = 10(0b1010) Parts = H9HCNNNBKMMLXR-NEE diff --git a/src/mainboard/google/volteer/variants/lindar/memory/dram_id.generated.txt b/src/mainboard/google/volteer/variants/lindar/memory/dram_id.generated.txt index 9bf0bd9..9ed10ec 100644 --- a/src/mainboard/google/volteer/variants/lindar/memory/dram_id.generated.txt +++ b/src/mainboard/google/volteer/variants/lindar/memory/dram_id.generated.txt @@ -1,2 +1,7 @@ DRAM Part Name ID to assign -K4U6E3S4AA-MGCL 0 (0000) +MT53E512M32D2NP-046 WT:E 0 (0000) +K4U6E3S4AA-MGCR 1 (0001) +H9HCNNNBKMMLXR-NEE 2 (0010) +MT53E512M32D2NP-046 WT:E 8 (1000) +K4U6E3S4AA-MGCR 9 (1001) +H9HCNNNBKMMLXR-NEE 10 (1010) diff --git a/src/mainboard/google/volteer/variants/lindar/memory/mem_list_variant.txt b/src/mainboard/google/volteer/variants/lindar/memory/mem_list_variant.txt index a226d2f..47159f8 100644 --- a/src/mainboard/google/volteer/variants/lindar/memory/mem_list_variant.txt +++ b/src/mainboard/google/volteer/variants/lindar/memory/mem_list_variant.txt @@ -1 +1,3 @@ -K4U6E3S4AA-MGCL +MT53E512M32D2NP-046 WT:E +K4U6E3S4AA-MGCR +H9HCNNNBKMMLXR-NEE -- To view, visit https://review.coreboot.org/c/coreboot/+/46293 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I088517090da0565e55ffa978cb90cb879f3b6702 Gerrit-Change-Number: 46293 Gerrit-PatchSet: 1 Gerrit-Owner: Rasheed Hsueh <rasheed.hsueh(a)lcfc.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/tigerlake: Enable and use USB4 PCIe driver
by Duncan Laurie (Code Review) 15 Oct '20

15 Oct '20

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44917 ) Change subject: soc/intel/tigerlake: Enable and use USB4 PCIe driver ...................................................................... soc/intel/tigerlake: Enable and use USB4 PCIe driver This change enables the USB4/Thunderbolt common layer for Intel SOC, and enables the Intel USB4 PCIe driver. This moves the _DSD variables from the DSDT into the SSDT and allows them to be configured for each board if necessary. Signed-off-by: Duncan Laurie <dlaurie(a)google.com> Change-Id: I2564512d951046e015c148db42fdaf2d4b8b81dd --- M src/mainboard/google/volteer/variants/baseboard/devicetree.cb M src/mainboard/google/volteer/variants/halvor/overridetree.cb M src/mainboard/google/volteer/variants/lindar/overridetree.cb M src/mainboard/google/volteer/variants/malefor/overridetree.cb M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/acpi/tcss_dma.asl M src/soc/intel/tigerlake/acpi/tcss_pcierp.asl M src/soc/intel/tigerlake/chipset.cb 8 files changed, 59 insertions(+), 125 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/44917/1 diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 636d946..2717acd 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -377,13 +377,17 @@ device generic 0 on end end end - device ref tbt_pcie_rp0 on - probe DB_USB USB4_GEN2 - probe DB_USB USB4_GEN3 + chip drivers/intel/usb4/pcie + device ref tbt_pcie_rp0 on + probe DB_USB USB4_GEN2 + probe DB_USB USB4_GEN3 + end end - device ref tbt_pcie_rp1 on - probe DB_USB USB4_GEN2 - probe DB_USB USB4_GEN3 + chip drivers/intel/usb4/pcie + device ref tbt_pcie_rp1 on + probe DB_USB USB4_GEN2 + probe DB_USB USB4_GEN3 + end end device ref tbt_dma0 on probe DB_USB USB4_GEN2 diff --git a/src/mainboard/google/volteer/variants/halvor/overridetree.cb b/src/mainboard/google/volteer/variants/halvor/overridetree.cb index 2db3b96..68269b5 100644 --- a/src/mainboard/google/volteer/variants/halvor/overridetree.cb +++ b/src/mainboard/google/volteer/variants/halvor/overridetree.cb @@ -18,7 +18,9 @@ register "SaGv" = "SaGv_Disabled" device domain 0 on - device pci 07.2 on end # TBT_PCIe2 + chip drivers/intel/usb4/pcie + device pci 07.2 on end # TBT_PCIe2 + end device pci 15.0 on chip drivers/i2c/generic register "hid" = ""10EC5682"" diff --git a/src/mainboard/google/volteer/variants/lindar/overridetree.cb b/src/mainboard/google/volteer/variants/lindar/overridetree.cb index 6f14622..9d9a376 100644 --- a/src/mainboard/google/volteer/variants/lindar/overridetree.cb +++ b/src/mainboard/google/volteer/variants/lindar/overridetree.cb @@ -27,10 +27,18 @@ [PchSerialIoIndexI2C5] = PchSerialIoPci, }" device domain 0 on - device pci 07.0 off end # TBT_PCIe0 0x9A23 - device pci 07.1 off end # TBT_PCIe1 0x9A25 - device pci 07.2 off end # TBT_PCIe2 0x9A27 - device pci 07.3 off end # TBT_PCIe3 0x9A29 + chip drivers/intel/usb4/pcie + device pci 07.0 off end # TBT_PCIe0 0x9A23 + end + chip drivers/intel/usb4/pcie + device pci 07.1 off end # TBT_PCIe1 0x9A25 + end + chip drivers/intel/usb4/pcie + device pci 07.2 off end # TBT_PCIe2 0x9A27 + end + chip drivers/intel/usb4/pcie + device pci 07.3 off end # TBT_PCIe3 0x9A29 + end device pci 15.0 on chip drivers/i2c/generic register "hid" = ""10EC5682"" diff --git a/src/mainboard/google/volteer/variants/malefor/overridetree.cb b/src/mainboard/google/volteer/variants/malefor/overridetree.cb index b184924..a4f3afe 100644 --- a/src/mainboard/google/volteer/variants/malefor/overridetree.cb +++ b/src/mainboard/google/volteer/variants/malefor/overridetree.cb @@ -34,10 +34,18 @@ }" device domain 0 on - device pci 07.0 off end # TBT_PCIe0 0x9A23 - device pci 07.1 off end # TBT_PCIe1 0x9A25 - device pci 07.2 off end # TBT_PCIe2 0x9A27 - device pci 07.3 off end # TBT_PCIe3 0x9A29 + chip drivers/intel/usb4/pcie + device pci 07.0 off end # TBT_PCIe0 0x9A23 + end + chip drivers/intel/usb4/pcie + device pci 07.1 off end # TBT_PCIe1 0x9A25 + end + chip drivers/intel/usb4/pcie + device pci 07.2 off end # TBT_PCIe2 0x9A27 + end + chip drivers/intel/usb4/pcie + device pci 07.3 off end # TBT_PCIe3 0x9A29 + end device pci 15.0 on chip drivers/i2c/generic register "hid" = ""10EC5682"" diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index 3b0df5d..250840f 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -17,6 +17,7 @@ select CACHE_MRC_SETTINGS select CPU_INTEL_COMMON select CPU_INTEL_FIRMWARE_INTERFACE_TABLE + select DRIVERS_INTEL_USB4_PCIE select FSP_COMPRESS_FSP_S_LZ4 select FSP_M_XIP select GENERIC_GPIO_LIB @@ -51,6 +52,7 @@ select SOC_INTEL_COMMON_BLOCK_SA select SOC_INTEL_COMMON_BLOCK_SMM select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP + select SOC_INTEL_COMMON_BLOCK_USB4 select SOC_INTEL_COMMON_PCH_BASE select SOC_INTEL_COMMON_RESET select SOC_INTEL_COMMON_BLOCK_CAR diff --git a/src/soc/intel/tigerlake/acpi/tcss_dma.asl b/src/soc/intel/tigerlake/acpi/tcss_dma.asl index da2e8fe..d00f794 100644 --- a/src/soc/intel/tigerlake/acpi/tcss_dma.asl +++ b/src/soc/intel/tigerlake/acpi/tcss_dma.asl @@ -82,30 +82,3 @@ { Return (Package() { 0x6D, 4 }) } - -Method (_DSD, 0) -{ - Return( - Package() - { - /* Thunderbolt GUID for IMR_VALID at ../drivers/acpi/property.c */ - ToUUID("C44D002F-69F9-4E7D-A904-A7BAABDF43F7"), - Package () - { - Package (2) { "IMR_VALID", 1 } - }, - - /* Thunderbolt GUID for WAKE_SUPPORTED at ../drivers/acpi/property.c */ - ToUUID("6C501103-C189-4296-BA72-9BF5A26EBE5D"), - Package () - { - Package (2) { "WAKE_SUPPORTED", 1 } - } - } - ) -} - -Method (_DSM, 4, Serialized) -{ - Return (Buffer() { 0 }) -} diff --git a/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl b/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl index abca5d1..3f495be 100644 --- a/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl +++ b/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl @@ -216,85 +216,6 @@ } } -Method (_DSD, 0) { - If ((TUID == 0) || (TUID == 1)) { - Return ( Package() { - /* acpi_pci_bridge_d3 at ../drivers/pci/pci-acpi.c */ - ToUUID("6211E2C0-58A3-4AF3-90E1-927A4E0C55A4"), - Package () - { - Package (2) { "HotPlugSupportInD3", 1 }, - }, - - /* pci_acpi_set_untrusted at ../drivers/pci/pci-acpi.c */ - ToUUID("EFCC06CC-73AC-4BC3-BFF0-76143807C389"), - Package () { - Package (2) { "ExternalFacingPort", 1 }, /* TBT/CIO port */ - /* - * UID of the TBT RP on platform, range is: 0, 1 ..., - * (NumOfTBTRP - 1). - */ - Package (2) { "UID", TUID }, - }, - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package (2) { "usb4-host-interface", \_SB.PCI0.TDM0 }, - Package (2) { "usb4-port-number", TUID }, - } - }) - } ElseIf (TUID == 2) { - Return ( Package () { - /* acpi_pci_bridge_d3 at ../drivers/pci/pci-acpi.c */ - ToUUID("6211E2C0-58A3-4AF3-90E1-927A4E0C55A4"), - Package () - { - Package (2) { "HotPlugSupportInD3", 1 }, - }, - - /* pci_acpi_set_untrusted at ../drivers/pci/pci-acpi.c */ - ToUUID("EFCC06CC-73AC-4BC3-BFF0-76143807C389"), - Package () { - Package (2) { "ExternalFacingPort", 1 }, /* TBT/CIO port */ - /* - * UID of the TBT RP on platform, range is: 0, 1 ..., - * (NumOfTBTRP - 1). - */ - Package (2) { "UID", TUID }, - }, - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package (2) { "usb4-host-interface", \_SB.PCI0.TDM1 }, - Package (2) { "usb4-port-number", 0 }, - } - }) - } Else { /* TUID == 3 */ - Return ( Package () { - /* acpi_pci_bridge_d3 at ../drivers/pci/pci-acpi.c */ - ToUUID("6211E2C0-58A3-4AF3-90E1-927A4E0C55A4"), - Package () - { - Package (2) { "HotPlugSupportInD3", 1 }, - }, - - /* pci_acpi_set_untrusted at ../drivers/pci/pci-acpi.c */ - ToUUID("EFCC06CC-73AC-4BC3-BFF0-76143807C389"), - Package () { - Package (2) { "ExternalFacingPort", 1 }, /* TBT/CIO port */ - /* - * UID of the TBT RP on platform, range is: 0, 1 ..., - * (NumOfTBTRP - 1). - */ - Package (2) { "UID", TUID }, - }, - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package (2) { "usb4-host-interface", \_SB.PCI0.TDM1 }, - Package (2) { "usb4-port-number", 1 }, - } - }) - } -} - Method (_S0W, 0x0, NotSerialized) { Return (0x4) diff --git a/src/soc/intel/tigerlake/chipset.cb b/src/soc/intel/tigerlake/chipset.cb index 0d2b7a2..43c99a5 100644 --- a/src/soc/intel/tigerlake/chipset.cb +++ b/src/soc/intel/tigerlake/chipset.cb @@ -5,10 +5,26 @@ device pci 04.0 alias dptf off end device pci 05.0 alias ipu off end device pci 06.0 alias peg off end - device pci 07.0 alias tbt_pcie_rp0 off end - device pci 07.1 alias tbt_pcie_rp1 off end - device pci 07.2 alias tbt_pcie_rp2 off end - device pci 07.3 alias tbt_pcie_rp3 off end + chip drivers/intel/usb4/pcie + register "port_id" = "0" + use tbt_dma0 as usb4_port + device pci 07.0 alias tbt_pcie_rp0 off end + end + chip drivers/intel/usb4/pcie + register "port_id" = "1" + use tbt_dma0 as usb4_port + device pci 07.1 alias tbt_pcie_rp1 off end + end + chip drivers/intel/usb4/pcie + register "port_id" = "0" + use tbt_dma1 as usb4_port + device pci 07.2 alias tbt_pcie_rp2 off end + end + chip drivers/intel/usb4/pcie + register "port_id" = "1" + use tbt_dma1 as usb4_port + device pci 07.3 alias tbt_pcie_rp3 off end + end device pci 08.0 alias gna off end device pci 09.0 alias npk off end device pci 0a.0 alias crashlog off end -- To view, visit https://review.coreboot.org/c/coreboot/+/44917 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2564512d951046e015c148db42fdaf2d4b8b81dd Gerrit-Change-Number: 44917 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 26

Change in coreboot[master]: soc/intel/skylake: Configure L1 substates for PCH root ports
by Nico Huber (Code Review) 15 Oct '20

15 Oct '20

Nico Huber has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39538 ) Change subject: soc/intel/skylake: Configure L1 substates for PCH root ports ...................................................................... soc/intel/skylake: Configure L1 substates for PCH root ports Exposes PcieRpL1Substates to devicetree to allow boards to override this configuration. Tested on an Acer Aspire VN7-572G (Skylake-U). Change-Id: I36150858485715016158595c832c142b0582ddb8 Signed-off-by: Benjamin Doron <benjamin.doron00(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39538 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> --- M src/soc/intel/skylake/chip.c M src/soc/intel/skylake/chip.h 2 files changed, 10 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index dfbdfb8..4139570 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -212,6 +212,8 @@ params->PcieRpMaxPayload[i] = config->PcieRpMaxPayload[i]; if (config->PcieRpAspm[i]) params->PcieRpAspm[i] = config->PcieRpAspm[i] - 1; + if (config->pcie_rp_l1substates[i]) + params->PcieRpL1Substates[i] = config->pcie_rp_l1substates[i] - 1; } /* diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index fa30c1d..5befb01 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -264,6 +264,14 @@ AspmAutoConfig, } PcieRpAspm[CONFIG_MAX_ROOT_PORTS]; + /* PCIe RP L1 substate */ + enum { + L1SS_Default, + L1SS_Disabled, + L1SS_L1_1, + L1SS_L1_2, + } pcie_rp_l1substates[CONFIG_MAX_ROOT_PORTS]; + /* USB related */ struct usb2_port_config usb2_ports[16]; struct usb3_port_config usb3_ports[10]; -- To view, visit https://review.coreboot.org/c/coreboot/+/39538 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I36150858485715016158595c832c142b0582ddb8 Gerrit-Change-Number: 39538 Gerrit-PatchSet: 29 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: soc/intel/skl,cpu/intel: copy AES-NI locking to common cpu code
by Tim Wawrzynczak (Code Review) 15 Oct '20

15 Oct '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46272 ) Change subject: soc/intel/skl,cpu/intel: copy AES-NI locking to common cpu code ...................................................................... Patch Set 6: (1 comment) https://review.coreboot.org/c/coreboot/+/46272/6/src/cpu/intel/common/commo… File src/cpu/intel/common/common_init.c: https://review.coreboot.org/c/coreboot/+/46272/6/src/cpu/intel/common/commo… PS6, Line 280: > I would note that CPUID Leaf 0x1, ecx[25] indicates AES-NI support. […] OH you add it later, sorry. -- To view, visit https://review.coreboot.org/c/coreboot/+/46272 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I81ad5c0d4797b139435c57d3af0a95db94a5c15e Gerrit-Change-Number: 46272 Gerrit-PatchSet: 6 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 14 Oct 2020 21:31:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/skl,cpu/intel: copy AES-NI locking to common cpu code
by Tim Wawrzynczak (Code Review) 15 Oct '20

15 Oct '20

1 0

Change in coreboot[master]: soc/intel/skl,cpu/intel: copy AES-NI locking to common cpu code
by Tim Wawrzynczak (Code Review) 15 Oct '20

15 Oct '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46272 ) Change subject: soc/intel/skl,cpu/intel: copy AES-NI locking to common cpu code ...................................................................... Patch Set 6: (4 comments) https://review.coreboot.org/c/coreboot/+/46272/6/src/cpu/intel/common/commo… File src/cpu/intel/common/common_init.c: https://review.coreboot.org/c/coreboot/+/46272/6/src/cpu/intel/common/commo… PS6, Line 280: I would note that CPUID Leaf 0x1, ecx[25] indicates AES-NI support. Should we verify that first ? https://review.coreboot.org/c/coreboot/+/46272/6/src/cpu/intel/common/commo… PS6, Line 282: (msr.lo & 1) == 0) if (!(msr.lo & AESNI_LOCK_BIT)) https://review.coreboot.org/c/coreboot/+/46272/6/src/cpu/intel/common/commo… PS6, Line 283: 1 AESNI_LOCK_BIT https://review.coreboot.org/c/coreboot/+/46272/6/src/include/cpu/intel/msr.h File src/include/cpu/intel/msr.h: https://review.coreboot.org/c/coreboot/+/46272/6/src/include/cpu/intel/msr.… PS6, Line 9: 0 BIT(0) -- To view, visit https://review.coreboot.org/c/coreboot/+/46272 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I81ad5c0d4797b139435c57d3af0a95db94a5c15e Gerrit-Change-Number: 46272 Gerrit-PatchSet: 6 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 14 Oct 2020 21:28:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit October 2020