coreboot-gerrit October 2020

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: include/cpu/x86: introduce new helper for (un)setting MSRs
by Michael Niewöhner (Code Review) 15 Oct '20

15 Oct '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46354 ) Change subject: include/cpu/x86: introduce new helper for (un)setting MSRs ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/c/coreboot/+/46354/3//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/46354/3//COMMIT_MSG@12 PS3, Line 12: CB:42134 > nit, the commit hash is easier to look up and set in stone. I use […] sounds good -- To view, visit https://review.coreboot.org/c/coreboot/+/46354 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idfe9b66e7cfe78ec295a44a2a193f530349f7689 Gerrit-Change-Number: 46354 Gerrit-PatchSet: 4 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 15 Oct 2020 14:43:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/{cnl,icl,tgl,jsl,ehl,adl}/acpi: generate CPPC entries
by Michael Niewöhner (Code Review) 15 Oct '20

15 Oct '20

Michael Niewöhner has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/45536 ) Change subject: soc/intel/{cnl,icl,tgl,jsl,ehl,adl}/acpi: generate CPPC entries ...................................................................... Abandoned done in intelblocks now -- To view, visit https://review.coreboot.org/c/coreboot/+/45536 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I40d47d18a35002bc9ec55473e94277d89fc5797e Gerrit-Change-Number: 45536 Gerrit-PatchSet: 10 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Elyes HAOUAS Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: soc/intel/icl: enable common CPU code
by Michael Niewöhner (Code Review) 15 Oct '20

15 Oct '20

Hello build bot (Jenkins), Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/45826 to look at the new patch set (#6). Change subject: soc/intel/icl: enable common CPU code ...................................................................... soc/intel/icl: enable common CPU code Enable CPU_INTEL_COMMON to make common CPU code available to CNL, which gets used in CB:45535 and CB:45536 for CPPC entries generation. Note: This also retrieves the VMX Kconfig and enables it by default, like done for SKL and CNL already. Change-Id: I58e86021687fc0a836324f70071f7ea80242b3cb Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/soc/intel/icelake/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/45826/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/45826 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I58e86021687fc0a836324f70071f7ea80242b3cb Gerrit-Change-Number: 45826 Gerrit-PatchSet: 6 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/skl,cpu/intel: copy AES-NI locking to common cpu code
by Tim Wawrzynczak (Code Review) 15 Oct '20

15 Oct '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46272 ) Change subject: soc/intel/skl,cpu/intel: copy AES-NI locking to common cpu code ...................................................................... Patch Set 6: Code-Review+1 (1 comment) https://review.coreboot.org/c/coreboot/+/46272/6/src/include/cpu/intel/msr.h File src/include/cpu/intel/msr.h: https://review.coreboot.org/c/coreboot/+/46272/6/src/include/cpu/intel/msr.… PS6, Line 9: 0 > BIT(0) Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/46272 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I81ad5c0d4797b139435c57d3af0a95db94a5c15e Gerrit-Change-Number: 46272 Gerrit-PatchSet: 6 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 15 Oct 2020 14:22:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: tests: Add lib/imd_cbmem-test test case
by Name of user not set (Code Review) 15 Oct '20

15 Oct '20

Name of user not set #1003143 has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46217 ) Change subject: tests: Add lib/imd_cbmem-test test case ...................................................................... tests: Add lib/imd_cbmem-test test case Signed-off-by: Jakub Czapiga <jacz(a)semihalf.com> Change-Id: I5d84c0b589a9360af93d6215ad35abe6d8ee1559 --- M tests/lib/Makefile.inc A tests/lib/imd_cbmem-test.c 2 files changed, 309 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/46217/1 diff --git a/tests/lib/Makefile.inc b/tests/lib/Makefile.inc index 3062bca..2f381fe 100644 --- a/tests/lib/Makefile.inc +++ b/tests/lib/Makefile.inc @@ -4,6 +4,7 @@ tests-y += b64_decode-test tests-y += hexstrtobin-test tests-y += imd-test +tests-y += imd_cbmem-test string-test-srcs += tests/lib/string-test.c string-test-srcs += src/lib/string.c @@ -17,4 +18,11 @@ imd-test-srcs += tests/lib/imd-test.c imd-test-srcs += tests/stubs/console.c -imd-test-srcs += src/lib/imd.c \ No newline at end of file +imd-test-srcs += src/lib/imd.c + +imd_cbmem-test-srcs += tests/lib/imd_cbmem-test.c +# imd_cbmem-test-srcs += src/lib/imd_cbmem.c +imd_cbmem-test-srcs += tests/stubs/console.c +imd_cbmem-test-srcs += src/lib/imd.c +imd_cbmem-test-srcs += src/lib/bootmem.c +imd_cbmem-test-srcs += src/lib/memrange.c diff --git a/tests/lib/imd_cbmem-test.c b/tests/lib/imd_cbmem-test.c new file mode 100644 index 0000000..2ad0941 --- /dev/null +++ b/tests/lib/imd_cbmem-test.c @@ -0,0 +1,300 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* Include UUT source code directly instead of linking it. This will allow + * access to internal structures and data without having to extract them to + * another header file + */ +#include "../lib/imd_cbmem.c" + +#include <imd.h> +#include <cbmem.h> +#include <stdlib.h> +#include <tests/test.h> +#include <stdio.h> +#include <commonlib/bsd/helpers.h> +#include <imd_private.h> + +#define LIMIT_SZ (LIMIT_ALIGN + 1) + +#define CBMEM_ENTRY_ID 0xA001 +#define CBMEM_SM_ENTRY_ID 0xB001 + +#define CBMEM_SIZE (4 * MiB) + +void reset_imd(void) +{ + imd.lg.limit = (uintptr_t) NULL; + imd.lg.r = NULL; + imd.sm.limit = (uintptr_t) NULL; + imd.sm.r = NULL; +} + +void cbmem_run_init_hooks(int is_recovery) +{ + (void) is_recovery; +} + +static void test_cbmem_top(void **state) +{ + cbmem_top_init_once(); + + if (ENV_ROMSTAGE) + assert_ptr_equal(cbmem_top_chipset(), cbmem_top()); + + if (ENV_POSTCAR || ENV_RAMSTAGE) + assert_ptr_equal((void *)_cbmem_top_ptr, cbmem_top()); +} + +static void test_cbmem_initialize_empty(void **state) +{ + const struct cbmem_entry *found; + + cbmem_initialize_empty(); + + found = cbmem_entry_find(SMALL_REGION_ID); + assert_non_null(found); +} + +static void test_cbmem_initialize_empty_id_size(void **state) +{ + const struct cbmem_entry *found_1, *found_2; + + cbmem_initialize_empty_id_size(CBMEM_ENTRY_ID, CBMEM_ROOT_SIZE); + + found_1 = cbmem_entry_find(SMALL_REGION_ID); + assert_non_null(found_1); + + found_2 = cbmem_entry_find(CBMEM_ENTRY_ID); + assert_non_null(found_2); +} + +static void test_cbmem_initialize(void **state) +{ + int res; + const struct cbmem_entry *found; + + res = cbmem_initialize(); + assert_int_equal(0, res); + + cbmem_initialize_empty(); + + res = cbmem_initialize(); + assert_int_equal(0, res); + + found = cbmem_entry_find(SMALL_REGION_ID); + assert_non_null(found); +} + +static void test_cbmem_initialize_id_size(void **state) +{ + int res; + const struct cbmem_entry *found_1, *found_2; + + res = cbmem_initialize_id_size(0, 0); + assert_int_equal(0, res); + + cbmem_initialize_empty(); + + res = cbmem_initialize_id_size(CBMEM_ENTRY_ID, CBMEM_ROOT_SIZE); + assert_int_equal(0, res); + + found_1 = cbmem_entry_find(SMALL_REGION_ID); + assert_non_null(found_1); + + found_2 = cbmem_entry_find(CBMEM_ENTRY_ID); + assert_non_null(found_2); +} + +static void test_cbmem_recovery(void **state) +{ + int is_wakeup = 1; + assert_int_equal(0, cbmem_recovery(is_wakeup)); + + is_wakeup = 0; + assert_int_equal(0, cbmem_recovery(is_wakeup)); +} + +static void test_cbmem_entry_add(void **state) +{ + int id1 = 0x1; + int id2 = 0x2; + + assert_null(cbmem_entry_find(id1)); + assert_null(cbmem_entry_find(id2)); + + cbmem_initialize_empty_id_size(id1, CBMEM_ROOT_SIZE); + cbmem_entry_add(id2, CBMEM_ROOT_SIZE); + + assert_non_null(cbmem_entry_find(id1)); + assert_non_null(cbmem_entry_find(id2)); +} + +static void test_cbmem_add(void **state) +{ + int id1 = 0x3; + int id2 = 0x4; + + assert_null(cbmem_find(id1)); + assert_null(cbmem_find(id2)); + + cbmem_initialize_empty_id_size(id1, CBMEM_ROOT_SIZE); + cbmem_add(id2, CBMEM_ROOT_SIZE); + + assert_non_null(cbmem_find(id1)); + assert_non_null(cbmem_find(id2)); +} + +static void test_cbmem_entry_find(void **state) +{ + int id1 = 0x6; + int id2 = 0x7; + const struct cbmem_entry *cbm_e1, *cbm_e2, *found_1, *found_2; + + assert_null(cbmem_entry_find(id1)); + + cbmem_initialize_empty(); + cbm_e1 = cbmem_entry_add(id1, CBMEM_ROOT_SIZE); + cbm_e2 = cbmem_entry_add(id2, CBMEM_ROOT_SIZE); + + found_1 = cbmem_entry_find(id1); + assert_non_null(found_1); + assert_ptr_equal(cbm_e1, found_1); + + found_2 = cbmem_entry_find(id2); + assert_non_null(found_2); + assert_ptr_equal(cbm_e2, found_2); +} + +static void test_cbmem_find(void **state) +{ + int id1 = 0x8; + int id2 = 0x9; + void *cbm_e1, *cbm_e2, *found_1, *found_2; + + assert_null(cbmem_find(id1)); + + cbmem_initialize_empty(); + cbm_e1 = cbmem_add(id1, CBMEM_ROOT_SIZE); + cbm_e2 = cbmem_add(id2, CBMEM_ROOT_SIZE); + + found_1 = cbmem_find(id1); + assert_non_null(found_1); + assert_ptr_equal(cbm_e1, found_1); + + found_2 = cbmem_find(id2); + assert_non_null(found_2); + assert_ptr_equal(cbm_e2, found_2); +} + +static void test_cbmem_entry_remove(void **state) +{ + int id1 = 0x10; + int id2 = 0x11; + const struct cbmem_entry *cbm_e1, *cbm_e2; + + assert_int_equal(-1, cbmem_entry_remove(NULL)); + + cbmem_initialize_empty(); + cbm_e1 = cbmem_entry_add(id1, CBMEM_ROOT_SIZE); + cbm_e2 = cbmem_entry_add(id2, CBMEM_ROOT_SIZE); + + assert_int_equal(-1, cbmem_entry_remove(cbm_e1)); + assert_int_equal(0, cbmem_entry_remove(cbm_e2)); + assert_int_equal(0, cbmem_entry_remove(cbm_e1)); +} + +static void test_cbmem_entry_size(void **state) +{ + struct imd_entry i_e = { .size = CBMEM_ROOT_SIZE }; + const struct cbmem_entry *cbm_e = imd_to_cbmem(&i_e); + + assert_int_equal(CBMEM_ROOT_SIZE, cbmem_entry_size(cbm_e)); + + i_e.size = 0; + assert_int_equal(0, cbmem_entry_size(cbm_e)); +} + +static void test_cbmem_entry_start(void **state) +{ + const struct cbmem_entry *cbm_e = NULL; + + assert_null(cbmem_entry_start(cbm_e)); + + cbmem_initialize_empty_id_size(CBMEM_ENTRY_ID, CBMEM_ROOT_SIZE); + cbm_e = cbmem_entry_find(CBMEM_ENTRY_ID); + assert_non_null(cbmem_entry_start(cbm_e)); +} + +static void test_cbmem_add_bootmem(void **state) +{ + void *baseptr = NULL; + size_t size = 0; + + cbmem_get_region(&baseptr, &size); + assert_null(baseptr); + assert_int_equal(0, size); + + cbmem_initialize_empty_id_size(CBMEM_ENTRY_ID, CBMEM_ROOT_SIZE); + + cbmem_add_bootmem(); + + assert_non_null(&baseptr); + assert_int_not_equal(0, &size); +} + +static void test_cbmem_get_region(void **state) +{ + void *baseptr = NULL; + size_t size = 0; + + cbmem_get_region(&baseptr, &size); + assert_null(baseptr); + assert_int_equal(0, size); + + cbmem_initialize_empty_id_size(CBMEM_ENTRY_ID, CBMEM_ROOT_SIZE); + + cbmem_get_region(&baseptr, &size); + assert_non_null(&baseptr); + assert_int_not_equal(0, size); +} + +static int teardown_test_imd_cbmem(void **state) +{ + reset_imd(); + return 0; +} + +static int setup_group_imd_cbmem(void **status) +{ + _cbmem_top_ptr = (uintptr_t)malloc(CBMEM_SIZE) + CBMEM_SIZE; + return 0; +} + +static int teardown_group_imd_cbmem(void **status) +{ + free((void *)_cbmem_top_ptr - CBMEM_SIZE); + return 0; +} + +int main(void) +{ + const struct CMUnitTest tests[] = { + cmocka_unit_test(test_cbmem_top), + cmocka_unit_test_teardown(test_cbmem_initialize_empty, teardown_test_imd_cbmem), + cmocka_unit_test_teardown(test_cbmem_initialize_empty_id_size, teardown_test_imd_cbmem), + cmocka_unit_test_teardown(test_cbmem_initialize, teardown_test_imd_cbmem), + cmocka_unit_test_teardown(test_cbmem_initialize_id_size, teardown_test_imd_cbmem), + cmocka_unit_test_teardown(test_cbmem_recovery, teardown_test_imd_cbmem), + cmocka_unit_test_teardown(test_cbmem_entry_add, teardown_test_imd_cbmem), + cmocka_unit_test_teardown(test_cbmem_add, teardown_test_imd_cbmem), + cmocka_unit_test_teardown(test_cbmem_entry_find, teardown_test_imd_cbmem), + cmocka_unit_test_teardown(test_cbmem_find, teardown_test_imd_cbmem), + cmocka_unit_test_teardown(test_cbmem_entry_remove, teardown_test_imd_cbmem), + cmocka_unit_test_teardown(test_cbmem_entry_size, teardown_test_imd_cbmem), + cmocka_unit_test_teardown(test_cbmem_entry_start, teardown_test_imd_cbmem), + cmocka_unit_test_teardown(test_cbmem_add_bootmem, teardown_test_imd_cbmem), + cmocka_unit_test_teardown(test_cbmem_get_region, teardown_test_imd_cbmem), + }; + + return cmocka_run_group_tests(tests, setup_group_imd_cbmem, teardown_group_imd_cbmem); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/46217 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5d84c0b589a9360af93d6215ad35abe6d8ee1559 Gerrit-Change-Number: 46217 Gerrit-PatchSet: 1 Gerrit-Owner: Name of user not set #1003143 Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/intel/common: rework AES-NI locking
by Michael Niewöhner (Code Review) 15 Oct '20

15 Oct '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46275 ) Change subject: cpu/intel/common: rework AES-NI locking ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/c/coreboot/+/46275/3/src/cpu/intel/common/commo… File src/cpu/intel/common/common_init.c: https://review.coreboot.org/c/coreboot/+/46275/3/src/cpu/intel/common/commo… PS3, Line 279: msr_unset_and_set(MSR_FEATURE_CONFIG, 0, AESNI_LOCK); > I'm not 100% sure about this. Sometimes registers that are already locked […] Ack but let's simplify it: if (rdmsr(MSR_FEATURE_CONFIG) & AESNI_LOCK) return; -- To view, visit https://review.coreboot.org/c/coreboot/+/46275 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib2cda433bbec0192277839c02a1862b8f41340cb Gerrit-Change-Number: 46275 Gerrit-PatchSet: 3 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 15 Oct 2020 13:52:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/skl,cpu/intel: copy AES-NI locking to common cpu code
by Michael Niewöhner (Code Review) 15 Oct '20

15 Oct '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46272 ) Change subject: soc/intel/skl,cpu/intel: copy AES-NI locking to common cpu code ...................................................................... Patch Set 6: (2 comments) https://review.coreboot.org/c/coreboot/+/46272/6/src/cpu/intel/common/commo… File src/cpu/intel/common/common_init.c: https://review.coreboot.org/c/coreboot/+/46272/6/src/cpu/intel/common/commo… PS6, Line 282: (msr.lo & 1) == 0) > if (!(msr. […] As mentioned in the commit message, rework is done in the follow-up ;) https://review.coreboot.org/c/coreboot/+/46272/6/src/cpu/intel/common/commo… PS6, Line 283: 1 > AESNI_LOCK_BIT same as above -- To view, visit https://review.coreboot.org/c/coreboot/+/46272 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I81ad5c0d4797b139435c57d3af0a95db94a5c15e Gerrit-Change-Number: 46272 Gerrit-PatchSet: 6 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 15 Oct 2020 13:52:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/skl,cpu/intel: copy AES-NI locking to common cpu code
by Michael Niewöhner (Code Review) 15 Oct '20

15 Oct '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46272 ) Change subject: soc/intel/skl,cpu/intel: copy AES-NI locking to common cpu code ...................................................................... Patch Set 6: > Patch Set 6: > > I guess I don't see the point of copying this over literally and then modifying it in the next patch? Well, I just wanted it to be clear where the code comes from and keep track of what was modified. Ofc that's not an absolute requirement. -- To view, visit https://review.coreboot.org/c/coreboot/+/46272 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I81ad5c0d4797b139435c57d3af0a95db94a5c15e Gerrit-Change-Number: 46272 Gerrit-PatchSet: 6 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 15 Oct 2020 13:51:08 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: ec/google/chromeec: Update ec_commands.h
by Yidi Lin (Code Review) 15 Oct '20

15 Oct '20

Yidi Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46403 ) Change subject: ec/google/chromeec: Update ec_commands.h ...................................................................... ec/google/chromeec: Update ec_commands.h This change copies ec_commands.h from Chromium OS EC repo at 7b6cb69db. The change also drops unneeded empty lines and coverts license header to SPDX style. BUG=b:147789962 BRANCH=none TEST=emerge-asurada coreboot Change-Id: I9816dab5edb418e76896355a0802c59307c664c4 Signed-off-by: Yidi Lin <yidi.lin(a)mediatek.com> --- M src/ec/google/chromeec/ec_commands.h 1 file changed, 226 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/46403/1 diff --git a/src/ec/google/chromeec/ec_commands.h b/src/ec/google/chromeec/ec_commands.h index 4c3d0bb..4e40c6d 100644 --- a/src/ec/google/chromeec/ec_commands.h +++ b/src/ec/google/chromeec/ec_commands.h @@ -2520,6 +2520,12 @@ */ MOTIONSENSE_CMD_ONLINE_CALIB_READ = 19, + /* + * Activity management + * Retrieve current status of given activity. + */ + MOTIONSENSE_CMD_GET_ACTIVITY = 20, + /* Number of motionsense sub-commands. */ MOTIONSENSE_NUM_CMDS }; @@ -2572,6 +2578,8 @@ MOTIONSENSE_CHIP_LIS2DW12 = 21, MOTIONSENSE_CHIP_LIS2DWL = 22, MOTIONSENSE_CHIP_LIS2DS = 23, + MOTIONSENSE_CHIP_BMI260 = 24, + MOTIONSENSE_CHIP_ICM426XX = 25, MOTIONSENSE_CHIP_MAX, }; @@ -2592,6 +2600,8 @@ /* Each sensor is up to 3-axis. */ union { int16_t data[3]; + /* for sensors using unsigned data */ + uint16_t udata[3]; struct __ec_todo_packed { uint16_t reserved; uint32_t timestamp; @@ -2637,6 +2647,7 @@ MOTIONSENSE_ACTIVITY_SIG_MOTION = 1, MOTIONSENSE_ACTIVITY_DOUBLE_TAP = 2, MOTIONSENSE_ACTIVITY_ORIENTATION = 3, + MOTIONSENSE_ACTIVITY_BODY_DETECTION = 4, }; struct ec_motion_sense_activity { @@ -2820,6 +2831,7 @@ uint32_t max_data_vector; } fifo_read; + /* Used for MOTIONSENSE_CMD_SET_ACTIVITY */ struct ec_motion_sense_activity set_activity; /* Used for MOTIONSENSE_CMD_LID_ANGLE */ @@ -2874,6 +2886,13 @@ uint8_t sensor_num; } online_calib_read; + /* + * Used for MOTIONSENSE_CMD_GET_ACTIVITY. + */ + struct __ec_todo_unpacked { + uint8_t sensor_num; + uint8_t activity; /* enum motionsensor_activity */ + } get_activity; }; } __ec_todo_packed; @@ -3025,6 +3044,10 @@ uint16_t hys_degree; } tablet_mode_threshold; + /* USED for MOTIONSENSE_CMD_GET_ACTIVITY. */ + struct __ec_todo_unpacked { + uint8_t state; + } get_activity; }; } __ec_todo_packed; @@ -4429,6 +4452,7 @@ uint32_t value; /* value to set */ } set_param; }; + uint8_t chgnum; /* Version 1 supports chgnum */ } __ec_todo_packed; struct ec_response_charge_state { @@ -4982,6 +5006,7 @@ EC_CODEC_I2S_RX_SET_SAMPLE_DEPTH = 0x2, EC_CODEC_I2S_RX_SET_DAIFMT = 0x3, EC_CODEC_I2S_RX_SET_BCLK = 0x4, + EC_CODEC_I2S_RX_RESET = 0x5, EC_CODEC_I2S_RX_SUBCMD_COUNT, }; @@ -5095,6 +5120,33 @@ }; /*****************************************************************************/ +/* Commands for PoE PSE controller */ + +#define EC_CMD_PSE 0x00C0 + +enum ec_pse_subcmd { + EC_PSE_STATUS = 0x0, + EC_PSE_ENABLE = 0x1, + EC_PSE_DISABLE = 0x2, + EC_PSE_SUBCMD_COUNT, +}; + +struct __ec_align1 ec_params_pse { + uint8_t cmd; /* enum ec_pse_subcmd */ + uint8_t port; /* PSE port */ +}; + +enum ec_pse_status { + EC_PSE_STATUS_DISABLED = 0x0, + EC_PSE_STATUS_ENABLED = 0x1, + EC_PSE_STATUS_POWERED = 0x2, +}; + +struct __ec_align1 ec_response_pse_status { + uint8_t status; /* enum ec_pse_status */ +}; + +/*****************************************************************************/ /* System commands */ /* @@ -5112,7 +5164,7 @@ EC_REBOOT_COLD = 4, /* Cold-reboot */ EC_REBOOT_DISABLE_JUMP = 5, /* Disable jump until next reboot */ EC_REBOOT_HIBERNATE = 6, /* Hibernate EC */ - EC_REBOOT_HIBERNATE_CLEAR_AP_OFF = 7, /* and clears AP_OFF flag */ + EC_REBOOT_HIBERNATE_CLEAR_AP_OFF = 7, /* and clears AP_IDLE flag */ }; /* Flags for ec_params_reboot_ec.reboot_flags */ @@ -5330,7 +5382,8 @@ uint8_t dp_mode; /* Current DP pin mode (MODE_DP_PIN_[A-E]) */ uint8_t reserved; /* Reserved for future use */ uint8_t control_flags; /* USB_PD_CTRL_*flags */ - uint8_t cable_speed; /* TBT_SS_* cable speed */ + /* TODO: b:158234949 Add definitions for cable speed */ + uint8_t cable_speed; /* USB_R30_SS/TBT_SS_* cable speed */ uint8_t cable_gen; /* TBT_GEN3_* cable rounded support */ } __ec_align1; @@ -5386,6 +5439,7 @@ uint32_t max_power; } __ec_align4; + /* * This command will return the number of USB PD charge port + the number * of dedicated port present. @@ -5587,6 +5641,7 @@ uint8_t port; /* port#, or 0 for events unrelated to a given port */ } __ec_align1; + /* Control USB-PD chip */ #define EC_CMD_PD_CONTROL 0x0119 @@ -5711,6 +5766,8 @@ CBI_TAG_MODEL_ID = 5, /* uint32_t or smaller */ CBI_TAG_FW_CONFIG = 6, /* uint32_t bit field */ CBI_TAG_PCB_SUPPLIER = 7, /* uint32_t or smaller */ + /* Second Source Factory Cache */ + CBI_TAG_SSFC = 8, /* uint32_t bit field */ CBI_TAG_COUNT, }; @@ -5775,6 +5832,9 @@ #define EC_RESET_FLAG_STAY_IN_RO BIT(19) /* Do not select RW in EFS. This * enables PD in RO for Chromebox. */ +#define EC_RESET_FLAG_EFS BIT(20) /* Jumped to this image by EFS */ +#define EC_RESET_FLAG_AP_IDLE BIT(21) /* Leave alone AP */ +#define EC_RESET_FLAG_INITIAL_PWR BIT(22) /* EC had power, then was reset */ struct ec_response_uptime_info { /* @@ -5870,6 +5930,7 @@ int32_t rw_rollback_version; } __ec_align4; + /* Issue AP reset */ #define EC_CMD_AP_RESET 0x0125 @@ -5911,6 +5972,7 @@ }; } __ec_align2; + struct ec_response_locate_chip { uint8_t bus_type; /* enum ec_bus_type */ uint8_t reserved; /* Aligning the following union to 2 bytes */ @@ -6035,6 +6097,7 @@ KEYBOARD_BUTTON_COUNT }; + /*****************************************************************************/ /* * "Get the Keyboard Config". An EC implementing this command is expected to be @@ -6113,6 +6176,164 @@ } __ec_align1; +/* + * Configure smart discharge + */ +#define EC_CMD_SMART_DISCHARGE 0x012B + +#define EC_SMART_DISCHARGE_FLAGS_SET BIT(0) + +/* Discharge rates when the system is in cutoff or hibernation. */ +struct discharge_rate { + uint16_t cutoff; /* Discharge rate (uA) in cutoff */ + uint16_t hibern; /* Discharge rate (uA) in hibernation */ +}; + +struct smart_discharge_zone { + /* When the capacity (mAh) goes below this, EC cuts off the battery. */ + int cutoff; + /* When the capacity (mAh) is below this, EC stays up. */ + int stayup; +}; + +struct ec_params_smart_discharge { + uint8_t flags; /* EC_SMART_DISCHARGE_FLAGS_* */ + /* + * Desired hours for the battery to survive before reaching 0%. Set to + * zero to disable smart discharging. That is, the system hibernates as + * soon as the G3 idle timer expires. + */ + uint16_t hours_to_zero; + /* Set both to zero to keep the current rates. */ + struct discharge_rate drate; +}; + +struct ec_response_smart_discharge { + uint16_t hours_to_zero; + struct discharge_rate drate; + struct smart_discharge_zone dzone; +}; + +/*****************************************************************************/ +/* Voltage regulator controls */ + +/* + * Get basic info of voltage regulator for given index. + * + * Returns the regulator name and supported voltage list in mV. + */ +#define EC_CMD_REGULATOR_GET_INFO 0x012C + +/* Maximum length of regulator name */ +#define EC_REGULATOR_NAME_MAX_LEN 16 + +/* Maximum length of the supported voltage list. */ +#define EC_REGULATOR_VOLTAGE_MAX_COUNT 16 + +struct ec_params_regulator_get_info { + uint32_t index; +} __ec_align4; + +struct ec_response_regulator_get_info { + char name[EC_REGULATOR_NAME_MAX_LEN]; + uint16_t num_voltages; + uint16_t voltages_mv[EC_REGULATOR_VOLTAGE_MAX_COUNT]; +} __ec_align2; + +/* + * Configure the regulator as enabled / disabled. + */ +#define EC_CMD_REGULATOR_ENABLE 0x012D + +struct ec_params_regulator_enable { + uint32_t index; + uint8_t enable; +} __ec_align4; + +/* + * Query if the regulator is enabled. + * + * Returns 1 if the regulator is enabled, 0 if not. + */ +#define EC_CMD_REGULATOR_IS_ENABLED 0x012E + +struct ec_params_regulator_is_enabled { + uint32_t index; +} __ec_align4; + +struct ec_response_regulator_is_enabled { + uint8_t enabled; +} __ec_align1; + +/* + * Set voltage for the voltage regulator within the range specified. + * + * The driver should select the voltage in range closest to min_mv. + * + * Also note that this might be called before the regulator is enabled, and the + * setting should be in effect after the regulator is enabled. + */ +#define EC_CMD_REGULATOR_SET_VOLTAGE 0x012F + +struct ec_params_regulator_set_voltage { + uint32_t index; + uint32_t min_mv; + uint32_t max_mv; +} __ec_align4; + +/* + * Get the currently configured voltage for the voltage regulator. + * + * Note that this might be called before the regulator is enabled, and this + * should return the configured output voltage if the regulator is enabled. + */ +#define EC_CMD_REGULATOR_GET_VOLTAGE 0x0130 + +struct ec_params_regulator_get_voltage { + uint32_t index; +} __ec_align4; + +struct ec_response_regulator_get_voltage { + uint32_t voltage_mv; +} __ec_align4; + +/* + * Gather all discovery information for the given port and partner type. + * + * Note that if discovery has not yet completed, only the currently completed + * responses will be filled in. If the discovery data structures are changed + * in the process of the command running, BUSY will be returned. + * + * VDO field sizes are set to the maximum possible number of VDOs a VDM may + * contain, while the number of SVIDs here is selected to fit within the PROTO2 + * maximum parameter size. + */ +#define EC_CMD_TYPEC_DISCOVERY 0x0131 + +enum typec_partner_type { + TYPEC_PARTNER_SOP = 0, + TYPEC_PARTNER_SOP_PRIME = 1, +}; + +struct ec_params_typec_discovery { + uint8_t port; + uint8_t partner_type; /* enum typec_partner_type */ +} __ec_align1; + +struct svid_mode_info { + uint16_t svid; + uint16_t mode_count; /* Number of modes partner sent */ + uint32_t mode_vdo[6]; /* Max VDOs allowed after VDM header is 6 */ +}; + +struct ec_response_typec_discovery { + uint8_t identity_count; /* Number of identity VDOs partner sent */ + uint8_t svid_count; /* Number of SVIDs partner sent */ + uint16_t reserved; + uint32_t discovery_vdo[6]; /* Max VDOs allowed after VDM header is 6 */ + struct svid_mode_info svids[0]; +} __ec_align1; + /*****************************************************************************/ /* The command range 0x200-0x2FF is reserved for Rotor. */ @@ -6156,6 +6377,8 @@ #define FP_MODE_MATCH BIT(6) /* Reset and re-initialize the sensor. */ #define FP_MODE_RESET_SENSOR BIT(7) +/* Sensor maintenance for dead pixels. */ +#define FP_MODE_SENSOR_MAINTENANCE BIT(8) /* special value: don't change anything just read back current mode */ #define FP_MODE_DONT_CHANGE BIT(31) @@ -6167,6 +6390,7 @@ FP_MODE_ENROLL_IMAGE | \ FP_MODE_MATCH | \ FP_MODE_RESET_SENSOR | \ + FP_MODE_SENSOR_MAINTENANCE | \ FP_MODE_DONT_CHANGE) /* Capture types defined in bits [30..28] */ -- To view, visit https://review.coreboot.org/c/coreboot/+/46403 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9816dab5edb418e76896355a0802c59307c664c4 Gerrit-Change-Number: 46403 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: Update bit field helpers to support more bit field operate
by CK HU (Code Review) 15 Oct '20

15 Oct '20

Hello Duan huayang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/44705 to review the following change. Change subject: Update bit field helpers to support more bit field operate ...................................................................... Update bit field helpers to support more bit field operate Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> Change-Id: I8f182fff45806912da2390939a6652932501d7c5 --- M src/include/device/mmio.h 1 file changed, 25 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/44705/1 diff --git a/src/include/device/mmio.h b/src/include/device/mmio.h index b4461e0..96bf28c 100644 --- a/src/include/device/mmio.h +++ b/src/include/device/mmio.h @@ -150,21 +150,44 @@ _BF_APPLY6(op, __VA_ARGS__)) #define _BF_APPLY8(op, name, value, ...) ((op(name, value)) | \ _BF_APPLY7(op, __VA_ARGS__)) +#define _BF_APPLY9(op, name, value, ...) ((op(name, value)) | \ + _BF_APPLY8(op, __VA_ARGS__)) +#define _BF_APPLY10(op, name, value, ...) ((op(name, value)) | \ + _BF_APPLY9(op, __VA_ARGS__)) +#define _BF_APPLY11(op, name, value, ...) ((op(name, value)) | \ + _BF_APPLY10(op, __VA_ARGS__)) +#define _BF_APPLY12(op, name, value, ...) ((op(name, value)) | \ + _BF_APPLY11(op, __VA_ARGS__)) +#define _BF_APPLY13(op, name, value, ...) ((op(name, value)) | \ + _BF_APPLY12(op, __VA_ARGS__)) +#define _BF_APPLY14(op, name, value, ...) ((op(name, value)) | \ + _BF_APPLY13(op, __VA_ARGS__)) +#define _BF_APPLY15(op, name, value, ...) ((op(name, value)) | \ + _BF_APPLY14(op, __VA_ARGS__)) +#define _BF_APPLY16(op, name, value, ...) ((op(name, value)) | \ + _BF_APPLY15(op, __VA_ARGS__)) #define _BF_APPLYINVALID(...) \ _Static_assert(0, "Invalid arguments for {WRITE,SET}*_BITFIELDS") #define _BF_IMPL2(op, addr, \ n1, v1, n2, v2, n3, v3, n4, v4, n5, v5, n6, v6, n7, v7, n8, v8, \ + n9, v9, n10, v10, n11, v11, n12, v12, n13, v13, n14, v14, n15, v15, n16, v16, \ NARGS, ...) \ \ op(addr, \ _BF_APPLY##NARGS(_BF_MASK, n1, v1, n2, v2, n3, v3, n4, v4, \ - n5, v5, n6, v6, n7, v7, n8, v8), \ + n5, v5, n6, v6, n7, v7, n8, v8, \ + n9, v9, n10, v10, n11, v11, n12, v12, \ + n13, v13, n14, v14, n15, v15, n16, v16 ), \ _BF_APPLY##NARGS(_BF_VALUE, n1, v1, n2, v2, n3, v3, n4, v4, \ - n5, v5, n6, v6, n7, v7, n8, v8)) + n5, v5, n6, v6, n7, v7, n8, v8,\ + n9, v9, n10, v10, n11, v11, n12, v12, \ + n13, v13, n14, v14, n15, v15, n16, v16)) #define _BF_IMPL(op, addr, ...) \ _BF_IMPL2(op, addr, __VA_ARGS__, \ + 16, INVALID, 15, INVALID, 14, INVALID, 13, INVALID, \ + 12, INVALID, 11, INVALID, 10, INVALID, 9, INVALID, \ 8, INVALID, 7, INVALID, 6, INVALID, 5, INVALID, \ 4, INVALID, 3, INVALID, 2, INVALID, 1, INVALID) -- To view, visit https://review.coreboot.org/c/coreboot/+/44705 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8f182fff45806912da2390939a6652932501d7c5 Gerrit-Change-Number: 44705 Gerrit-PatchSet: 1 Gerrit-Owner: CK HU <ck.hu(a)mediatek.com> Gerrit-Reviewer: Duan huayang <huayang.duan(a)mediatek.com> Gerrit-MessageType: newchange

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