Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46465 )
Change subject: soc/intel/skl,acpi/acpigen: convert global CPPC package to local one
......................................................................
Patch Set 4:
This change is ready for review.
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Hello Felix Singer, build bot (Jenkins), Nico Huber, Furquan Shaikh, David Guckian, Paul Menzel, Tim Wawrzynczak, Vanessa Eusebio, Subrata Banik, Andrey Petrov, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46278
to look at the new patch set (#7).
Change subject: {cpu,soc}/intel: replace AES-NI locking by common implemenation call
......................................................................
{cpu,soc}/intel: replace AES-NI locking by common implemenation call
Deduplicate code by using the new common cpu code implementation of
AES-NI locking.
For model_2065x and model_206ax locking was moved from SMM to core init
because the MSR is core-scoped, not package-scoped.
Change-Id: I7ab2d3839ecb758335ef8cc6a0c0c7103db0fa50
Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de>
---
M src/cpu/intel/common/common_init.c
M src/cpu/intel/model_2065x/Kconfig
M src/cpu/intel/model_2065x/finalize.c
M src/cpu/intel/model_2065x/model_2065x_init.c
M src/cpu/intel/model_206ax/Kconfig
M src/cpu/intel/model_206ax/finalize.c
M src/cpu/intel/model_206ax/model_206ax_init.c
M src/include/cpu/intel/msr.h
M src/soc/intel/apollolake/cpu.c
M src/soc/intel/common/block/cpu/cpulib.c
M src/soc/intel/common/block/include/intelblocks/msr.h
M src/soc/intel/denverton_ns/Kconfig
M src/soc/intel/denverton_ns/cpu.c
M src/soc/intel/skylake/cpu.c
14 files changed, 22 insertions(+), 45 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/46278/7
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Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46273 )
Change subject: soc/intel/cnl: lock AES-NI feature if selected
......................................................................
Patch Set 8:
(1 comment)
https://review.coreboot.org/c/coreboot/+/46273/2//COMMIT_MSG
Commit Message:
https://review.coreboot.org/c/coreboot/+/46273/2//COMMIT_MSG@12
PS2, Line 12: Tested by checking the MSR.
> need to test again after dedup changes
Done
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Gerrit-Comment-Date: Thu, 15 Oct 2020 17:08:28 +0000
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Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de>
Gerrit-MessageType: comment
Hello Felix Singer, build bot (Jenkins), Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Aamir Bohra, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46275
to look at the new patch set (#5).
Change subject: cpu/intel/common: rework AES-NI locking
......................................................................
cpu/intel/common: rework AES-NI locking
Simplify the AES-NI code by using msr_set_bit and correct the comment.
Change-Id: Ib2cda433bbec0192277839c02a1862b8f41340cb
Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de>
---
M src/cpu/intel/common/common.h
M src/cpu/intel/common/common_init.c
M src/include/cpu/intel/msr.h
3 files changed, 10 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/46275/5
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Gerrit-MessageType: newpatchset
Hello Felix Singer, build bot (Jenkins), Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Paul Menzel, Subrata Banik, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46354
to look at the new patch set (#5).
Change subject: include/cpu/x86: introduce new helper fors (un)setting MSRs
......................................................................
include/cpu/x86: introduce new helper fors (un)setting MSRs
msr_set_bit can only set single bits in MSRs and causes mixing of bit
positions and bitmasks in the MSR header files. Thus, replace the helper
by versions which can unset and set whole MSR bitmasks, just like the
"and-or"-helper, but in the way commit 64a6b6c was done (inversion done
in the helper). This helps keeping the MSR macros unified in bitmask
style.
In sum, the three helpers msr_set, msr_unset and msr_unset_and_set get
added.
The few uses of msr_set_bit have been replaced by the new version, while
the used macros have been converted accordingly.
Change-Id: Idfe9b66e7cfe78ec295a44a2a193f530349f7689
Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de>
---
M src/cpu/intel/haswell/finalize.c
M src/cpu/intel/model_2065x/finalize.c
M src/cpu/intel/model_206ax/finalize.c
M src/include/cpu/x86/msr.h
M src/soc/intel/common/block/cpu/cpulib.c
M src/soc/intel/common/block/include/intelblocks/msr.h
6 files changed, 48 insertions(+), 22 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/46354/5
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Gerrit-MessageType: newpatchset
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46275 )
Change subject: cpu/intel/common: rework AES-NI locking
......................................................................
Patch Set 4:
(2 comments)
https://review.coreboot.org/c/coreboot/+/46275/3/src/cpu/intel/common/commo…
File src/cpu/intel/common/common_init.c:
https://review.coreboot.org/c/coreboot/+/46275/3/src/cpu/intel/common/commo…
PS3, Line 279: msr_unset_and_set(MSR_FEATURE_CONFIG, 0, AESNI_LOCK);
> It says another write is not allowed, which could mean it won't have any effect, or it could generat […]
Tim, thank you very much. I'll add this
https://review.coreboot.org/c/coreboot/+/46275/4/src/cpu/intel/common/commo…
File src/cpu/intel/common/common_init.c:
https://review.coreboot.org/c/coreboot/+/46275/4/src/cpu/intel/common/commo…
PS4, Line 269: /*
: * Lock AES-NI feature (MSR_FEATURE_CONFIG) to prevent unintended changes
: * to the enablement state as suggested in Intel document 325384-070US.
: */
> This is redundant, it's copied verbatim from the header
So, where would you like to have this? here or in the header?
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Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46275 )
Change subject: cpu/intel/common: rework AES-NI locking
......................................................................
Patch Set 4:
(4 comments)
https://review.coreboot.org/c/coreboot/+/46275/3/src/cpu/intel/common/commo…
File src/cpu/intel/common/common_init.c:
https://review.coreboot.org/c/coreboot/+/46275/3/src/cpu/intel/common/commo…
PS3, Line 279: msr_unset_and_set(MSR_FEATURE_CONFIG, 0, AESNI_LOCK);
> I'm not 100% sure about this. Sometimes registers that are already locked […]
It says another write is not allowed, which could mean it won't have any effect, or it could generate a #GP. The check is definitely required.
https://review.coreboot.org/c/coreboot/+/46275/4/src/cpu/intel/common/commo…
File src/cpu/intel/common/common_init.c:
https://review.coreboot.org/c/coreboot/+/46275/4/src/cpu/intel/common/commo…
PS4, Line 269: /*
: * Lock AES-NI feature (MSR_FEATURE_CONFIG) to prevent unintended changes
: * to the enablement state as suggested in Intel document 325384-070US.
: */
This is redundant, it's copied verbatim from the header
https://review.coreboot.org/c/coreboot/+/46275/4/src/cpu/intel/common/commo…
PS4, Line 279: msr_unset_and_set
This is where it may still be helpful to have another function like msr_set_bits, that can just call msr_unset_and_set and pass 0 as the 2nd argument.
https://review.coreboot.org/c/coreboot/+/46275/4/src/include/cpu/intel/msr.h
File src/include/cpu/intel/msr.h:
https://review.coreboot.org/c/coreboot/+/46275/4/src/include/cpu/intel/msr.…
PS4, Line 9: (1 << 0)
How about `BIT(0)` ? (would require #include <types.h>)
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