coreboot-gerrit October 2020

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Change in coreboot[master]: mb/google/dedede: replace dt option by MSR write for disabling HWP ca...
by Matt DeVillier (Code Review) 15 Oct '20

15 Oct '20

Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46459 ) Change subject: mb/google/dedede: replace dt option by MSR write for disabling HWP capability ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/c/coreboot/+/46459/2/src/mainboard/google/deded… File src/mainboard/google/dedede/variants/waddledee/variant.c: https://review.coreboot.org/c/coreboot/+/46459/2/src/mainboard/google/deded… PS2, Line 17: msr = rdmsr(MSR_MISC_PWR_MGMT); : msr.lo &= ~MISC_PWR_MGMT_ISST_EN; : wrmsr(MSR_MISC_PWR_MGMT, msr); seems like this should just be put into a function in the msr block, since we've got 2 instances of the same code, and potentially more in the future. Though TBH, this doesn't make much sense as implemented, the correlation between board version and ISST enablement -- To view, visit https://review.coreboot.org/c/coreboot/+/46459 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic335c0bf03a5b07130f79c24107a1b1b0ae75611 Gerrit-Change-Number: 46459 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 15 Oct 2020 18:41:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/intel/common: correct MSR for the Nominal Performance in CPPC
by Matt Delco (Code Review) 15 Oct '20

15 Oct '20

Matt Delco has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46464 ) Change subject: cpu/intel/common: correct MSR for the Nominal Performance in CPPC ...................................................................... Patch Set 4: Code-Review+1 Seems alright to me, though I can't speak to the msr.h part. It's been awhile so I'm not sure if the use of 0x771 was accidental (i.e., overlooked that this field was an exception to how the ACPI definition seemed to go along with the MSR layout), or intentional (e.g., looked at an older reference or tried to avoid using an MSR that might not be present). In any case, this change seems consistent with other firmwares and Skylake is reading from MSR_PLATFORM_INFO in other places so I shouldn't be too concerned about whether it's present or not. -- To view, visit https://review.coreboot.org/c/coreboot/+/46464 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic2c27fd3e14af18aa4101c0acd7a5ede15d1f3a9 Gerrit-Change-Number: 46464 Gerrit-PatchSet: 4 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 15 Oct 2020 18:36:08 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: vc/amd/fsp/picasso: Remove typedefs in bl_syscall_public.h
by Martin Roth (Code Review) 15 Oct '20

15 Oct '20

Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46334 ) Change subject: vc/amd/fsp/picasso: Remove typedefs in bl_syscall_public.h ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/46334 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I403075e18886b566f576d9ca0d198c2f5e9c3d96 Gerrit-Change-Number: 46334 Gerrit-PatchSet: 2 Gerrit-Owner: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Reviewer: Justin Frodsham <justin.frodsham(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 15 Oct 2020 18:29:54 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: vc/amd/fsp/picasso: Remove typedefs in bl_syscall_public.h
by Jason Glenesk (Code Review) 15 Oct '20

15 Oct '20

Jason Glenesk has uploaded a new patch set (#2) to the change originally created by Jason Glenesk. ( https://review.coreboot.org/c/coreboot/+/46334 ) Change subject: vc/amd/fsp/picasso: Remove typedefs in bl_syscall_public.h ...................................................................... vc/amd/fsp/picasso: Remove typedefs in bl_syscall_public.h Remove all typedefs and cleanup references to all structs and enums. BUG=b:159061802 TEST=Boot morphius to shell. Signed-off-by: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Change-Id: I403075e18886b566f576d9ca0d198c2f5e9c3d96 --- M src/soc/amd/picasso/psp_verstage/fch.c M src/soc/amd/picasso/psp_verstage/svc.c M src/soc/amd/picasso/psp_verstage/vboot_crypto.c M src/vendorcode/amd/fsp/picasso/include/bl_uapp/bl_syscall_public.h 4 files changed, 57 insertions(+), 68 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/46334/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/46334 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I403075e18886b566f576d9ca0d198c2f5e9c3d96 Gerrit-Change-Number: 46334 Gerrit-PatchSet: 2 Gerrit-Owner: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Reviewer: Justin Frodsham <justin.frodsham(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/amd/picasso: Remove typedefs in bl_syscall_public.h
by Jason Glenesk (Code Review) 15 Oct '20

15 Oct '20

Jason Glenesk has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46334 ) Change subject: soc/amd/picasso: Remove typedefs in bl_syscall_public.h ...................................................................... Patch Set 1: Please help to review this change. -- To view, visit https://review.coreboot.org/c/coreboot/+/46334 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I403075e18886b566f576d9ca0d198c2f5e9c3d96 Gerrit-Change-Number: 46334 Gerrit-PatchSet: 1 Gerrit-Owner: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Reviewer: Justin Frodsham <justin.frodsham(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 15 Oct 2020 18:24:55 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/acpi: rename uuid for s0ix
by Angel Pons (Code Review) 15 Oct '20

15 Oct '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46468 ) Change subject: soc/intel/common/acpi: rename uuid for s0ix ...................................................................... Patch Set 1: Code-Review+1 (1 comment) https://review.coreboot.org/c/coreboot/+/46468/1//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/46468/1//COMMIT_MSG@11 PS1, Line 11: CB I see... nothing? I guess you forgot to fill this in? -- To view, visit https://review.coreboot.org/c/coreboot/+/46468 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic62c37090ad1b747f9d7d204363cc58f96ef67ef Gerrit-Change-Number: 46468 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 15 Oct 2020 18:07:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/acpi: correct indentation
by Angel Pons (Code Review) 15 Oct '20

15 Oct '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46467 ) Change subject: soc/intel/common/acpi: correct indentation ...................................................................... Patch Set 1: Code-Review+1 (1 comment) https://review.coreboot.org/c/coreboot/+/46467/1//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/46467/1//COMMIT_MSG@7 PS1, Line 7: soc/intel/common/acpi: correct indentation This change should be reproducible. Mind checking this for at least one board using this file, please? -- To view, visit https://review.coreboot.org/c/coreboot/+/46467 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice6cef402dfcc33f1fc7fdced66d38c380d338e5 Gerrit-Change-Number: 46467 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 15 Oct 2020 18:06:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mrc_cache: Add config SAVE_MRC_CACHE for checking TPM hash
by Shelley Chen (Code Review) 15 Oct '20

15 Oct '20

Shelley Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46433 ) Change subject: mrc_cache: Add config SAVE_MRC_CACHE for checking TPM hash ...................................................................... mrc_cache: Add config SAVE_MRC_CACHE for checking TPM hash As the mrc_cache training data is stored in RW, we calculate and store a hash of the data in TPM NVRAM space. This config will enable the calculation and storing of the hash. BUG=b:150502246 BRANCH=None TEST=None Change-Id: I4f8b00bec283683788da820de460cbe30719a1fb Signed-off-by: Shelley Chen <shchen(a)google.com> --- M src/drivers/mrc_cache/Kconfig 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/46433/1 diff --git a/src/drivers/mrc_cache/Kconfig b/src/drivers/mrc_cache/Kconfig index e09c5d8..2017b31 100644 --- a/src/drivers/mrc_cache/Kconfig +++ b/src/drivers/mrc_cache/Kconfig @@ -49,4 +49,11 @@ that need to write back the MRC data in late ramstage boot states (MRC_WRITE_NV_LATE). +config SAVE_MRC_HASH + bool + default y + help + Store a hash of the MRC_CACHE training data to ensure in + TPM NVRAM space. + endif # CACHE_MRC_SETTINGS -- To view, visit https://review.coreboot.org/c/coreboot/+/46433 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4f8b00bec283683788da820de460cbe30719a1fb Gerrit-Change-Number: 46433 Gerrit-PatchSet: 1 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: Fixed feedback from generic functions
by Shelley Chen (Code Review) 15 Oct '20

15 Oct '20

Shelley Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46473 ) Change subject: Fixed feedback from generic functions ...................................................................... Fixed feedback from generic functions Change-Id: I023145af34c223f8e95db7b92fedfcebd912af14 Signed-off-by: Shelley Chen <shchen(a)google.com> --- M src/security/vboot/antirollback.h M src/security/vboot/mrc_cache_hash_tpm.c M src/security/vboot/secdata_tpm.c M src/security/vboot/vboot_logic.c 4 files changed, 14 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/46473/1 diff --git a/src/security/vboot/antirollback.h b/src/security/vboot/antirollback.h index d66281a..eb5978a 100644 --- a/src/security/vboot/antirollback.h +++ b/src/security/vboot/antirollback.h @@ -22,8 +22,10 @@ * want to use 0x1009 for something else. */ #define BACKUP_NV_INDEX 0x1009 #define FWMP_NV_INDEX 0x100a -#define REC_HASH_NV_INDEX 0x100b -/* 0x100c is used for OOBE autoconfig public key hashes */ +/* 0x100b: Hash of MRC_CACHE training data for recovery boot */ +#define MRC_REC_HASH_NV_INDEX 0x100b +/* 0x100c: OOBE autoconfig public key hashes */ +/* 0x100d: Hash of MRC_CACHE training data for normal boot */ #define MRC_RW_HASH_NV_INDEX 0x100d #define HASH_NV_SIZE VB2_SHA256_DIGEST_SIZE diff --git a/src/security/vboot/mrc_cache_hash_tpm.c b/src/security/vboot/mrc_cache_hash_tpm.c index 525e97f..f5b3175 100644 --- a/src/security/vboot/mrc_cache_hash_tpm.c +++ b/src/security/vboot/mrc_cache_hash_tpm.c @@ -24,7 +24,7 @@ }; const uint8_t *hash_ptr = data_hash; uint32_t hash_idx = vboot_recovery_mode_enabled() ? - REC_HASH_NV_INDEX : MRC_RW_HASH_NV_INDEX; + MRC_REC_HASH_NV_INDEX : MRC_RW_HASH_NV_INDEX; /* Initialize TPM driver. */ if (tlcl_lib_init() != VB2_SUCCESS) { @@ -62,9 +62,9 @@ uint8_t data_hash[VB2_SHA256_DIGEST_SIZE]; uint8_t tpm_hash[VB2_SHA256_DIGEST_SIZE]; uint32_t hash_idx = vboot_recovery_mode_enabled() ? - REC_HASH_NV_INDEX : MRC_RW_HASH_NV_INDEX; + MRC_REC_HASH_NV_INDEX : MRC_RW_HASH_NV_INDEX; - /* Calculate hash of data read from RECOVERY_MRC_CACHE. */ + /* Calculate hash of data read from MRC_CACHE. */ if (vb2_digest_buffer(data, size, VB2_HASH_SHA256, data_hash, sizeof(data_hash))) { printk(BIOS_ERR, "MRC: SHA-256 calculation failed for data.\n"); diff --git a/src/security/vboot/secdata_tpm.c b/src/security/vboot/secdata_tpm.c index 0c3d9e7..2f819d7 100644 --- a/src/security/vboot/secdata_tpm.c +++ b/src/security/vboot/secdata_tpm.c @@ -164,10 +164,12 @@ static uint32_t set_hash_space(uint32_t index, const uint8_t *data) { + bool recovery_boot = (index == MRC_REC_HASH_NV_INDEX); return set_space("MRC Hash", index, data, HASH_NV_SIZE, - ro_space_attributes, pcr0_unchanged_policy, - sizeof(pcr0_unchanged_policy)); + recovery_boot ? ro_space_attributes : rw_space_attributes, + recovery_boot ? pcr0_unchanged_policy : NULL, + recovery_boot ? sizeof(pcr0_unchanged_policy) : 0); } static uint32_t _factory_initialize_tpm(struct vb2_context *ctx) @@ -185,7 +187,7 @@ RETURN_ON_FAILURE(set_kernel_space(ctx->secdata_kernel)); if (CONFIG(VBOOT_HAS_REC_HASH_SPACE)) - RETURN_ON_FAILURE(set_hash_space(REC_HASH_NV_INDEX, rec_hash_data)); + RETURN_ON_FAILURE(set_hash_space(MRC_REC_HASH_NV_INDEX, rec_hash_data)); RETURN_ON_FAILURE(set_firmware_space(ctx->secdata_firmware)); @@ -307,7 +309,7 @@ /* Define and set rec hash space, if available. */ if (CONFIG(VBOOT_HAS_REC_HASH_SPACE)) - RETURN_ON_FAILURE(set_hash_space(REC_HASH_NV_INDEX, rec_hash_data)); + RETURN_ON_FAILURE(set_hash_space(MRC_REC_HASH_NV_INDEX, rec_hash_data)); return TPM_SUCCESS; } diff --git a/src/security/vboot/vboot_logic.c b/src/security/vboot/vboot_logic.c index 873e796..509a327 100644 --- a/src/security/vboot/vboot_logic.c +++ b/src/security/vboot/vboot_logic.c @@ -404,7 +404,7 @@ /* Lock rec hash space if available. */ if (CONFIG(VBOOT_HAS_REC_HASH_SPACE)) { - rv = antirollback_lock_space_hash(REC_HASH_NV_INDEX); + rv = antirollback_lock_space_hash(MRC_REC_HASH_NV_INDEX); if (rv) { printk(BIOS_INFO, "Failed to lock rec hash space(%x)\n", rv); -- To view, visit https://review.coreboot.org/c/coreboot/+/46473 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I023145af34c223f8e95db7b92fedfcebd912af14 Gerrit-Change-Number: 46473 Gerrit-PatchSet: 1 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/intel/usb4: Add driver for USB4 PCIe root port
by Duncan Laurie (Code Review) 15 Oct '20

15 Oct '20

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44915 ) Change subject: drivers/intel/usb4: Add driver for USB4 PCIe root port ...................................................................... drivers/intel/usb4: Add driver for USB4 PCIe root port This driver will generate the ACPI _DSD for the USB4 PCIe root port properties instead of using static ASL. It assigns the USB4 port number and marks the port as external and hotplug capable. Signed-off-by: Duncan Laurie <dlaurie(a)google.com> Change-Id: I7086b06346ce63fab6bef4077fb76ae1d30dc1eb --- A src/drivers/intel/usb4/Kconfig A src/drivers/intel/usb4/Makefile.inc A src/drivers/intel/usb4/pcie/Kconfig A src/drivers/intel/usb4/pcie/Makefile.inc A src/drivers/intel/usb4/pcie/chip.h A src/drivers/intel/usb4/pcie/pcie.c 6 files changed, 99 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/44915/1 diff --git a/src/drivers/intel/usb4/Kconfig b/src/drivers/intel/usb4/Kconfig new file mode 100644 index 0000000..93501aa --- /dev/null +++ b/src/drivers/intel/usb4/Kconfig @@ -0,0 +1 @@ +source "src/drivers/intel/usb4/*/Kconfig" diff --git a/src/drivers/intel/usb4/Makefile.inc b/src/drivers/intel/usb4/Makefile.inc new file mode 100644 index 0000000..4c02663 --- /dev/null +++ b/src/drivers/intel/usb4/Makefile.inc @@ -0,0 +1 @@ +subdirs-y += ./* diff --git a/src/drivers/intel/usb4/pcie/Kconfig b/src/drivers/intel/usb4/pcie/Kconfig new file mode 100644 index 0000000..6363939 --- /dev/null +++ b/src/drivers/intel/usb4/pcie/Kconfig @@ -0,0 +1,2 @@ +config DRIVERS_INTEL_USB4_PCIE + bool diff --git a/src/drivers/intel/usb4/pcie/Makefile.inc b/src/drivers/intel/usb4/pcie/Makefile.inc new file mode 100644 index 0000000..b5d3e94 --- /dev/null +++ b/src/drivers/intel/usb4/pcie/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_DRIVERS_INTEL_USB4_PCIE) += pcie.c diff --git a/src/drivers/intel/usb4/pcie/chip.h b/src/drivers/intel/usb4/pcie/chip.h new file mode 100644 index 0000000..b821d47 --- /dev/null +++ b/src/drivers/intel/usb4/pcie/chip.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __DRIVERS_INTEL_USB4_PCIE_H__ +#define __DRIVERS_INTEL_USB4_PCIE_H__ + +struct drivers_intel_usb4_pcie_config { + const char *desc; + + /* USB port number */ + unsigned int port_id; + + /* Pointer to USB4 device that this PCIe root port is routed to. */ + DEVTREE_CONST struct device *usb4_port; +}; + +#endif /* __DRIVERS_INTEL_USB4_PCIE_H__ */ diff --git a/src/drivers/intel/usb4/pcie/pcie.c b/src/drivers/intel/usb4/pcie/pcie.c new file mode 100644 index 0000000..bba803f --- /dev/null +++ b/src/drivers/intel/usb4/pcie/pcie.c @@ -0,0 +1,78 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <acpi/acpigen.h> +#include <console/console.h> +#include <device/device.h> +#include <device/path.h> +#include <device/pci_def.h> +#include <stdlib.h> +#include <string.h> +#include "chip.h" + +#define PCI_HOTPLUG_IN_D3_UUID "6211E2C0-58A3-4AF3-90E1-927A4E0C55A4" +#define PCI_EXTERNAL_PORT_UUID "EFCC06CC-73AC-4BC3-BFF0-76143807C389" + +static void usb4_pcie_fill_ssdt(const struct device *dev) +{ + struct drivers_intel_usb4_pcie_config *config = dev->chip_info; + struct acpi_dp *dsd, *pkg; + const char *usb4_path; + + if (!dev->enabled) + return; + if (!config->usb4_port) + return; + + /* Get ACPI path to USB4 device. */ + usb4_path = acpi_device_path(config->usb4_port); + if (!usb4_path) + return; + usb4_path = strdup(usb4_path); + + acpigen_write_scope(acpi_device_path(dev)); + + /* Add pointer to USB4 port controller. */ + dsd = acpi_dp_new_table("_DSD"); + acpi_dp_add_reference(dsd, "usb4-host-interface", usb4_path); + acpi_dp_add_integer(dsd, "usb4-port-number", config->port_id); + + /* Indicate that device supports hotplug in D3. */ + pkg = acpi_dp_new_table(PCI_HOTPLUG_IN_D3_UUID); + acpi_dp_add_integer(pkg, "HotPlugSupportInD3", 1); + acpi_dp_add_package(dsd, pkg); + + /* Indicate that port is external. */ + pkg = acpi_dp_new_table(PCI_EXTERNAL_PORT_UUID); + acpi_dp_add_integer(pkg, "ExternalFacingPort", 1); + acpi_dp_add_integer(pkg, "UID", config->port_id); + + acpi_dp_add_package(dsd, pkg); + acpi_dp_write(dsd); + + acpigen_pop_len(); /* Scope */ + + printk(BIOS_INFO, "%s: %s at %s\n", acpi_device_path(dev), config->desc, dev_path(dev)); +} + +static struct device_operations usb4_pcie_dev_ops = { + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, + .acpi_fill_ssdt = usb4_pcie_fill_ssdt, +}; + +static void usb4_pcie_enable(struct device *dev) +{ + struct drivers_intel_usb4_pcie_config *config = dev->chip_info; + + dev->ops = &usb4_pcie_dev_ops; + + if (config->desc) + dev->name = config->desc; + else + config->desc = dev->chip_ops->name; +} + +struct chip_operations drivers_intel_usb4_pcie_ops = { + CHIP_NAME("Intel USB4 PCIe Root Port") + .enable_dev = usb4_pcie_enable +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/44915 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7086b06346ce63fab6bef4077fb76ae1d30dc1eb Gerrit-Change-Number: 44915 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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coreboot-gerrit October 2020