coreboot-gerrit October 2020

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: include/cpu/x86: introduce new helper for (un)setting MSRs
by Tim Wawrzynczak (Code Review) 15 Oct '20

15 Oct '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46354 ) Change subject: include/cpu/x86: introduce new helper for (un)setting MSRs ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/c/coreboot/+/46354/3/src/cpu/intel/haswell/fina… File src/cpu/intel/haswell/finalize.c: https://review.coreboot.org/c/coreboot/+/46354/3/src/cpu/intel/haswell/fina… PS3, Line 10: (1 << 0) nit: we should use the BIT macro (types.h) more often 😊 -- To view, visit https://review.coreboot.org/c/coreboot/+/46354 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idfe9b66e7cfe78ec295a44a2a193f530349f7689 Gerrit-Change-Number: 46354 Gerrit-PatchSet: 3 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 14 Oct 2020 21:20:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/skylake/cpu.c: Fix comment coding style
by Angel Pons (Code Review) 14 Oct '20

14 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46428 ) Change subject: soc/intel/skylake/cpu.c: Fix comment coding style ...................................................................... soc/intel/skylake/cpu.c: Fix comment coding style This comment does not follow any of the styles outlined in the coding style page of the documentation. Adjust it to match the preferred style. Change-Id: Idf6d0ea69a08e378266b4256c476580889adfca8 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/skylake/cpu.c 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/46428/1 diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 79fcda1..f1b40f6 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -34,10 +34,10 @@ if (conf->speed_shift_enable) { /* - * Kernel driver checks CPUID.06h:EAX[Bit 7] to determine if HWP - is supported or not. coreboot needs to configure MSR 0x1AA - which is then reflected in the CPUID register. - */ + * Kernel driver checks CPUID.06h:EAX[Bit 7] to determine if HWP + * is supported or not. coreboot needs to configure MSR 0x1AA + * which is then reflected in the CPUID register. + */ msr = rdmsr(MSR_MISC_PWR_MGMT); msr.lo |= MISC_PWR_MGMT_ISST_EN; /* Enable Speed Shift */ msr.lo |= MISC_PWR_MGMT_ISST_EN_INT; /* Enable Interrupt */ -- To view, visit https://review.coreboot.org/c/coreboot/+/46428 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idf6d0ea69a08e378266b4256c476580889adfca8 Gerrit-Change-Number: 46428 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common: drop default to enable the PIT if SeaBIOS is chosen
by Nico Huber (Code Review) 14 Oct '20

14 Oct '20

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46301 ) Change subject: soc/intel/common: drop default to enable the PIT if SeaBIOS is chosen ...................................................................... Patch Set 1: > Well. Sure that actually works? > > The pmtimer is used in case seabios runs on qemu and initializes the (virtual) acpi pci device. > I doubt this also happens when running as coreboot payload. I have reason to assume it does: platform_hardware_setup() calls coreboot_platform_setup() calls find_acpi_features() calls pmtimer_setup(). Didn't test it though, but I assume the PM timer would be used. And the PM timer always works as it's emulated in the worst case :) -- To view, visit https://review.coreboot.org/c/coreboot/+/46301 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd75800678707a92110682347c7cfb93e25109a4 Gerrit-Change-Number: 46301 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Gerd Hoffmann <kraxel(a)redhat.com> Gerrit-Reviewer: Kevin O'Connor <kevin(a)koconnor.net> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 14 Oct 2020 20:33:42 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tigerlake: Replace soc_get_pmc_mux_device with device pointers
by Nick Vaccaro (Code Review) 14 Oct '20

14 Oct '20

Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45747 ) Change subject: soc/intel/tigerlake: Replace soc_get_pmc_mux_device with device pointers ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/45747 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie00834c79bd5304998adaccb388ae74a108192b1 Gerrit-Change-Number: 45747 Gerrit-PatchSet: 7 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 14 Oct 2020 20:14:57 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: libpayload/x86: Try to discover invariant TSC rate
by Angel Pons (Code Review) 14 Oct '20

14 Oct '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34170 ) Change subject: libpayload/x86: Try to discover invariant TSC rate ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/c/coreboot/+/34170/4/payloads/libpayload/arch/x… File payloads/libpayload/arch/x86/timer.c: https://review.coreboot.org/c/coreboot/+/34170/4/payloads/libpayload/arch/x… PS4, Line 176: _rdmsr(MSR_PLATFORM_INFO) >> 8 > lol, I can definitely drop those below. But would really not like to add […] reminds me I first thought of replying "to worsen readability?" but thought it would be a tad bit too rude. -- To view, visit https://review.coreboot.org/c/coreboot/+/34170 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic6607ee2a8b41c2be9dc1bb4f1e23e652bb33889 Gerrit-Change-Number: 34170 Gerrit-PatchSet: 4 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 14 Oct 2020 20:03:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: libpayload/storage/ahci: Use pci_dev struct in ahci_initialize()
by Felix Singer (Code Review) 14 Oct '20

14 Oct '20

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46426 ) Change subject: libpayload/storage/ahci: Use pci_dev struct in ahci_initialize() ...................................................................... libpayload/storage/ahci: Use pci_dev struct in ahci_initialize() Change-Id: I559f1aba6985ebadc0a9b2d2db0f7fa1a6c24af2 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M payloads/libpayload/drivers/storage/ahci.c M payloads/libpayload/drivers/storage/storage.c M payloads/libpayload/include/storage/ahci.h 3 files changed, 14 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/46426/1 diff --git a/payloads/libpayload/drivers/storage/ahci.c b/payloads/libpayload/drivers/storage/ahci.c index be54686..7c67182 100644 --- a/payloads/libpayload/drivers/storage/ahci.c +++ b/payloads/libpayload/drivers/storage/ahci.c @@ -228,34 +228,33 @@ }; #endif -void ahci_initialize(pcidev_t dev) +void ahci_initialize(struct pci_dev *dev) { int i; + pcidev_t pcidev = PCI_DEV(dev->bus, dev->dev, dev->func); + if (dev->device_class != PCI_CLASS_STORAGE_AHCI) return; - const u16 vendor = pci_read_config16(dev, 0x00); - const u16 device = pci_read_config16(dev, 0x02); - #if CONFIG(LP_STORAGE_AHCI_ONLY_TESTED) - const u32 vendor_device = pci_read_config32(dev, 0x0); + const u32 vendor_device = dev->vendor_id | dev->device_id >> 16; for (i = 0; i < ARRAY_SIZE(working_controllers); ++i) if (vendor_device == working_controllers[i]) break; if (i == ARRAY_SIZE(working_controllers)) { printf("ahci: Not using untested SATA controller " - "%02x:%02x.%02x (%04x:%04x).\n", PCI_BUS(dev), - PCI_SLOT(dev), PCI_FUNC(dev), vendor, device); + "%02x:%02x.%02x (%04x:%04x).\n", dev->bus, + dev->dev, dev->func, dev->vendor_id, dev->device_id); return; } #endif printf("ahci: Found SATA controller %02x:%02x.%02x (%04x:%04x).\n", - PCI_BUS(dev), PCI_SLOT(dev), PCI_FUNC(dev), vendor, device); + dev->bus, dev->dev, dev->func, dev->vendor_id, dev->device_id); hba_ctrl_t *const ctrl = phys_to_virt( - pci_read_config32(dev, 0x24) & ~0x3ff); + pci_read_config32(pcidev, 0x24) & ~0x3ff); hba_port_t *const ports = ctrl->ports; /* Reset host controller. */ @@ -274,8 +273,8 @@ ctrl->global_ctrl |= HBA_CTRL_AHCI_EN; /* Enable bus mastering. */ - const u16 command = pci_read_config16(dev, PCI_COMMAND); - pci_write_config16(dev, PCI_COMMAND, command | PCI_COMMAND_MASTER); + const u16 command = pci_read_config16(pcidev, PCI_COMMAND); + pci_write_config16(pcidev, PCI_COMMAND, command | PCI_COMMAND_MASTER); /* Probe for devices. */ for (i = 0; i < 32; ++i) { diff --git a/payloads/libpayload/drivers/storage/storage.c b/payloads/libpayload/drivers/storage/storage.c index e720a2d..f2bde77 100644 --- a/payloads/libpayload/drivers/storage/storage.c +++ b/payloads/libpayload/drivers/storage/storage.c @@ -112,11 +112,9 @@ struct pci_dev *dev; for (dev = lib_sysinfo.pacc->devices; dev; dev = dev->next) { - const uint32_t pcidev = PCI_DEV(dev->bus, dev->dev, dev->func); - switch (dev->device_class) { case PCI_CLASS_STORAGE_AHCI: - ahci_initialize(pcidev); + ahci_initialize(dev); break; default: break; diff --git a/payloads/libpayload/include/storage/ahci.h b/payloads/libpayload/include/storage/ahci.h index 2843624..18a0920 100644 --- a/payloads/libpayload/include/storage/ahci.h +++ b/payloads/libpayload/include/storage/ahci.h @@ -26,9 +26,11 @@ * SUCH DAMAGE. */ +#include <pci/pci.h> + #ifndef _STORAGE_AHCI_H #define _STORAGE_AHCI_H -void ahci_initialize(pcidev_t dev); +void ahci_initialize(struct pci_dev *dev); #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/46426 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I559f1aba6985ebadc0a9b2d2db0f7fa1a6c24af2 Gerrit-Change-Number: 46426 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: newchange

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Change in coreboot[master]: libpayload/storage/ahci: Read device class from pcidev struct
by Felix Singer (Code Review) 14 Oct '20

14 Oct '20

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46425 ) Change subject: libpayload/storage/ahci: Read device class from pcidev struct ...................................................................... libpayload/storage/ahci: Read device class from pcidev struct Read device class from pcidev struct Change-Id: I2d5673c631d978d8ebd0c4a90962ab9cccaf40a2 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M payloads/libpayload/drivers/storage/ahci.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/46425/1 diff --git a/payloads/libpayload/drivers/storage/ahci.c b/payloads/libpayload/drivers/storage/ahci.c index e54bfbf..be54686 100644 --- a/payloads/libpayload/drivers/storage/ahci.c +++ b/payloads/libpayload/drivers/storage/ahci.c @@ -232,9 +232,9 @@ { int i; - const u16 class = pci_read_config16(dev, 0xa); - if (class != 0x0106) + if (dev->device_class != PCI_CLASS_STORAGE_AHCI) return; + const u16 vendor = pci_read_config16(dev, 0x00); const u16 device = pci_read_config16(dev, 0x02); -- To view, visit https://review.coreboot.org/c/coreboot/+/46425 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2d5673c631d978d8ebd0c4a90962ab9cccaf40a2 Gerrit-Change-Number: 46425 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/icl: enable common CPU code
by Nico Huber (Code Review) 14 Oct '20

14 Oct '20

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45826 ) Change subject: soc/intel/icl: enable common CPU code ...................................................................... Patch Set 5: (1 comment) https://review.coreboot.org/c/coreboot/+/45826/2/src/soc/intel/icelake/roms… File src/soc/intel/icelake/romstage/fsp_params.c: https://review.coreboot.org/c/coreboot/+/45826/2/src/soc/intel/icelake/roms… PS2, Line 59: m_cfg->VmxEnable = CONFIG(ENABLE_VMX); > This already configures VMX in FSP and set the feature lock bit (FC_LOCK MSR). […] That's a bit annoying. I would prefer to mimic that in Kconfig then, i.e. what you proposed config ENABLE_VMX select ...LOCK and always call the lock function in coreboot. -- To view, visit https://review.coreboot.org/c/coreboot/+/45826 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I58e86021687fc0a836324f70071f7ea80242b3cb Gerrit-Change-Number: 45826 Gerrit-PatchSet: 5 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 14 Oct 2020 19:37:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: vendorcode/intel/fsp: Add Jasper Lake FSP headers for FSP v2376
by Karthik Ramasubramanian (Code Review) 14 Oct '20

14 Oct '20

Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45899 ) Change subject: vendorcode/intel/fsp: Add Jasper Lake FSP headers for FSP v2376 ...................................................................... Patch Set 6: (1 comment) https://review.coreboot.org/c/coreboot/+/45899/6//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/45899/6//COMMIT_MSG@14 PS6, Line 14: Can you please mention Cq-Depend: TBD so that we downstream accordingly. -- To view, visit https://review.coreboot.org/c/coreboot/+/45899 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I65c03d8eda11664541479983c7be11854410e1c6 Gerrit-Change-Number: 45899 Gerrit-PatchSet: 6 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 14 Oct 2020 19:23:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/jasperlake: Set the GpioOverride configuration
by Karthik Ramasubramanian (Code Review) 14 Oct '20

14 Oct '20

Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45901 ) Change subject: soc/intel/jasperlake: Set the GpioOverride configuration ...................................................................... Patch Set 8: (1 comment) https://review.coreboot.org/c/coreboot/+/45901/8//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/45901/8//COMMIT_MSG@15 PS8, Line 15: Cq-Depend: TBD -- To view, visit https://review.coreboot.org/c/coreboot/+/45901 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia4036cf0be3a6036d70920743958dc327a652077 Gerrit-Change-Number: 45901 Gerrit-PatchSet: 8 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 14 Oct 2020 19:23:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit October 2020