coreboot-gerrit October 2020

coreboot-gerrit@coreboot.org

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3474 discussions

Change in coreboot[master]: nb/intel/haswell: Account for DPR region in memory map
by Angel Pons (Code Review) 14 Oct '20

14 Oct '20

Hello build bot (Jenkins), Arthur Heymans, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/45712 to look at the new patch set (#12). Change subject: nb/intel/haswell: Account for DPR region in memory map ...................................................................... nb/intel/haswell: Account for DPR region in memory map While MRC.bin does not allocate any memory for DPR by default, it can be patched to do so. However, the current northbridge code does not account for DPR and will, among other things, place CBMEM inside it. Even though this may seem like a good thing, it renders TianoCore unable to boot and clashes with Intel TXT support (the reason to enable DPR to begin with). Update memmap.c so that CBMEM top does not fall within DPR. Also, report DPR as reserved, so that OSes know that the DPR memory is not to be used. Change-Id: I11f23fd43188f987e35fd61f52587e567496cd78 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/haswell/memmap.c M src/northbridge/intel/haswell/northbridge.c M src/northbridge/intel/haswell/registers/host_bridge.h 3 files changed, 62 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/45712/12 -- To view, visit https://review.coreboot.org/c/coreboot/+/45712 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I11f23fd43188f987e35fd61f52587e567496cd78 Gerrit-Change-Number: 45712 Gerrit-PatchSet: 12 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/cnl: Add ACPI support for PMC core OS driver
by Angel Pons (Code Review) 14 Oct '20

14 Oct '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45318 ) Change subject: soc/intel/cnl: Add ACPI support for PMC core OS driver ...................................................................... Patch Set 4: > Patch Set 4: > > FYI, this breaks booting Windows 10 on google/hatch (akemi variant) with a BSOD 'INTERNAL_POWER_FAILURE' Actually, `INTERNAL_POWER_ERROR` -- To view, visit https://review.coreboot.org/c/coreboot/+/45318 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibf7c8ba7449df15c2ca30d23791e17fc878204f2 Gerrit-Change-Number: 45318 Gerrit-PatchSet: 4 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Wed, 14 Oct 2020 17:40:49 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/poppy/variant/atlas: Reset bluetooth on boot
by Furquan Shaikh (Code Review) 14 Oct '20

14 Oct '20

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46120 ) Change subject: mb/google/poppy/variant/atlas: Reset bluetooth on boot ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/c/coreboot/+/46120/2/src/mainboard/google/poppy… File src/mainboard/google/poppy/variants/atlas/gpio.c: https://review.coreboot.org/c/coreboot/+/46120/2/src/mainboard/google/poppy… PS2, Line 335: early_gpio_table > I'm not familiar with atlas, but if the timing works out, you could add something to romstage or eve […] +1. You can assert it in romstage so that the regular GPIO table deasserts it. As Tim mentioned, you will have to check if there are any timing requirements about how long the signal needs to be asserted. -- To view, visit https://review.coreboot.org/c/coreboot/+/46120 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I361caa49e82aa086c3c35962164fb078fa30139e Gerrit-Change-Number: 46120 Gerrit-PatchSet: 2 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 14 Oct 2020 17:13:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Caveh Jalali <caveh(a)chromium.org> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/cnl: Add ACPI support for PMC core OS driver
by Matt DeVillier (Code Review) 14 Oct '20

14 Oct '20

Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45318 ) Change subject: soc/intel/cnl: Add ACPI support for PMC core OS driver ...................................................................... Patch Set 4: FYI, this breaks booting Windows 10 on google/hatch (akemi variant) with a BSOD 'INTERNAL_POWER_FAILURE' -- To view, visit https://review.coreboot.org/c/coreboot/+/45318 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibf7c8ba7449df15c2ca30d23791e17fc878204f2 Gerrit-Change-Number: 45318 Gerrit-PatchSet: 4 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Wed, 14 Oct 2020 17:06:25 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/poppy/variant/atlas: Reset bluetooth on boot
by Tim Wawrzynczak (Code Review) 14 Oct '20

14 Oct '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46120 ) Change subject: mb/google/poppy/variant/atlas: Reset bluetooth on boot ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/c/coreboot/+/46120/2/src/mainboard/google/poppy… File src/mainboard/google/poppy/variants/atlas/gpio.c: https://review.coreboot.org/c/coreboot/+/46120/2/src/mainboard/google/poppy… PS2, Line 335: early_gpio_table > that's unfortunate. so, we basically can't do this here for the installed […] I'm not familiar with atlas, but if the timing works out, you could add something to romstage or even just the regular gpio table. -- To view, visit https://review.coreboot.org/c/coreboot/+/46120 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I361caa49e82aa086c3c35962164fb078fa30139e Gerrit-Change-Number: 46120 Gerrit-PatchSet: 2 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 14 Oct 2020 16:58:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Caveh Jalali <caveh(a)chromium.org> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/volteer: Disable HybridStorageMode for Volteer EVT and Delbin
by Shaunak Saha (Code Review) 14 Oct '20

14 Oct '20

Shaunak Saha has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45643 ) Change subject: mb/google/volteer: Disable HybridStorageMode for Volteer EVT and Delbin ...................................................................... mb/google/volteer: Disable HybridStorageMode for Volteer EVT and Delbin HybridStorageMode FSP UPD needs to be set only for optane storage. Enabling HybridStorageMode causes some extra delay in FspSiliconInit due to HECI command and hence is avoided for NVMe and SATA scenerios. This change disables "HybridStorageMode" for volteer EVT and Delbin. BUG=b:158573805 TEST=Build and boot volteer evt and confirm that FspSiliconInit time is reduced. In Volteer this saves ~100ms. Signed-off-by: Shaunak Saha <shaunak.saha(a)intel.com> Change-Id: I54fc78e3f888d4f2a02ba0ad6b9aef33eb872a9c --- M src/mainboard/google/volteer/variants/delbin/overridetree.cb M src/mainboard/google/volteer/variants/volteer2/overridetree.cb 2 files changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/45643/1 diff --git a/src/mainboard/google/volteer/variants/delbin/overridetree.cb b/src/mainboard/google/volteer/variants/delbin/overridetree.cb index 05c8a34..7624d40 100644 --- a/src/mainboard/google/volteer/variants/delbin/overridetree.cb +++ b/src/mainboard/google/volteer/variants/delbin/overridetree.cb @@ -2,6 +2,8 @@ register "DdiPort1Hpd" = "0" register "DdiPort2Hpd" = "0" + register "HybridStorageMode" = "0" + device domain 0 on device pci 15.0 on chip drivers/i2c/generic diff --git a/src/mainboard/google/volteer/variants/volteer2/overridetree.cb b/src/mainboard/google/volteer/variants/volteer2/overridetree.cb index 0bb82f1..b6d5c8a 100644 --- a/src/mainboard/google/volteer/variants/volteer2/overridetree.cb +++ b/src/mainboard/google/volteer/variants/volteer2/overridetree.cb @@ -5,6 +5,8 @@ register "DdiPort1Hpd" = "0" register "DdiPort2Hpd" = "0" + register "HybridStorageMode" = "0" + device domain 0 on device pci 05.0 on end # IPU 0x9A19 device pci 15.0 on -- To view, visit https://review.coreboot.org/c/coreboot/+/45643 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I54fc78e3f888d4f2a02ba0ad6b9aef33eb872a9c Gerrit-Change-Number: 45643 Gerrit-PatchSet: 1 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: libpayload/x86: Try to discover invariant TSC rate
by Tim Wawrzynczak (Code Review) 14 Oct '20

14 Oct '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34170 ) Change subject: libpayload/x86: Try to discover invariant TSC rate ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/c/coreboot/+/34170/4/payloads/libpayload/arch/x… File payloads/libpayload/arch/x86/timer.c: https://review.coreboot.org/c/coreboot/+/34170/4/payloads/libpayload/arch/x… PS4, Line 90: ecx > `nominal` is a 64-bit variable, though yeah I guess it wouldn't work b/c of the macro. -- To view, visit https://review.coreboot.org/c/coreboot/+/34170 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic6607ee2a8b41c2be9dc1bb4f1e23e652bb33889 Gerrit-Change-Number: 34170 Gerrit-PatchSet: 4 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 14 Oct 2020 15:37:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: lib: add 64-bit versions of clz, __ffs and log2
by Tim Wawrzynczak (Code Review) 14 Oct '20

14 Oct '20

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45938 ) Change subject: lib: add 64-bit versions of clz, __ffs and log2 ...................................................................... lib: add 64-bit versions of clz, __ffs and log2 Tack on `_64` to the end of the 32-bit name. Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: Iefc6e6c51f5b20607c88e38660a499a4f77ce0d0 --- M src/include/lib.h 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/45938/1 diff --git a/src/include/lib.h b/src/include/lib.h index 46d8b02..4342b9e 100644 --- a/src/include/lib.h +++ b/src/include/lib.h @@ -56,4 +56,8 @@ /* Integer binary logarithm (rounding up): log2_ceil(0) == -1, log2(5) == 3 */ static inline int log2_ceil(u32 x) { return (x == 0) ? -1 : log2(x * 2 - 1); } +static inline long long clz_64(u64 x) { return x ? __builtin_clz(x) : sizeof(x) * 8; } +static inline int log2_64(u64 x) { return sizeof(x) * 8 - clz_64(x) - 1; } +static inline int __ffs_64(u64 x) { return log2_64(x & (u64)(-(s64)x)); } + #endif /* __LIB_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/45938 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iefc6e6c51f5b20607c88e38660a499a4f77ce0d0 Gerrit-Change-Number: 45938 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/intel/adlrvp: Add ADL-P mainboard ASL code
by Subrata Banik (Code Review) 14 Oct '20

14 Oct '20

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46267 ) Change subject: mb/intel/adlrvp: Add ADL-P mainboard ASL code ...................................................................... mb/intel/adlrvp: Add ADL-P mainboard ASL code List of changes: 1. Add required files for dsdt.asl 2. Include 'acpi' directory for mainboard related ASL code TEST=Dump dsdt.aml and verified all ACPI device present there Change-Id: I70829e2bdb12fad20627d9aea47e745d9095f07a Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- A src/mainboard/intel/adlrvp/acpi/mainboard.asl A src/mainboard/intel/adlrvp/acpi/mipi_camera.asl M src/mainboard/intel/adlrvp/dsdt.asl 3 files changed, 589 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/46267/1 diff --git a/src/mainboard/intel/adlrvp/acpi/mainboard.asl b/src/mainboard/intel/adlrvp/acpi/mainboard.asl new file mode 100644 index 0000000..6647ac1 --- /dev/null +++ b/src/mainboard/intel/adlrvp/acpi/mainboard.asl @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#if CONFIG(EC_GOOGLE_CHROMEEC) +Scope (\_SB) +{ + Device (PWRB) + { + Name (_HID, EisaId ("PNP0C0C")) + } +} +#endif diff --git a/src/mainboard/intel/adlrvp/acpi/mipi_camera.asl b/src/mainboard/intel/adlrvp/acpi/mipi_camera.asl new file mode 100644 index 0000000..c830ea1 --- /dev/null +++ b/src/mainboard/intel/adlrvp/acpi/mipi_camera.asl @@ -0,0 +1,523 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2020 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope (\_SB.PCI0.IPU0) +{ + Name (_DSD, Package (0x02) + { + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x02) + { + Package (0x02) + { + "port0", + "PRT0" + }, + + Package (0x02) + { + "port1", + "PRT1" + } + } + }) + + Name (PRT0, Package (0x04) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x01) + { + Package (0x02) + { + "port", + One + } + }, + + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "endpoint0", + "EP00" + } + } + }) + + Name (PRT1, Package (0x04) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x01) + { + Package (0x02) + { + "port", + 2 + } + }, + + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "endpoint0", + "EP10" + } + } + }) +} + +Scope (_SB.PCI0.IPU0) +{ + Name (EP00, Package (0x02) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x04) + { + Package (0x02) + { + "endpoint", + Zero + }, + + Package (0x02) + { + "clock-lanes", + Zero + }, + + Package (0x02) + { + "data-lanes", + Package (0x04) + { + One, + 0x02, + 0x03, + 0x04 + } + }, + + Package (0x02) + { + "remote-endpoint", + Package (0x03) + { + ^I2C3.CAM0, + Zero, + Zero + } + } + } + }) + Name (EP10, Package (0x02) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x04) + { + Package (0x02) + { + "endpoint", + Zero + }, + + Package (0x02) + { + "clock-lanes", + Zero + }, + + Package (0x02) + { + "data-lanes", + Package (0x04) + { + One, + 0x02, + 0x03, + 0x04 + } + }, + + Package (0x02) + { + "remote-endpoint", + Package (0x03) + { + ^I2C5.CAM1, + Zero, + Zero + } + } + } + }) +} + +Scope (\_SB.PCI0.I2C3) +{ + PowerResource (RCPR, 0x00, 0x0000) + { + Name (STA, Zero) + Method (_ON, 0, Serialized) + { + If ((STA == Zero)) + { + /* Enable CLK0 with 19.2MHz */ + MCCT(0,1,1) + /* Pull PWREN(GPIO B23) high */ + STXS(GPP_B23) + Sleep(5) + /* Pull RST(GPIO C15) low */ + CTXS(GPP_C15) + Sleep(5) + /* Pull RST high */ + STXS(GPP_C15) + Sleep(5) + Store(1,STA) + } + } + + Method (_OFF, 0, Serialized) + { + If ((STA == One)) + { + /* Pull RST low */ + CTXS(GPP_C15) + /* Pull PWREN low */ + CTXS(GPP_B23) + /* Disable CLK0 */ + MCCT(0,0,1) + Store(0,STA) + } + } + + Method (_STA, 0, NotSerialized) + { + Return (STA) + } + } + + Device (CAM0) + { + Name (_HID, "OVTI8856") + Name (_UID, Zero) + Name (_DDN, "Ov 8856 Camera") + Method (_STA, 0, NotSerialized) + { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () + { + I2cSerialBus (0x0010, ControllerInitiated, 0x00061A80, + AddressingMode7Bit, "\\_SB.PCI0.I2C3", + 0x00, ResourceConsumer, , + ) + }) + + Name (_PR0, Package (0x01) + { + RCPR + }) + + Name (_PR3, Package (0x01) + { + RCPR + }) + + Name (_DSD, Package (0x04) + { + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "port0", + "PRT0" + } + }, + + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x02) + { + Package (0x02) + { + "clock-frequency", + 0x0124F800 + }, + Package (0x02) + { + "lens-focus", + Package (0x01) + { + VCM0 + } + } + } + }) + + Name (PRT0, Package (0x04) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x01) + { + Package (0x02) + { + "port", + Zero + } + }, + + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "endpoint0", + "EP00" + } + } + }) + + Name (EP00, Package (0x02) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x03) + { + Package (0x02) + { + "endpoint", + Zero + }, + + Package (0x02) + { + "link-frequencies", + Package (0x01) + { + 0x325AA000 + } + }, + Package (0x02) + { + "remote-endpoint", + Package (0x03) + { + IPU0, + Zero, + Zero + } + } + } + }) + } + + Device (VCM0) + { + Name (_HID, "PRP0001") + Name (_UID, 0x03) + Name (_DDN, "DW9714 VCM") + Method (_STA, 0, NotSerialized) + { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () + { + I2cSerialBus (0x000C, ControllerInitiated, 0x00061A80, + AddressingMode7Bit, "\\_SB.PCI0.I2C3", + 0x00, ResourceConsumer, , + ) + }) + Name (_DEP, Package (0x01) + { + CAM0 + }) + Name (_PR0, Package (0x01) + { + RCPR + }) + Name (_PR3, Package (0x01) + { + RCPR + }) + Name (_DSD, Package (0x02) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x01) + { + Package (0x02) + { + "compatible", + "dongwoon,dw9714" + } + } + }) + } +} + +Scope (\_SB.PCI0.I2C5) +{ + PowerResource (FCPR, 0x00, 0x0000) + { + Name (STA, Zero) + Method (_ON, 0, Serialized) + { + If ((STA == Zero)) + { + /* Enable CLK1 with 19.2MHz */ + MCCT(1,1,1) + /* Pull PWREN(GPIO R6) high */ + STXS(GPP_R6) + Sleep(5) + /* Pull RST(GPIO H12) low */ + CTXS(GPP_H12) + Sleep(5) + /* Pull RST high */ + STXS(GPP_H12) + Sleep(5) + Store(1,STA) + } + } + + Method (_OFF, 0, Serialized) + { + If ((STA == One)) + { + /* Pull RST low */ + CTXS(GPP_H12) + /* Pull PWREN low */ + CTXS(GPP_R6) + /* Disable CLK1 */ + MCCT(1,0,1) + Store(0,STA) + } + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (STA) + } + } + + Device (CAM1) + { + Name (_HID, "OVTI8856") + Name (_UID, Zero) + Name (_DDN, "Ov 8856 Camera") + Method (_STA, 0, NotSerialized) + { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () + { + I2cSerialBus (0x0010, ControllerInitiated, 0x00061A80, + AddressingMode7Bit, "\\_SB.PCI0.I2C5", + 0x00, ResourceConsumer, , + ) + }) + + Name (_PR0, Package (0x01) + { + FCPR + }) + + Name (_PR3, Package (0x01) + { + FCPR + }) + + Name (_DSD, Package (0x04) + { + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "port0", + "PRT0" + } + }, + + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x01) + { + Package (0x02) + { + "clock-frequency", + 0x0124F800 + } + } + }) + + Name (PRT0, Package (0x04) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x01) + { + Package (0x02) + { + "port", + Zero + } + }, + + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "endpoint0", + "EP00" + } + } + }) + + Name (EP00, Package (0x02) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x03) + { + Package (0x02) + { + "endpoint", + Zero + }, + + Package (0x02) + { + "link-frequencies", + Package (0x01) + { + 0x325AA000 + } + }, + Package (0x02) + { + "remote-endpoint", + Package (0x03) + { + IPU0, + One, + Zero + } + } + } + }) + } +} diff --git a/src/mainboard/intel/adlrvp/dsdt.asl b/src/mainboard/intel/adlrvp/dsdt.asl index fca3242..93dfc2c 100644 --- a/src/mainboard/intel/adlrvp/dsdt.asl +++ b/src/mainboard/intel/adlrvp/dsdt.asl @@ -1,6 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi.h> +#include <baseboard/ec.h> +#include <baseboard/gpio.h> DefinitionBlock( "dsdt.aml", @@ -11,5 +13,45 @@ 0x20110725 /* OEM revision */ ) { + #include <soc/intel/common/block/acpi/acpi/platform.asl> + /* global NVS and variables */ + #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> + + /* CPU */ + #include <cpu/intel/common/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <soc/intel/common/block/acpi/acpi/northbridge.asl> + #include <soc/intel/alderlake/acpi/southbridge.asl> + #include <soc/intel/alderlake/acpi/tcss.asl> + #include <soc/intel/common/block/acpi/acpi/ipu.asl> + } + } + +#if CONFIG(CHROMEOS) + /* Chrome OS specific */ + #include <vendorcode/google/chromeos/acpi/chromeos.asl> +#endif + +#if CONFIG(EC_GOOGLE_CHROMEEC) + /* Chrome OS Embedded Controller */ + Scope (\_SB.PCI0.LPCB) + { + /* ACPI code for EC SuperIO functions */ + #include <ec/google/chromeec/acpi/superio.asl> + /* ACPI code for EC functions */ + #include <ec/google/chromeec/acpi/ec.asl> + } +#endif + + #include <southbridge/intel/common/acpi/sleepstates.asl> + + /* Mainboard specific */ + #include "acpi/mainboard.asl" + + /* Camera */ + #include "acpi/mipi_camera.asl" } -- To view, visit https://review.coreboot.org/c/coreboot/+/46267 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I70829e2bdb12fad20627d9aea47e745d9095f07a Gerrit-Change-Number: 46267 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

5 14

Change in coreboot[master]: mb/intel/adlrvp: Add ADL-P ramstage mainboard code
by Subrata Banik (Code Review) 14 Oct '20

14 Oct '20

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46265 ) Change subject: mb/intel/adlrvp: Add ADL-P ramstage mainboard code ...................................................................... mb/intel/adlrvp: Add ADL-P ramstage mainboard code List of changes: 1. Add devicetree.cb config parameters related to FSP-S UPD 2. Configure GPIO as per ADL-P RVP 3. Add files required for Ramstage (ec.c, mainboard.c) 4. Add smihandler.c for SMM TEST=Able to reach till payload Change-Id: I120885956c88babfa09d24ce1079d49306919b8a Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/mainboard/intel/adlrvp/Makefile.inc A src/mainboard/intel/adlrvp/ec.c A src/mainboard/intel/adlrvp/mainboard.c A src/mainboard/intel/adlrvp/smihandler.c M src/mainboard/intel/adlrvp/variants/adlrvp_p/Makefile.inc M src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb A src/mainboard/intel/adlrvp/variants/adlrvp_p/gpio.c A src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/ec.h M src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/variants.h 9 files changed, 581 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/46265/1 diff --git a/src/mainboard/intel/adlrvp/Makefile.inc b/src/mainboard/intel/adlrvp/Makefile.inc index e8a0eca..2ca32f3 100644 --- a/src/mainboard/intel/adlrvp/Makefile.inc +++ b/src/mainboard/intel/adlrvp/Makefile.inc @@ -11,7 +11,12 @@ romstage-y += romstage_fsp_params.c romstage-y += board_id.c +smm-y += smihandler.c + ramstage-$(CONFIG_CHROMEOS) += chromeos.c +ramstage-y += ec.c +ramstage-y += mainboard.c +ramstage-y += board_id.c subdirs-y += variants/baseboard CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include diff --git a/src/mainboard/intel/adlrvp/ec.c b/src/mainboard/intel/adlrvp/ec.c new file mode 100644 index 0000000..14760017 --- /dev/null +++ b/src/mainboard/intel/adlrvp/ec.c @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +#include <ec/ec.h> +#include <ec/google/chromeec/ec.h> +#include <baseboard/ec.h> + +void mainboard_ec_init(void) +{ + const struct google_chromeec_event_info info = { + .log_events = MAINBOARD_EC_LOG_EVENTS, + .sci_events = MAINBOARD_EC_SCI_EVENTS, + .s3_wake_events = MAINBOARD_EC_S3_WAKE_EVENTS, + .s5_wake_events = MAINBOARD_EC_S5_WAKE_EVENTS, + .s0ix_wake_events = MAINBOARD_EC_S0IX_WAKE_EVENTS, + }; + + google_chromeec_events_init(&info, acpi_is_wakeup_s3()); +} diff --git a/src/mainboard/intel/adlrvp/mainboard.c b/src/mainboard/intel/adlrvp/mainboard.c new file mode 100644 index 0000000..d9458cd --- /dev/null +++ b/src/mainboard/intel/adlrvp/mainboard.c @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <device/device.h> +#include <ec/ec.h> +#include <soc/gpio.h> +#include <vendorcode/google/chromeos/chromeos.h> +#include <smbios.h> +#include <string.h> + +const char *smbios_system_sku(void) +{ + static char sku_str[7] = ""; /* sku{0..255} */ + uint32_t sku_id = 255; + + snprintf(sku_str, sizeof(sku_str), "sku%u", sku_id); + return sku_str; +} + +static void mainboard_init(void *chip_info) +{ + variant_configure_gpio_pads(); + + if (CONFIG(EC_GOOGLE_CHROMEEC)) + mainboard_ec_init(); +} + +static void mainboard_enable(struct device *dev) +{ + dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; +} + +struct chip_operations mainboard_ops = { + .init = mainboard_init, + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/intel/adlrvp/smihandler.c b/src/mainboard/intel/adlrvp/smihandler.c new file mode 100644 index 0000000..a3b4323 --- /dev/null +++ b/src/mainboard/intel/adlrvp/smihandler.c @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <cpu/x86/smm.h> +#include <ec/google/chromeec/smm.h> +#include <intelblocks/smihandler.h> +#include <baseboard/ec.h> + +void mainboard_smi_espi_handler(void) +{ + if (!CONFIG(EC_GOOGLE_CHROMEEC)) + return; + + chromeec_smi_process_events(); +} + +void mainboard_smi_sleep(u8 slp_typ) +{ + if (!CONFIG(EC_GOOGLE_CHROMEEC)) + return; + + chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS, MAINBOARD_EC_S5_WAKE_EVENTS); +} + +int mainboard_smi_apmc(u8 apmc) +{ + if (CONFIG(EC_GOOGLE_CHROMEEC)) + chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS, MAINBOARD_EC_SMI_EVENTS); + + return 0; +} diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p/Makefile.inc b/src/mainboard/intel/adlrvp/variants/adlrvp_p/Makefile.inc index 8c05721..513963e 100644 --- a/src/mainboard/intel/adlrvp/variants/adlrvp_p/Makefile.inc +++ b/src/mainboard/intel/adlrvp/variants/adlrvp_p/Makefile.inc @@ -3,3 +3,5 @@ bootblock-y += early_gpio.c romstage-y += memory.c + +ramstage-y += gpio.c diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb b/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb index a6b0039..3484713 100644 --- a/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb +++ b/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb @@ -4,6 +4,34 @@ device lapic 0 on end end + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "pmc_gpe0_dw0" = "GPP_B" + register "pmc_gpe0_dw1" = "GPP_D" + register "pmc_gpe0_dw2" = "GPP_E" + + # FSP configuration + # Enable Speed Shift Technology/HWP support + register "speed_shift_enable" = "1" + + register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" # Type C port - various configurations – TCP0 + register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" # Type C port - various configurations – TCP1 + register "usb2_ports[2]" = "USB2_PORT_MID(OC3)" # Type C port - various configurations – TCP2 + register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # WWAN M.2 Module / USB2.0 Type-A Port-1 + register "usb2_ports[4]" = "USB2_PORT_MID(OC3)" # Type C port - various configurations – TCP3 + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # FPS connector/USB2.0 Type-A Port-1 + register "usb2_ports[6]" = "USB2_PORT_MID(OC0)" # USB3.2 Gen2x1 Type-A Port - TAP2 + register "usb2_ports[7]" = "USB2_PORT_MID(OC0)" # USB3.2 Gen2x1 Type-A Vertical Port – TAP3 + register "usb2_ports[8]" = "USB2_PORT_MID(OC3)" # USB3.2 Gen2x1 Type-A Port - TAP1 + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # WLAN M.2 Module/BT + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC3)" # USB3.2 Gen2x1 Type-A Port - TAP1 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # USB3.2 Gen2x1 Type-A Port - TAP2 + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)" # USB3.2 Gen2x1 Type-A Vertical Port - TAP3 + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # WWAN M.2 Module + # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f register "gen1_dec" = "0x00fc0801" register "gen2_dec" = "0x000c0201" @@ -41,6 +69,94 @@ # Mark LAN CLK pins as unused as GbE 0:0x1f.6 is disabled below register "PcieClkSrcUsage[6]" = "0xff" + register "SataSalpSupport" = "1" + + register "SataPortsEnable[0]" = "1" + register "SataPortsEnable[1]" = "1" + register "SataPortsEnable[2]" = "1" + register "SataPortsEnable[3]" = "1" + + register "SataPortsDevSlp[0]" = "1" + register "SataPortsDevSlp[1]" = "1" + register "SataPortsDevSlp[2]" = "1" + register "SataPortsDevSlp[3]" = "1" + + # Enable EDP in PortA + register "DdiPortAConfig" = "1" + register "DdiPortBConfig" = "1" + + # TCSS USB3 + register "TcssAuxOri" = "0" + + register "s0ix_enable" = "1" + + register "SerialIoI2cMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoDisabled, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + }" + + register "SerialIoGSpiMode" = "{ + [PchSerialIoIndexGSPI0] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI1] = PchSerialIoPci, + [PchSerialIoIndexGSPI2] = PchSerialIoDisabled, + }" + + register "SerialIoGSpiCsMode" = "{ + [PchSerialIoIndexGSPI0] = 0, + [PchSerialIoIndexGSPI1] = 0, + [PchSerialIoIndexGSPI2] = 0, + }" + + register "SerialIoGSpiCsState" = "{ + [PchSerialIoIndexGSPI0] = 0, + [PchSerialIoIndexGSPI1] = 0, + [PchSerialIoIndexGSPI2] = 0, + }" + + register "SerialIoUartMode" = "{ + [PchSerialIoIndexUART0] = PchSerialIoDisabled, + [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoSkipInit, + }" + + # HD Audio + register "PchHdaDspEnable" = "1" + register "PchHdaAudioLinkHdaEnable" = "0" + register "PchHdaAudioLinkDmicEnable[0]" = "1" + register "PchHdaAudioLinkDmicEnable[1]" = "1" + register "PchHdaAudioLinkSndwEnable[0]" = "1" + register "PchHdaAudioLinkSndwEnable[1]" = "1" + # iDisp-Link T-Mode 0: 2T, 2: 4T, 3: 8T, 4: 16T + register "PchHdaIDispLinkTmode" = "2" + # iDisp-Link Freq 4: 96MHz, 3: 48MHz. + register "PchHdaIDispLinkFrequency" = "4" + # Not disconnected/enumerable + register "PchHdaIDispCodecDisconnect" = "0" + + # Intel Common SoC Config + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + }, + }" + device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Graphics diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p/gpio.c b/src/mainboard/intel/adlrvp/variants/adlrvp_p/gpio.c new file mode 100644 index 0000000..f06e70e --- /dev/null +++ b/src/mainboard/intel/adlrvp/variants/adlrvp_p/gpio.c @@ -0,0 +1,297 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <commonlib/helpers.h> + +/* Pad configuration in ramstage*/ +static const struct pad_config gpio_table[] = { + /* SSD1_PWREN CPU SSD1 */ + PAD_CFG_GPO(GPP_D14, 1, PLTRST), + /* SSD1_RESET CPU SSD1 */ + PAD_CFG_GPO(GPP_F20, 1, PLTRST), + /* BT_RF_KILL_N */ + PAD_CFG_GPO(GPP_A13, 1, PLTRST), + /* WLAN RST# */ + PAD_CFG_GPO(GPP_H2, 1, PLTRST), + /* WIFI_WAKE_N */ + PAD_CFG_GPI_IRQ_WAKE(GPP_D13, NONE, DEEP, LEVEL, INVERT), + /* x4 PCIE slot1 PWREN */ + PAD_CFG_GPO(GPP_H17, 0, PLTRST), + /* x4 PCIE slot 1 RESET */ + PAD_CFG_GPO(GPP_F10, 1, PLTRST), + /* Retimer Force Power */ + PAD_CFG_GPO(GPP_E4, 0, PLTRST), + /* PEG Slot RST# */ + PAD_CFG_GPO(GPP_B2, 1, PLTRST), + /* M.2 SSD_2 Reset */ + PAD_CFG_GPO(GPP_H0, 1, PLTRST), + /* CAM1-IRQ */ + PAD_CFG_GPO(GPP_B23, 1, PLTRST), + /* CAM_STROBE */ + PAD_CFG_GPO(GPP_B18, 0, PLTRST), + /* Audio Codec INT N */ + PAD_CFG_GPI_APIC(GPP_H3, NONE, PLTRST, LEVEL, INVERT), + /* TCH PAD Power EN */ + PAD_CFG_GPO(GPP_F7, 1, PLTRST), + /* THC1 SPI2 RST# */ + PAD_CFG_GPO(GPP_F17, 1, PLTRST), + /* THC1_SPI2_INTB */ + PAD_CFG_GPI_APIC(GPP_F18, NONE, PLTRST, EDGE_SINGLE, INVERT), + /* THC1_SPI2_INTB */ + PAD_CFG_GPI(GPP_E17, NONE, PLTRST), + /* EC_SMI_N */ + PAD_CFG_GPI_SMI_LOW(GPP_E7, NONE, PLTRST, LEVEL), + /* EC_SLP_S0_CS_N */ + PAD_CFG_GPO(GPP_F9, 1, PLTRST), + /* WIFI RF KILL */ + PAD_CFG_GPO(GPP_E3, 1, PLTRST), + /* DISP_AUX_N_BIAS_GPIO */ + PAD_CFG_GPO(GPP_E23, 1, PLTRST), + /* WWAN WAKE N*/ + PAD_CFG_GPI_IRQ_WAKE(GPP_D18, NONE, DEEP, LEVEL, INVERT), + /* WWAN_DISABLE_N */ + PAD_CFG_GPO(GPP_D15, 1, PLTRST), + /* WWAN_RST# */ + PAD_CFG_GPO(GPP_E10, 1, PLTRST), + /* WWAN_PWR_EN */ + PAD_CFG_GPO(GPP_E13, 1, DEEP), + /* WWAN_PERST# */ + PAD_CFG_GPO(GPP_C5, 1, PLTRST), + /* PEG_SLOT_WAKE_N */ + PAD_CFG_GPI(GPP_A20, NONE, PLTRST), + /* UART_BT_WAKE_N */ + PAD_CFG_GPI_IRQ_WAKE(GPP_E0, NONE, DEEP, LEVEL, INVERT), + /* CAM CONN1 CLKEN */ + PAD_CFG_GPO(GPP_H15, 1, PLTRST), + /* CPU SSD2 PWREN */ + PAD_CFG_GPO(GPP_C2, 1, PLTRST), + /* CPU SSD2 RST# */ + PAD_CFG_GPO(GPP_H1, 1, PLTRST), + /* Sata direct Power */ + PAD_CFG_GPO(GPP_B4, 1, PLTRST), + + /* THC0 SPI1 CLK */ + PAD_CFG_NF(GPP_E11, NONE, DEEP, NF2), + /* THC0 SPI1 IO 1 */ + PAD_CFG_NF(GPP_E12, NONE, DEEP, NF2), + /* THC0 SPI1 IO 2 */ + PAD_CFG_NF(GPP_E1, NONE, DEEP, NF2), + /* THC0 SPI IO 3 */ + PAD_CFG_NF(GPP_E2, NONE, DEEP, NF2), + /* THC1 SPI1 RSTB */ + PAD_CFG_NF(GPP_E6, NONE, DEEP, NF2), + /* UART_RX(1) */ + PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), + /* UART_RX(2) */ + PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), + /* UART_RX(4) */ + PAD_CFG_NF(GPP_T4, NONE, DEEP, NF1), + /* UART_RX(5) */ + PAD_CFG_NF(GPP_T8, NONE, DEEP, NF1), + /* UART_RX(6) */ + PAD_CFG_NF(GPP_T12, NONE, DEEP, NF1), + + /* UART_TX(1) */ + PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), + /* UART_TX(2) */ + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), + /* UART_TX(4) */ + PAD_CFG_NF(GPP_T5, NONE, DEEP, NF1), + /* UART_TX(5) */ + PAD_CFG_NF(GPP_T9, NONE, DEEP, NF1), + /* UART_TX(6) */ + PAD_CFG_NF(GPP_T13, NONE, DEEP, NF1), + + /* UART_RTS(1) */ + PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1), + /* UART_RTS(2) */ + PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1), + /* UART_RTS(4) */ + PAD_CFG_NF(GPP_T6, NONE, DEEP, NF1), + /* UART_RTS(5) */ + PAD_CFG_NF(GPP_T10, NONE, DEEP, NF1), + /* UART_RTS(6) */ + PAD_CFG_NF(GPP_T14, NONE, DEEP, NF1), + + /* UART_CTS(1) */ + PAD_CFG_NF(GPP_C15, NONE, DEEP, NF1), + /* UART_CTS(2) */ + PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1), + /* UART_CTS(4) */ + PAD_CFG_NF(GPP_T7, NONE, DEEP, NF1), + /* UART_CTS(5) */ + PAD_CFG_NF(GPP_T11, NONE, DEEP, NF1), + /* UART_CTS(6) */ + PAD_CFG_NF(GPP_T15, NONE, DEEP, NF1), + + /* SPI_MOSI(1) */ + PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1), + /* SPI_MOSI(2) */ + PAD_CFG_NF(GPP_D12, NONE, DEEP, NF2), + + /* SPI_MIS0(0) */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), + /* SPI_MIS0(1) */ + PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1), + /* SPI_MIS0(2) */ + PAD_CFG_NF(GPP_D11, NONE, DEEP, NF2), + + /* SPI_CLK(0) */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), + /* SPI_CLK(1) */ + PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1), + /* SPI_CLK(2) */ + PAD_CFG_NF(GPP_D10, NONE, DEEP, NF2), + + /* SPI_CS(0, 0) */ + PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), + /* SPI_CS(0, 1) */ + PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), + /* SPI_CS(1, 0) */ + PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1), + /* SPI_CS(2, 0) */ + PAD_CFG_NF(GPP_D9, NONE, DEEP, NF2), + + /* I2C_SCL(0) */ + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), + /* I2C_SCL(1) */ + PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), + /* I2C_SCL(2) */ + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), + /* I2C_SCL(3) */ + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), + /* I2C_SCL(5) */ + PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), + /* I2C_SCL(6) */ + PAD_CFG_NF(GPP_T1, NONE, DEEP, NF1), + /* I2C_SCL(7) */ + PAD_CFG_NF(GPP_T3, NONE, DEEP, NF1), + + /* I2C_SDA(0) */ + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), + /* I2C_SDA(1) */ + PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), + /* I2C_SDA(2) */ + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), + /* I2C_SDA(3) */ + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), + /* I2C_SDA(5) */ + PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), + /* I2C_SDA(6) */ + PAD_CFG_NF(GPP_T0, NONE, DEEP, NF1), + /* I2C_SDA(7) */ + PAD_CFG_NF(GPP_T2, NONE, DEEP, NF1), + + /* I2S0_SCLK */ + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), + /* I2S0_SFRM */ + PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), + /* I2S0_TXD */ + PAD_CFG_NF(GPP_R2, NONE, DEEP, NF2), + /* I2S0_RXD */ + PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), + + /* I2S1_SCLK */ + PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1), + /* I2S1_SFRM */ + PAD_CFG_NF(GPP_R5, NONE, DEEP, NF2), + /* I2S1_TXD */ + PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2), + /* I2S1_RXD */ + PAD_CFG_NF(GPP_R7, NONE, DEEP, NF2), + + /* I2S2_SCLK */ + PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), + /* I2S2_SFRM */ + PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), + /* I2S2_TXD */ + PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), + /* I2S2_RXD */ + PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), + + /* I2S_MCLK1_OUT */ + PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), + /* I2S_MCLK2_INOUT */ + PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), + + /* SNDW1_CLK */ + PAD_CFG_NF(GPP_S0, NONE, DEEP, NF1), + /* SNDW1_DATA */ + PAD_CFG_NF(GPP_S1, NONE, DEEP, NF1), + /* SNDW2_CLK */ + PAD_CFG_NF(GPP_S2, NONE, DEEP, NF1), + /* SNDW2_DATA */ + PAD_CFG_NF(GPP_S3, NONE, DEEP, NF1), + /* SNDW3_CLK */ + PAD_CFG_NF(GPP_S4, NONE, DEEP, NF1), + /* SNDW3_DATA */ + PAD_CFG_NF(GPP_S5, NONE, DEEP, NF1), + /* SNDW4_CLK */ + PAD_CFG_NF(GPP_S6, NONE, DEEP, NF1), + /* SNDW4_DATA */ + PAD_CFG_NF(GPP_S7, NONE, DEEP, NF1), + + /* SMB_CLK */ + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), + /* SMB_DATA */ + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), + + /* SATADevSlpPin to GPIO pin mapping */ + PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), + /* SATA DIRECT DEVSLP*/ + PAD_CFG_NF(GPP_H12, NONE, DEEP, NF5), + + /* SATA LED pin */ + PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), + + /* USB2 OC0 pins */ + PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), + /* USB2 OC1 pins */ + PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), + /* USB2 OC2 pins */ + PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), + /* USB2 OC3 pins */ + PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), + + /* GPIO pin for PCIE SRCCLKREQB */ + PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), + + /* DDP1/2/3/4/A/B/C CTRLCLK and CTRLDATA pins */ + PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E22, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A21, NONE, DEEP, NF2), + PAD_CFG_NF(GPP_A22, NONE, DEEP, NF2), + + /* IMGCLKOUT */ + PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H23, NONE, DEEP, NF1), +}; + +void variant_configure_gpio_pads(void) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), +}; + +const struct cros_gpio *variant_cros_gpios(size_t *num) +{ + *num = ARRAY_SIZE(cros_gpios); + return cros_gpios; +} diff --git a/src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/ec.h b/src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/ec.h new file mode 100644 index 0000000..4303faf --- /dev/null +++ b/src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/ec.h @@ -0,0 +1,73 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __BASEBOARD_EC_H__ +#define __BASEBOARD_EC_H__ + +#include <ec/ec.h> +#include <ec/google/chromeec/ec_commands.h> +#include <baseboard/gpio.h> + +#define MAINBOARD_EC_SCI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_MUX)) + +#define MAINBOARD_EC_SMI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)) + +/* EC can wake from S5 with lid or power button */ +#define MAINBOARD_EC_S5_WAKE_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) + +/* + * EC can wake from S3 with lid or power button or key press or + * mode change event. + */ +#define MAINBOARD_EC_S3_WAKE_EVENTS \ + (MAINBOARD_EC_S5_WAKE_EVENTS |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)) + +#define MAINBOARD_EC_S0IX_WAKE_EVENTS (MAINBOARD_EC_S3_WAKE_EVENTS) + +/* Log EC wake events plus EC shutdown events */ +#define MAINBOARD_EC_LOG_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC)) + +/* + * ACPI related definitions for ASL code. + */ + +/* Enable EC backed ALS device in ACPI */ +#define EC_ENABLE_ALS_DEVICE + +/* Enable EC sync interrupt, EC_SYNC_IRQ is defined in baseboard/gpio.h */ +#define EC_ENABLE_SYNC_IRQ + +/* Enable EC backed PD MCU device in ACPI */ +#define EC_ENABLE_PD_MCU_DEVICE + +/* Enable LID switch and provide wake pin for EC */ +#define EC_ENABLE_LID_SWITCH +#define EC_ENABLE_WAKE_PIN GPE_EC_WAKE + +#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */ +#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */ +#define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */ + +#endif /* __BASEBOARD_EC_H__ */ diff --git a/src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/variants.h index 5288b6f..005ec83 100644 --- a/src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/variants.h @@ -20,7 +20,8 @@ /* The next set of functions return the gpio table and fill in the number of * entries for each table. */ const struct cros_gpio *variant_cros_gpios(size_t *num); - +/* Functions to configure GPIO as per variant schematics */ +void variant_configure_gpio_pads(void); void variant_configure_early_gpio_pads(void); size_t variant_memory_sku(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/46265 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I120885956c88babfa09d24ce1079d49306919b8a Gerrit-Change-Number: 46265 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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coreboot-gerrit October 2020