Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46265 )
Change subject: mb/intel/adlrvp: Add ADL-P ramstage mainboard code ......................................................................
mb/intel/adlrvp: Add ADL-P ramstage mainboard code
List of changes: 1. Add devicetree.cb config parameters related to FSP-S UPD 2. Configure GPIO as per ADL-P RVP 3. Add files required for Ramstage (ec.c, mainboard.c) 4. Add smihandler.c for SMM
TEST=Able to reach till payload
Change-Id: I120885956c88babfa09d24ce1079d49306919b8a Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/mainboard/intel/adlrvp/Makefile.inc A src/mainboard/intel/adlrvp/ec.c A src/mainboard/intel/adlrvp/mainboard.c A src/mainboard/intel/adlrvp/smihandler.c M src/mainboard/intel/adlrvp/variants/adlrvp_p/Makefile.inc M src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb A src/mainboard/intel/adlrvp/variants/adlrvp_p/gpio.c A src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/ec.h M src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/variants.h 9 files changed, 581 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/46265/1
diff --git a/src/mainboard/intel/adlrvp/Makefile.inc b/src/mainboard/intel/adlrvp/Makefile.inc index e8a0eca..2ca32f3 100644 --- a/src/mainboard/intel/adlrvp/Makefile.inc +++ b/src/mainboard/intel/adlrvp/Makefile.inc @@ -11,7 +11,12 @@ romstage-y += romstage_fsp_params.c romstage-y += board_id.c
+smm-y += smihandler.c + ramstage-$(CONFIG_CHROMEOS) += chromeos.c +ramstage-y += ec.c +ramstage-y += mainboard.c +ramstage-y += board_id.c
subdirs-y += variants/baseboard CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include diff --git a/src/mainboard/intel/adlrvp/ec.c b/src/mainboard/intel/adlrvp/ec.c new file mode 100644 index 0000000..14760017 --- /dev/null +++ b/src/mainboard/intel/adlrvp/ec.c @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +#include <ec/ec.h> +#include <ec/google/chromeec/ec.h> +#include <baseboard/ec.h> + +void mainboard_ec_init(void) +{ + const struct google_chromeec_event_info info = { + .log_events = MAINBOARD_EC_LOG_EVENTS, + .sci_events = MAINBOARD_EC_SCI_EVENTS, + .s3_wake_events = MAINBOARD_EC_S3_WAKE_EVENTS, + .s5_wake_events = MAINBOARD_EC_S5_WAKE_EVENTS, + .s0ix_wake_events = MAINBOARD_EC_S0IX_WAKE_EVENTS, + }; + + google_chromeec_events_init(&info, acpi_is_wakeup_s3()); +} diff --git a/src/mainboard/intel/adlrvp/mainboard.c b/src/mainboard/intel/adlrvp/mainboard.c new file mode 100644 index 0000000..d9458cd --- /dev/null +++ b/src/mainboard/intel/adlrvp/mainboard.c @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <device/device.h> +#include <ec/ec.h> +#include <soc/gpio.h> +#include <vendorcode/google/chromeos/chromeos.h> +#include <smbios.h> +#include <string.h> + +const char *smbios_system_sku(void) +{ + static char sku_str[7] = ""; /* sku{0..255} */ + uint32_t sku_id = 255; + + snprintf(sku_str, sizeof(sku_str), "sku%u", sku_id); + return sku_str; +} + +static void mainboard_init(void *chip_info) +{ + variant_configure_gpio_pads(); + + if (CONFIG(EC_GOOGLE_CHROMEEC)) + mainboard_ec_init(); +} + +static void mainboard_enable(struct device *dev) +{ + dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; +} + +struct chip_operations mainboard_ops = { + .init = mainboard_init, + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/intel/adlrvp/smihandler.c b/src/mainboard/intel/adlrvp/smihandler.c new file mode 100644 index 0000000..a3b4323 --- /dev/null +++ b/src/mainboard/intel/adlrvp/smihandler.c @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <cpu/x86/smm.h> +#include <ec/google/chromeec/smm.h> +#include <intelblocks/smihandler.h> +#include <baseboard/ec.h> + +void mainboard_smi_espi_handler(void) +{ + if (!CONFIG(EC_GOOGLE_CHROMEEC)) + return; + + chromeec_smi_process_events(); +} + +void mainboard_smi_sleep(u8 slp_typ) +{ + if (!CONFIG(EC_GOOGLE_CHROMEEC)) + return; + + chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS, MAINBOARD_EC_S5_WAKE_EVENTS); +} + +int mainboard_smi_apmc(u8 apmc) +{ + if (CONFIG(EC_GOOGLE_CHROMEEC)) + chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS, MAINBOARD_EC_SMI_EVENTS); + + return 0; +} diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p/Makefile.inc b/src/mainboard/intel/adlrvp/variants/adlrvp_p/Makefile.inc index 8c05721..513963e 100644 --- a/src/mainboard/intel/adlrvp/variants/adlrvp_p/Makefile.inc +++ b/src/mainboard/intel/adlrvp/variants/adlrvp_p/Makefile.inc @@ -3,3 +3,5 @@ bootblock-y += early_gpio.c
romstage-y += memory.c + +ramstage-y += gpio.c diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb b/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb index a6b0039..3484713 100644 --- a/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb +++ b/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb @@ -4,6 +4,34 @@ device lapic 0 on end end
+ # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "pmc_gpe0_dw0" = "GPP_B" + register "pmc_gpe0_dw1" = "GPP_D" + register "pmc_gpe0_dw2" = "GPP_E" + + # FSP configuration + # Enable Speed Shift Technology/HWP support + register "speed_shift_enable" = "1" + + register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" # Type C port - various configurations – TCP0 + register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" # Type C port - various configurations – TCP1 + register "usb2_ports[2]" = "USB2_PORT_MID(OC3)" # Type C port - various configurations – TCP2 + register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # WWAN M.2 Module / USB2.0 Type-A Port-1 + register "usb2_ports[4]" = "USB2_PORT_MID(OC3)" # Type C port - various configurations – TCP3 + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # FPS connector/USB2.0 Type-A Port-1 + register "usb2_ports[6]" = "USB2_PORT_MID(OC0)" # USB3.2 Gen2x1 Type-A Port - TAP2 + register "usb2_ports[7]" = "USB2_PORT_MID(OC0)" # USB3.2 Gen2x1 Type-A Vertical Port – TAP3 + register "usb2_ports[8]" = "USB2_PORT_MID(OC3)" # USB3.2 Gen2x1 Type-A Port - TAP1 + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # WLAN M.2 Module/BT + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC3)" # USB3.2 Gen2x1 Type-A Port - TAP1 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # USB3.2 Gen2x1 Type-A Port - TAP2 + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)" # USB3.2 Gen2x1 Type-A Vertical Port - TAP3 + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # WWAN M.2 Module + # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f register "gen1_dec" = "0x00fc0801" register "gen2_dec" = "0x000c0201" @@ -41,6 +69,94 @@ # Mark LAN CLK pins as unused as GbE 0:0x1f.6 is disabled below register "PcieClkSrcUsage[6]" = "0xff"
+ register "SataSalpSupport" = "1" + + register "SataPortsEnable[0]" = "1" + register "SataPortsEnable[1]" = "1" + register "SataPortsEnable[2]" = "1" + register "SataPortsEnable[3]" = "1" + + register "SataPortsDevSlp[0]" = "1" + register "SataPortsDevSlp[1]" = "1" + register "SataPortsDevSlp[2]" = "1" + register "SataPortsDevSlp[3]" = "1" + + # Enable EDP in PortA + register "DdiPortAConfig" = "1" + register "DdiPortBConfig" = "1" + + # TCSS USB3 + register "TcssAuxOri" = "0" + + register "s0ix_enable" = "1" + + register "SerialIoI2cMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoDisabled, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + }" + + register "SerialIoGSpiMode" = "{ + [PchSerialIoIndexGSPI0] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI1] = PchSerialIoPci, + [PchSerialIoIndexGSPI2] = PchSerialIoDisabled, + }" + + register "SerialIoGSpiCsMode" = "{ + [PchSerialIoIndexGSPI0] = 0, + [PchSerialIoIndexGSPI1] = 0, + [PchSerialIoIndexGSPI2] = 0, + }" + + register "SerialIoGSpiCsState" = "{ + [PchSerialIoIndexGSPI0] = 0, + [PchSerialIoIndexGSPI1] = 0, + [PchSerialIoIndexGSPI2] = 0, + }" + + register "SerialIoUartMode" = "{ + [PchSerialIoIndexUART0] = PchSerialIoDisabled, + [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoSkipInit, + }" + + # HD Audio + register "PchHdaDspEnable" = "1" + register "PchHdaAudioLinkHdaEnable" = "0" + register "PchHdaAudioLinkDmicEnable[0]" = "1" + register "PchHdaAudioLinkDmicEnable[1]" = "1" + register "PchHdaAudioLinkSndwEnable[0]" = "1" + register "PchHdaAudioLinkSndwEnable[1]" = "1" + # iDisp-Link T-Mode 0: 2T, 2: 4T, 3: 8T, 4: 16T + register "PchHdaIDispLinkTmode" = "2" + # iDisp-Link Freq 4: 96MHz, 3: 48MHz. + register "PchHdaIDispLinkFrequency" = "4" + # Not disconnected/enumerable + register "PchHdaIDispCodecDisconnect" = "0" + + # Intel Common SoC Config + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + }, + }" + device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Graphics diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p/gpio.c b/src/mainboard/intel/adlrvp/variants/adlrvp_p/gpio.c new file mode 100644 index 0000000..f06e70e --- /dev/null +++ b/src/mainboard/intel/adlrvp/variants/adlrvp_p/gpio.c @@ -0,0 +1,297 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <commonlib/helpers.h> + +/* Pad configuration in ramstage*/ +static const struct pad_config gpio_table[] = { + /* SSD1_PWREN CPU SSD1 */ + PAD_CFG_GPO(GPP_D14, 1, PLTRST), + /* SSD1_RESET CPU SSD1 */ + PAD_CFG_GPO(GPP_F20, 1, PLTRST), + /* BT_RF_KILL_N */ + PAD_CFG_GPO(GPP_A13, 1, PLTRST), + /* WLAN RST# */ + PAD_CFG_GPO(GPP_H2, 1, PLTRST), + /* WIFI_WAKE_N */ + PAD_CFG_GPI_IRQ_WAKE(GPP_D13, NONE, DEEP, LEVEL, INVERT), + /* x4 PCIE slot1 PWREN */ + PAD_CFG_GPO(GPP_H17, 0, PLTRST), + /* x4 PCIE slot 1 RESET */ + PAD_CFG_GPO(GPP_F10, 1, PLTRST), + /* Retimer Force Power */ + PAD_CFG_GPO(GPP_E4, 0, PLTRST), + /* PEG Slot RST# */ + PAD_CFG_GPO(GPP_B2, 1, PLTRST), + /* M.2 SSD_2 Reset */ + PAD_CFG_GPO(GPP_H0, 1, PLTRST), + /* CAM1-IRQ */ + PAD_CFG_GPO(GPP_B23, 1, PLTRST), + /* CAM_STROBE */ + PAD_CFG_GPO(GPP_B18, 0, PLTRST), + /* Audio Codec INT N */ + PAD_CFG_GPI_APIC(GPP_H3, NONE, PLTRST, LEVEL, INVERT), + /* TCH PAD Power EN */ + PAD_CFG_GPO(GPP_F7, 1, PLTRST), + /* THC1 SPI2 RST# */ + PAD_CFG_GPO(GPP_F17, 1, PLTRST), + /* THC1_SPI2_INTB */ + PAD_CFG_GPI_APIC(GPP_F18, NONE, PLTRST, EDGE_SINGLE, INVERT), + /* THC1_SPI2_INTB */ + PAD_CFG_GPI(GPP_E17, NONE, PLTRST), + /* EC_SMI_N */ + PAD_CFG_GPI_SMI_LOW(GPP_E7, NONE, PLTRST, LEVEL), + /* EC_SLP_S0_CS_N */ + PAD_CFG_GPO(GPP_F9, 1, PLTRST), + /* WIFI RF KILL */ + PAD_CFG_GPO(GPP_E3, 1, PLTRST), + /* DISP_AUX_N_BIAS_GPIO */ + PAD_CFG_GPO(GPP_E23, 1, PLTRST), + /* WWAN WAKE N*/ + PAD_CFG_GPI_IRQ_WAKE(GPP_D18, NONE, DEEP, LEVEL, INVERT), + /* WWAN_DISABLE_N */ + PAD_CFG_GPO(GPP_D15, 1, PLTRST), + /* WWAN_RST# */ + PAD_CFG_GPO(GPP_E10, 1, PLTRST), + /* WWAN_PWR_EN */ + PAD_CFG_GPO(GPP_E13, 1, DEEP), + /* WWAN_PERST# */ + PAD_CFG_GPO(GPP_C5, 1, PLTRST), + /* PEG_SLOT_WAKE_N */ + PAD_CFG_GPI(GPP_A20, NONE, PLTRST), + /* UART_BT_WAKE_N */ + PAD_CFG_GPI_IRQ_WAKE(GPP_E0, NONE, DEEP, LEVEL, INVERT), + /* CAM CONN1 CLKEN */ + PAD_CFG_GPO(GPP_H15, 1, PLTRST), + /* CPU SSD2 PWREN */ + PAD_CFG_GPO(GPP_C2, 1, PLTRST), + /* CPU SSD2 RST# */ + PAD_CFG_GPO(GPP_H1, 1, PLTRST), + /* Sata direct Power */ + PAD_CFG_GPO(GPP_B4, 1, PLTRST), + + /* THC0 SPI1 CLK */ + PAD_CFG_NF(GPP_E11, NONE, DEEP, NF2), + /* THC0 SPI1 IO 1 */ + PAD_CFG_NF(GPP_E12, NONE, DEEP, NF2), + /* THC0 SPI1 IO 2 */ + PAD_CFG_NF(GPP_E1, NONE, DEEP, NF2), + /* THC0 SPI IO 3 */ + PAD_CFG_NF(GPP_E2, NONE, DEEP, NF2), + /* THC1 SPI1 RSTB */ + PAD_CFG_NF(GPP_E6, NONE, DEEP, NF2), + /* UART_RX(1) */ + PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), + /* UART_RX(2) */ + PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), + /* UART_RX(4) */ + PAD_CFG_NF(GPP_T4, NONE, DEEP, NF1), + /* UART_RX(5) */ + PAD_CFG_NF(GPP_T8, NONE, DEEP, NF1), + /* UART_RX(6) */ + PAD_CFG_NF(GPP_T12, NONE, DEEP, NF1), + + /* UART_TX(1) */ + PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), + /* UART_TX(2) */ + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), + /* UART_TX(4) */ + PAD_CFG_NF(GPP_T5, NONE, DEEP, NF1), + /* UART_TX(5) */ + PAD_CFG_NF(GPP_T9, NONE, DEEP, NF1), + /* UART_TX(6) */ + PAD_CFG_NF(GPP_T13, NONE, DEEP, NF1), + + /* UART_RTS(1) */ + PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1), + /* UART_RTS(2) */ + PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1), + /* UART_RTS(4) */ + PAD_CFG_NF(GPP_T6, NONE, DEEP, NF1), + /* UART_RTS(5) */ + PAD_CFG_NF(GPP_T10, NONE, DEEP, NF1), + /* UART_RTS(6) */ + PAD_CFG_NF(GPP_T14, NONE, DEEP, NF1), + + /* UART_CTS(1) */ + PAD_CFG_NF(GPP_C15, NONE, DEEP, NF1), + /* UART_CTS(2) */ + PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1), + /* UART_CTS(4) */ + PAD_CFG_NF(GPP_T7, NONE, DEEP, NF1), + /* UART_CTS(5) */ + PAD_CFG_NF(GPP_T11, NONE, DEEP, NF1), + /* UART_CTS(6) */ + PAD_CFG_NF(GPP_T15, NONE, DEEP, NF1), + + /* SPI_MOSI(1) */ + PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1), + /* SPI_MOSI(2) */ + PAD_CFG_NF(GPP_D12, NONE, DEEP, NF2), + + /* SPI_MIS0(0) */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), + /* SPI_MIS0(1) */ + PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1), + /* SPI_MIS0(2) */ + PAD_CFG_NF(GPP_D11, NONE, DEEP, NF2), + + /* SPI_CLK(0) */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), + /* SPI_CLK(1) */ + PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1), + /* SPI_CLK(2) */ + PAD_CFG_NF(GPP_D10, NONE, DEEP, NF2), + + /* SPI_CS(0, 0) */ + PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), + /* SPI_CS(0, 1) */ + PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), + /* SPI_CS(1, 0) */ + PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1), + /* SPI_CS(2, 0) */ + PAD_CFG_NF(GPP_D9, NONE, DEEP, NF2), + + /* I2C_SCL(0) */ + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), + /* I2C_SCL(1) */ + PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), + /* I2C_SCL(2) */ + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), + /* I2C_SCL(3) */ + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), + /* I2C_SCL(5) */ + PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), + /* I2C_SCL(6) */ + PAD_CFG_NF(GPP_T1, NONE, DEEP, NF1), + /* I2C_SCL(7) */ + PAD_CFG_NF(GPP_T3, NONE, DEEP, NF1), + + /* I2C_SDA(0) */ + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), + /* I2C_SDA(1) */ + PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), + /* I2C_SDA(2) */ + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), + /* I2C_SDA(3) */ + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), + /* I2C_SDA(5) */ + PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), + /* I2C_SDA(6) */ + PAD_CFG_NF(GPP_T0, NONE, DEEP, NF1), + /* I2C_SDA(7) */ + PAD_CFG_NF(GPP_T2, NONE, DEEP, NF1), + + /* I2S0_SCLK */ + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), + /* I2S0_SFRM */ + PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), + /* I2S0_TXD */ + PAD_CFG_NF(GPP_R2, NONE, DEEP, NF2), + /* I2S0_RXD */ + PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), + + /* I2S1_SCLK */ + PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1), + /* I2S1_SFRM */ + PAD_CFG_NF(GPP_R5, NONE, DEEP, NF2), + /* I2S1_TXD */ + PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2), + /* I2S1_RXD */ + PAD_CFG_NF(GPP_R7, NONE, DEEP, NF2), + + /* I2S2_SCLK */ + PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), + /* I2S2_SFRM */ + PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), + /* I2S2_TXD */ + PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), + /* I2S2_RXD */ + PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), + + /* I2S_MCLK1_OUT */ + PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), + /* I2S_MCLK2_INOUT */ + PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), + + /* SNDW1_CLK */ + PAD_CFG_NF(GPP_S0, NONE, DEEP, NF1), + /* SNDW1_DATA */ + PAD_CFG_NF(GPP_S1, NONE, DEEP, NF1), + /* SNDW2_CLK */ + PAD_CFG_NF(GPP_S2, NONE, DEEP, NF1), + /* SNDW2_DATA */ + PAD_CFG_NF(GPP_S3, NONE, DEEP, NF1), + /* SNDW3_CLK */ + PAD_CFG_NF(GPP_S4, NONE, DEEP, NF1), + /* SNDW3_DATA */ + PAD_CFG_NF(GPP_S5, NONE, DEEP, NF1), + /* SNDW4_CLK */ + PAD_CFG_NF(GPP_S6, NONE, DEEP, NF1), + /* SNDW4_DATA */ + PAD_CFG_NF(GPP_S7, NONE, DEEP, NF1), + + /* SMB_CLK */ + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), + /* SMB_DATA */ + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), + + /* SATADevSlpPin to GPIO pin mapping */ + PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), + /* SATA DIRECT DEVSLP*/ + PAD_CFG_NF(GPP_H12, NONE, DEEP, NF5), + + /* SATA LED pin */ + PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), + + /* USB2 OC0 pins */ + PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), + /* USB2 OC1 pins */ + PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), + /* USB2 OC2 pins */ + PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), + /* USB2 OC3 pins */ + PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), + + /* GPIO pin for PCIE SRCCLKREQB */ + PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), + + /* DDP1/2/3/4/A/B/C CTRLCLK and CTRLDATA pins */ + PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E22, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A21, NONE, DEEP, NF2), + PAD_CFG_NF(GPP_A22, NONE, DEEP, NF2), + + /* IMGCLKOUT */ + PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H23, NONE, DEEP, NF1), +}; + +void variant_configure_gpio_pads(void) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), +}; + +const struct cros_gpio *variant_cros_gpios(size_t *num) +{ + *num = ARRAY_SIZE(cros_gpios); + return cros_gpios; +} diff --git a/src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/ec.h b/src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/ec.h new file mode 100644 index 0000000..4303faf --- /dev/null +++ b/src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/ec.h @@ -0,0 +1,73 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __BASEBOARD_EC_H__ +#define __BASEBOARD_EC_H__ + +#include <ec/ec.h> +#include <ec/google/chromeec/ec_commands.h> +#include <baseboard/gpio.h> + +#define MAINBOARD_EC_SCI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_MUX)) + +#define MAINBOARD_EC_SMI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)) + +/* EC can wake from S5 with lid or power button */ +#define MAINBOARD_EC_S5_WAKE_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) + +/* + * EC can wake from S3 with lid or power button or key press or + * mode change event. + */ +#define MAINBOARD_EC_S3_WAKE_EVENTS \ + (MAINBOARD_EC_S5_WAKE_EVENTS |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)) + +#define MAINBOARD_EC_S0IX_WAKE_EVENTS (MAINBOARD_EC_S3_WAKE_EVENTS) + +/* Log EC wake events plus EC shutdown events */ +#define MAINBOARD_EC_LOG_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC)) + +/* + * ACPI related definitions for ASL code. + */ + +/* Enable EC backed ALS device in ACPI */ +#define EC_ENABLE_ALS_DEVICE + +/* Enable EC sync interrupt, EC_SYNC_IRQ is defined in baseboard/gpio.h */ +#define EC_ENABLE_SYNC_IRQ + +/* Enable EC backed PD MCU device in ACPI */ +#define EC_ENABLE_PD_MCU_DEVICE + +/* Enable LID switch and provide wake pin for EC */ +#define EC_ENABLE_LID_SWITCH +#define EC_ENABLE_WAKE_PIN GPE_EC_WAKE + +#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */ +#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */ +#define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */ + +#endif /* __BASEBOARD_EC_H__ */ diff --git a/src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/variants.h index 5288b6f..005ec83 100644 --- a/src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/variants.h @@ -20,7 +20,8 @@ /* The next set of functions return the gpio table and fill in the number of * entries for each table. */ const struct cros_gpio *variant_cros_gpios(size_t *num); - +/* Functions to configure GPIO as per variant schematics */ +void variant_configure_gpio_pads(void); void variant_configure_early_gpio_pads(void);
size_t variant_memory_sku(void);
Hello build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46265
to look at the new patch set (#2).
Change subject: mb/intel/adlrvp: Add ADL-P ramstage mainboard code ......................................................................
mb/intel/adlrvp: Add ADL-P ramstage mainboard code
List of changes: 1. Add devicetree.cb config parameters related to FSP-S UPD 2. Configure GPIO as per ADL-P RVP 3. Add files required for Ramstage (ec.c, mainboard.c) 4. Add smihandler.c for SMM
TEST=Able to reach till payload
Change-Id: I120885956c88babfa09d24ce1079d49306919b8a Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/mainboard/intel/adlrvp/Makefile.inc A src/mainboard/intel/adlrvp/ec.c A src/mainboard/intel/adlrvp/mainboard.c A src/mainboard/intel/adlrvp/smihandler.c M src/mainboard/intel/adlrvp/variants/adlrvp_p/Makefile.inc M src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb A src/mainboard/intel/adlrvp/variants/adlrvp_p/gpio.c A src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/ec.h M src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/variants.h 9 files changed, 581 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/46265/2
Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Tim Wawrzynczak, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46265
to look at the new patch set (#5).
Change subject: mb/intel/adlrvp: Add ADL-P ramstage mainboard code ......................................................................
mb/intel/adlrvp: Add ADL-P ramstage mainboard code
List of changes: 1. Add devicetree.cb config parameters related to FSP-S UPD 2. Configure GPIO as per ADL-P RVP 3. Add files required for Ramstage (ec.c, mainboard.c) 4. Add smihandler.c for SMM
TEST=Able to reach till payload
Change-Id: I120885956c88babfa09d24ce1079d49306919b8a Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/mainboard/intel/adlrvp/Makefile.inc A src/mainboard/intel/adlrvp/ec.c A src/mainboard/intel/adlrvp/mainboard.c A src/mainboard/intel/adlrvp/smihandler.c M src/mainboard/intel/adlrvp/variants/adlrvp_p/Makefile.inc M src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb A src/mainboard/intel/adlrvp/variants/adlrvp_p/gpio.c A src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/ec.h M src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/variants.h 9 files changed, 583 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/46265/5
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46265 )
Change subject: mb/intel/adlrvp: Add ADL-P ramstage mainboard code ......................................................................
Patch Set 5:
Angel, Tim, If you could help to take a look this CL?
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46265 )
Change subject: mb/intel/adlrvp: Add ADL-P ramstage mainboard code ......................................................................
Patch Set 5: Code-Review+1
(6 comments)
https://review.coreboot.org/c/coreboot/+/46265/5/src/mainboard/intel/adlrvp/... File src/mainboard/intel/adlrvp/mainboard.c:
https://review.coreboot.org/c/coreboot/+/46265/5/src/mainboard/intel/adlrvp/... PS5, Line 14: /* sku{0..255} */ If you make `sku_id` an uint8_t, this comment can be dropped.
https://review.coreboot.org/c/coreboot/+/46265/5/src/mainboard/intel/adlrvp/... PS5, Line 15: 255 Is this supposed to be hardcoded?
https://review.coreboot.org/c/coreboot/+/46265/5/src/mainboard/intel/adlrvp/... File src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/46265/5/src/mainboard/intel/adlrvp/... PS5, Line 72: register "SataSalpSupport" = "1" : : register "SataPortsEnable[0]" = "1" : register "SataPortsEnable[1]" = "1" : register "SataPortsEnable[2]" = "1" : register "SataPortsEnable[3]" = "1" : : register "SataPortsDevSlp[0]" = "1" : register "SataPortsDevSlp[1]" = "1" : register "SataPortsDevSlp[2]" = "1" : register "SataPortsDevSlp[3]" = "1" Move these settings under the SATA PCI device scope?
Also, you can initialize the arrays like this:
register "SataPortsEnable" = "{ [0] = 1, [1] = 1, [2] = 1, [3] = 1, }"
register "SataPortsDevSlp" = "{ [0] = 1, [1] = 1, [2] = 1, [3] = 1, }"
https://review.coreboot.org/c/coreboot/+/46265/5/src/mainboard/intel/adlrvp/... PS5, Line 91: s0ix_enable Does S0ix entry work with this patch?
https://review.coreboot.org/c/coreboot/+/46265/5/src/mainboard/intel/adlrvp/... PS5, Line 104: PchSerialIoPci GSPI1 is disabled in the devicetree
https://review.coreboot.org/c/coreboot/+/46265/5/src/mainboard/intel/adlrvp/... PS5, Line 105: [PchSerialIoIndexGSPI2] = PchSerialIoDisabled, GSPI2 not in the devicetree?
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46265 )
Change subject: mb/intel/adlrvp: Add ADL-P ramstage mainboard code ......................................................................
Patch Set 5:
(6 comments)
https://review.coreboot.org/c/coreboot/+/46265/5/src/mainboard/intel/adlrvp/... File src/mainboard/intel/adlrvp/mainboard.c:
https://review.coreboot.org/c/coreboot/+/46265/5/src/mainboard/intel/adlrvp/... PS5, Line 14: /* sku{0..255} */
If you make `sku_id` an uint8_t, this comment can be dropped.
Ack
https://review.coreboot.org/c/coreboot/+/46265/5/src/mainboard/intel/adlrvp/... PS5, Line 15: 255
Is this supposed to be hardcoded?
This is what it is today but very nice feedback, ideally this is to uniquely identify the SKU, i believe we are good with board ID check. adding that now.
https://review.coreboot.org/c/coreboot/+/46265/5/src/mainboard/intel/adlrvp/... File src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/46265/5/src/mainboard/intel/adlrvp/... PS5, Line 72: register "SataSalpSupport" = "1" : : register "SataPortsEnable[0]" = "1" : register "SataPortsEnable[1]" = "1" : register "SataPortsEnable[2]" = "1" : register "SataPortsEnable[3]" = "1" : : register "SataPortsDevSlp[0]" = "1" : register "SataPortsDevSlp[1]" = "1" : register "SataPortsDevSlp[2]" = "1" : register "SataPortsDevSlp[3]" = "1"
Move these settings under the SATA PCI device scope? […]
Ack
https://review.coreboot.org/c/coreboot/+/46265/5/src/mainboard/intel/adlrvp/... PS5, Line 91: s0ix_enable
Does S0ix entry work with this patch?
Yes Angel, S0ix use case is not fully enabled but system is going to lower c-state and system is going to lower system states as well
https://review.coreboot.org/c/coreboot/+/46265/5/src/mainboard/intel/adlrvp/... PS5, Line 104: PchSerialIoPci
GSPI1 is disabled in the devicetree
Ack
https://review.coreboot.org/c/coreboot/+/46265/5/src/mainboard/intel/adlrvp/... PS5, Line 105: [PchSerialIoIndexGSPI2] = PchSerialIoDisabled,
GSPI2 not in the devicetree?
i guess you meant GSPI3 not 2 😊
Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Tim Wawrzynczak, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46265
to look at the new patch set (#6).
Change subject: mb/intel/adlrvp: Add ADL-P ramstage mainboard code ......................................................................
mb/intel/adlrvp: Add ADL-P ramstage mainboard code
List of changes: 1. Add devicetree.cb config parameters related to FSP-S UPD 2. Configure GPIO as per ADL-P RVP 3. Add files required for Ramstage (ec.c, mainboard.c) 4. Add smihandler.c for SMM
TEST=Able to reach till payload
Change-Id: I120885956c88babfa09d24ce1079d49306919b8a Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/mainboard/intel/adlrvp/Makefile.inc A src/mainboard/intel/adlrvp/ec.c A src/mainboard/intel/adlrvp/mainboard.c A src/mainboard/intel/adlrvp/smihandler.c M src/mainboard/intel/adlrvp/variants/adlrvp_p/Makefile.inc M src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb A src/mainboard/intel/adlrvp/variants/adlrvp_p/gpio.c A src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/ec.h M src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/variants.h 9 files changed, 593 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/46265/6
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46265 )
Change subject: mb/intel/adlrvp: Add ADL-P ramstage mainboard code ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/46265/5/src/mainboard/intel/adlrvp/... File src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/46265/5/src/mainboard/intel/adlrvp/... PS5, Line 105: [PchSerialIoIndexGSPI2] = PchSerialIoDisabled,
i guess you meant GSPI3 not 2 😊
I see `GSPI2` here in the array index, and can't see GSPI3 anywhere.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46265 )
Change subject: mb/intel/adlrvp: Add ADL-P ramstage mainboard code ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/46265/5/src/mainboard/intel/adlrvp/... File src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/46265/5/src/mainboard/intel/adlrvp/... PS5, Line 105: [PchSerialIoIndexGSPI2] = PchSerialIoDisabled,
I see `GSPI2` here in the array index, and can't see GSPI3 anywhere.
Yes, GSPI3 was missing added now in latest patchset.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46265 )
Change subject: mb/intel/adlrvp: Add ADL-P ramstage mainboard code ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/46265/5/src/mainboard/intel/adlrvp/... File src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/46265/5/src/mainboard/intel/adlrvp/... PS5, Line 105: [PchSerialIoIndexGSPI2] = PchSerialIoDisabled,
Yes, GSPI3 was missing added now in latest patchset.
Oh, I see them now:
device pci 12.6 off end # GSPI2 device pci 13.0 off end # GSPI3
I somehow didn't find these lines earlier.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46265 )
Change subject: mb/intel/adlrvp: Add ADL-P ramstage mainboard code ......................................................................
Patch Set 6:
(2 comments)
https://review.coreboot.org/c/coreboot/+/46265/5/src/mainboard/intel/adlrvp/... File src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/46265/5/src/mainboard/intel/adlrvp/... PS5, Line 91: s0ix_enable
Yes Angel, S0ix use case is not fully enabled but system is going to lower c-state and system is goi […]
Alright. I wanted to know because S0ix entry requirements are somewhat unclear.
https://review.coreboot.org/c/coreboot/+/46265/5/src/mainboard/intel/adlrvp/... PS5, Line 105: [PchSerialIoIndexGSPI2] = PchSerialIoDisabled,
Oh, I see them now: […]
Done
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46265 )
Change subject: mb/intel/adlrvp: Add ADL-P ramstage mainboard code ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/46265/5/src/mainboard/intel/adlrvp/... File src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/46265/5/src/mainboard/intel/adlrvp/... PS5, Line 91: s0ix_enable
Alright. I wanted to know because S0ix entry requirements are somewhat unclear.
Yes, you are right, its not just depends in this config there are other SOC related FW also and HW IP might also block S0ix but this is basic to have required ACPI and C-states getting exposed.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46265 )
Change subject: mb/intel/adlrvp: Add ADL-P ramstage mainboard code ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/46265/5/src/mainboard/intel/adlrvp/... File src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/46265/5/src/mainboard/intel/adlrvp/... PS5, Line 91: s0ix_enable
Yes, you are right, its not just depends in this config there are other SOC related FW also and HW I […]
So, if I understood correctly, `s0ix_enable = 0` would also disable C-states?
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46265 )
Change subject: mb/intel/adlrvp: Add ADL-P ramstage mainboard code ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/46265/5/src/mainboard/intel/adlrvp/... File src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/46265/5/src/mainboard/intel/adlrvp/... PS5, Line 91: s0ix_enable
So, if I understood correctly, `s0ix_enable = 0` would also disable C-states?
So most differentiation is here to have S0ix we first need to ensure C10 is hitting hence need to publish the lowest C-state capability as well
https://github.com/coreboot/coreboot/blob/master/src/soc/intel/alderlake/acp...
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46265 )
Change subject: mb/intel/adlrvp: Add ADL-P ramstage mainboard code ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/46265/5/src/mainboard/intel/adlrvp/... File src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/46265/5/src/mainboard/intel/adlrvp/... PS5, Line 91: s0ix_enable
So most differentiation is here to have S0ix we first need to ensure C10 is hitting hence need to pu […]
Ah, I see. Thank you!
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46265 )
Change subject: mb/intel/adlrvp: Add ADL-P ramstage mainboard code ......................................................................
Patch Set 6: Code-Review+1
(2 comments)
https://review.coreboot.org/c/coreboot/+/46265/6/src/mainboard/intel/adlrvp/... File src/mainboard/intel/adlrvp/mainboard.c:
https://review.coreboot.org/c/coreboot/+/46265/6/src/mainboard/intel/adlrvp/... PS6, Line 10: #include <string.h> #include <stdint.h>
https://review.coreboot.org/c/coreboot/+/46265/6/src/mainboard/intel/adlrvp/... File src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/46265/6/src/mainboard/intel/adlrvp/... PS6, Line 143: PchHdaIDispLinkFrequency for another patch: this should be an enum
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46265 )
Change subject: mb/intel/adlrvp: Add ADL-P ramstage mainboard code ......................................................................
Patch Set 6:
(2 comments)
https://review.coreboot.org/c/coreboot/+/46265/6/src/mainboard/intel/adlrvp/... File src/mainboard/intel/adlrvp/mainboard.c:
https://review.coreboot.org/c/coreboot/+/46265/6/src/mainboard/intel/adlrvp/... PS6, Line 10: #include <string.h>
#include <stdint. […]
Ack
https://review.coreboot.org/c/coreboot/+/46265/6/src/mainboard/intel/adlrvp/... File src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/46265/6/src/mainboard/intel/adlrvp/... PS6, Line 143: PchHdaIDispLinkFrequency
for another patch: this should be an enum
Perfect, I will take a note
Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Tim Wawrzynczak, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46265
to look at the new patch set (#7).
Change subject: mb/intel/adlrvp: Add ADL-P ramstage mainboard code ......................................................................
mb/intel/adlrvp: Add ADL-P ramstage mainboard code
List of changes: 1. Add devicetree.cb config parameters related to FSP-S UPD 2. Configure GPIO as per ADL-P RVP 3. Add files required for Ramstage (ec.c, mainboard.c) 4. Add smihandler.c for SMM
TEST=Able to reach till payload
Change-Id: I120885956c88babfa09d24ce1079d49306919b8a Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/mainboard/intel/adlrvp/Makefile.inc A src/mainboard/intel/adlrvp/ec.c A src/mainboard/intel/adlrvp/mainboard.c A src/mainboard/intel/adlrvp/smihandler.c M src/mainboard/intel/adlrvp/variants/adlrvp_p/Makefile.inc M src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb A src/mainboard/intel/adlrvp/variants/adlrvp_p/gpio.c A src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/ec.h M src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/variants.h 9 files changed, 594 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/46265/7
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46265 )
Change subject: mb/intel/adlrvp: Add ADL-P ramstage mainboard code ......................................................................
Patch Set 7: Code-Review+2
LGTM, but I'd like to have someone else ack this patch as well.
Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Tim Wawrzynczak, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46265
to look at the new patch set (#8).
Change subject: mb/intel/adlrvp: Add ADL-P ramstage mainboard code ......................................................................
mb/intel/adlrvp: Add ADL-P ramstage mainboard code
List of changes: 1. Add devicetree.cb config parameters related to FSP-S UPD 2. Configure GPIO as per ADL-P RVP 3. Add files required for Ramstage (ec.c, mainboard.c) 4. Add smihandler.c for SMM
TEST=Able to reach till payload
Change-Id: I120885956c88babfa09d24ce1079d49306919b8a Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/mainboard/intel/adlrvp/Makefile.inc A src/mainboard/intel/adlrvp/ec.c A src/mainboard/intel/adlrvp/mainboard.c A src/mainboard/intel/adlrvp/smihandler.c M src/mainboard/intel/adlrvp/variants/adlrvp_p/Makefile.inc M src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb A src/mainboard/intel/adlrvp/variants/adlrvp_p/gpio.c A src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/ec.h M src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/variants.h 9 files changed, 594 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/46265/8
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46265 )
Change subject: mb/intel/adlrvp: Add ADL-P ramstage mainboard code ......................................................................
Patch Set 8:
Patch Set 7: Code-Review+2
LGTM, but I'd like to have someone else ack this patch as well.
Sure Angel, my bad there was syntax error
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46265 )
Change subject: mb/intel/adlrvp: Add ADL-P ramstage mainboard code ......................................................................
Patch Set 8: Code-Review+2
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46265 )
Change subject: mb/intel/adlrvp: Add ADL-P ramstage mainboard code ......................................................................
Patch Set 8:
Tim, requesting you to take a look here
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46265 )
Change subject: mb/intel/adlrvp: Add ADL-P ramstage mainboard code ......................................................................
Patch Set 8: Code-Review+2
Patch Set 8:
Tim, requesting you to take a look here
Sorry Subrata, I'm just slammed with reviews 🤓 LGTM
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46265 )
Change subject: mb/intel/adlrvp: Add ADL-P ramstage mainboard code ......................................................................
Patch Set 8:
(3 comments)
https://review.coreboot.org/c/coreboot/+/46265/8//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/46265/8//COMMIT_MSG@12 PS8, Line 12: Ramstage ramstage
https://review.coreboot.org/c/coreboot/+/46265/8//COMMIT_MSG@14 PS8, Line 14: 1. What board did you take as a template? 2. Please mention the UART devicetree changes, and mention if UART works.
https://review.coreboot.org/c/coreboot/+/46265/8//COMMIT_MSG@15 PS8, Line 15: payload Which payload?
Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46265 )
Change subject: mb/intel/adlrvp: Add ADL-P ramstage mainboard code ......................................................................
Patch Set 8:
(1 comment)
https://review.coreboot.org/c/coreboot/+/46265/8//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/46265/8//COMMIT_MSG@15 PS8, Line 15: payload
Which payload?
"till payload" -> it got into the payload, so it doesn't really matter which one.
Hello build bot (Jenkins), Patrick Georgi, Furquan Shaikh, Martin Roth, Tim Wawrzynczak, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46265
to look at the new patch set (#9).
Change subject: mb/intel/adlrvp: Add ADL-P ramstage mainboard code ......................................................................
mb/intel/adlrvp: Add ADL-P ramstage mainboard code
List of changes: 1. Add devicetree.cb config parameters related to FSP-S UPD 2. Configure GPIO as per ADL-P RVP 3. Add files required for ramstage(ec.c, mainboard.c) 4. Add smihandler.c for SMM 5. Add devicetree changes as below - USB OC PIN programing - GPE configuration - SATA port mapping - LPSS configuration - Audio configuration - IA common SoC configuration - EDP configuration - TCSS USB configuration - Enable S0ix
TEST=Able to boot ADL-P RVP without Chrome EC (using on-board EC) with UART log over legacy UART0 port as 0x3f8 with NVME at RP9 reach till depthcharge payload.
Change-Id: I120885956c88babfa09d24ce1079d49306919b8a Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/mainboard/intel/adlrvp/Makefile.inc A src/mainboard/intel/adlrvp/ec.c A src/mainboard/intel/adlrvp/mainboard.c A src/mainboard/intel/adlrvp/smihandler.c M src/mainboard/intel/adlrvp/variants/adlrvp_p/Makefile.inc M src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb A src/mainboard/intel/adlrvp/variants/adlrvp_p/gpio.c A src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/ec.h M src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/variants.h 9 files changed, 594 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/46265/9
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46265 )
Change subject: mb/intel/adlrvp: Add ADL-P ramstage mainboard code ......................................................................
Patch Set 9:
(2 comments)
https://review.coreboot.org/c/coreboot/+/46265/8//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/46265/8//COMMIT_MSG@12 PS8, Line 12: Ramstage
ramstage
Ack
https://review.coreboot.org/c/coreboot/+/46265/8//COMMIT_MSG@14 PS8, Line 14:
- What board did you take as a template? […]
Ack
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46265 )
Change subject: mb/intel/adlrvp: Add ADL-P ramstage mainboard code ......................................................................
mb/intel/adlrvp: Add ADL-P ramstage mainboard code
List of changes: 1. Add devicetree.cb config parameters related to FSP-S UPD 2. Configure GPIO as per ADL-P RVP 3. Add files required for ramstage(ec.c, mainboard.c) 4. Add smihandler.c for SMM 5. Add devicetree changes as below - USB OC PIN programing - GPE configuration - SATA port mapping - LPSS configuration - Audio configuration - IA common SoC configuration - EDP configuration - TCSS USB configuration - Enable S0ix
TEST=Able to boot ADL-P RVP without Chrome EC (using on-board EC) with UART log over legacy UART0 port as 0x3f8 with NVME at RP9 reach till depthcharge payload.
Change-Id: I120885956c88babfa09d24ce1079d49306919b8a Signed-off-by: Subrata Banik subrata.banik@intel.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/46265 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Angel Pons th3fanbus@gmail.com Reviewed-by: Tim Wawrzynczak twawrzynczak@chromium.org --- M src/mainboard/intel/adlrvp/Makefile.inc A src/mainboard/intel/adlrvp/ec.c A src/mainboard/intel/adlrvp/mainboard.c A src/mainboard/intel/adlrvp/smihandler.c M src/mainboard/intel/adlrvp/variants/adlrvp_p/Makefile.inc M src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb A src/mainboard/intel/adlrvp/variants/adlrvp_p/gpio.c A src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/ec.h M src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/variants.h 9 files changed, 594 insertions(+), 4 deletions(-)
Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved
diff --git a/src/mainboard/intel/adlrvp/Makefile.inc b/src/mainboard/intel/adlrvp/Makefile.inc index e8a0eca..2ca32f3 100644 --- a/src/mainboard/intel/adlrvp/Makefile.inc +++ b/src/mainboard/intel/adlrvp/Makefile.inc @@ -11,7 +11,12 @@ romstage-y += romstage_fsp_params.c romstage-y += board_id.c
+smm-y += smihandler.c + ramstage-$(CONFIG_CHROMEOS) += chromeos.c +ramstage-y += ec.c +ramstage-y += mainboard.c +ramstage-y += board_id.c
subdirs-y += variants/baseboard CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include diff --git a/src/mainboard/intel/adlrvp/ec.c b/src/mainboard/intel/adlrvp/ec.c new file mode 100644 index 0000000..14760017 --- /dev/null +++ b/src/mainboard/intel/adlrvp/ec.c @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +#include <ec/ec.h> +#include <ec/google/chromeec/ec.h> +#include <baseboard/ec.h> + +void mainboard_ec_init(void) +{ + const struct google_chromeec_event_info info = { + .log_events = MAINBOARD_EC_LOG_EVENTS, + .sci_events = MAINBOARD_EC_SCI_EVENTS, + .s3_wake_events = MAINBOARD_EC_S3_WAKE_EVENTS, + .s5_wake_events = MAINBOARD_EC_S5_WAKE_EVENTS, + .s0ix_wake_events = MAINBOARD_EC_S0IX_WAKE_EVENTS, + }; + + google_chromeec_events_init(&info, acpi_is_wakeup_s3()); +} diff --git a/src/mainboard/intel/adlrvp/mainboard.c b/src/mainboard/intel/adlrvp/mainboard.c new file mode 100644 index 0000000..fb25578 --- /dev/null +++ b/src/mainboard/intel/adlrvp/mainboard.c @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <device/device.h> +#include <ec/ec.h> +#include <soc/gpio.h> +#include <vendorcode/google/chromeos/chromeos.h> +#include <smbios.h> +#include <stdint.h> +#include <string.h> + +#include "board_id.h" + +const char *smbios_system_sku(void) +{ + static char sku_str[7] = ""; + uint8_t sku_id = get_board_id(); + + snprintf(sku_str, sizeof(sku_str), "sku%u", sku_id); + return sku_str; +} + +static void mainboard_init(void *chip_info) +{ + variant_configure_gpio_pads(); + + if (CONFIG(EC_GOOGLE_CHROMEEC)) + mainboard_ec_init(); +} + +static void mainboard_enable(struct device *dev) +{ + dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; +} + +struct chip_operations mainboard_ops = { + .init = mainboard_init, + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/intel/adlrvp/smihandler.c b/src/mainboard/intel/adlrvp/smihandler.c new file mode 100644 index 0000000..a3b4323 --- /dev/null +++ b/src/mainboard/intel/adlrvp/smihandler.c @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <cpu/x86/smm.h> +#include <ec/google/chromeec/smm.h> +#include <intelblocks/smihandler.h> +#include <baseboard/ec.h> + +void mainboard_smi_espi_handler(void) +{ + if (!CONFIG(EC_GOOGLE_CHROMEEC)) + return; + + chromeec_smi_process_events(); +} + +void mainboard_smi_sleep(u8 slp_typ) +{ + if (!CONFIG(EC_GOOGLE_CHROMEEC)) + return; + + chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS, MAINBOARD_EC_S5_WAKE_EVENTS); +} + +int mainboard_smi_apmc(u8 apmc) +{ + if (CONFIG(EC_GOOGLE_CHROMEEC)) + chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS, MAINBOARD_EC_SMI_EVENTS); + + return 0; +} diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p/Makefile.inc b/src/mainboard/intel/adlrvp/variants/adlrvp_p/Makefile.inc index 8c05721..513963e 100644 --- a/src/mainboard/intel/adlrvp/variants/adlrvp_p/Makefile.inc +++ b/src/mainboard/intel/adlrvp/variants/adlrvp_p/Makefile.inc @@ -3,3 +3,5 @@ bootblock-y += early_gpio.c
romstage-y += memory.c + +ramstage-y += gpio.c diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb b/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb index 47a2e91..7025b76 100644 --- a/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb +++ b/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb @@ -4,6 +4,34 @@ device lapic 0 on end end
+ # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "pmc_gpe0_dw0" = "GPP_B" + register "pmc_gpe0_dw1" = "GPP_D" + register "pmc_gpe0_dw2" = "GPP_E" + + # FSP configuration + # Enable Speed Shift Technology/HWP support + register "speed_shift_enable" = "1" + + register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" # Type-C Port1 + register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" # Type-C Port2 + register "usb2_ports[2]" = "USB2_PORT_MID(OC3)" # Type-C Port3 + register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN + register "usb2_ports[4]" = "USB2_PORT_MID(OC3)" # Type-C Port4 + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # FPS connector + register "usb2_ports[6]" = "USB2_PORT_MID(OC0)" # USB3/2 Type A port1 + register "usb2_ports[7]" = "USB2_PORT_MID(OC0)" # USB3/2 Type A port2 + register "usb2_ports[8]" = "USB2_PORT_MID(OC3)" # USB3/2 Type A port3 + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WLAN + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC3)" # USB3/2 Type A port1 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port2 + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port3 + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 WWAN + # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f register "gen1_dec" = "0x00fc0801" register "gen2_dec" = "0x000c0201" @@ -41,6 +69,101 @@ # Mark LAN CLK pins as unused as GbE 0:0x1f.6 is disabled below register "PcieClkSrcUsage[6]" = "0xff"
+ register "SataSalpSupport" = "1" + + register "SataPortsEnable" = "{ + [0] = 1, + [1] = 1, + [2] = 1, + [3] = 1, + }" + + register "SataPortsDevSlp" = "{ + [0] = 1, + [1] = 1, + [2] = 1, + [3] = 1, + }" + + # Enable EDP in PortA + register "DdiPortAConfig" = "1" + register "DdiPortBConfig" = "1" + + # TCSS USB3 + register "TcssAuxOri" = "0" + + register "s0ix_enable" = "1" + + register "SerialIoI2cMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoDisabled, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + }" + + register "SerialIoGSpiMode" = "{ + [PchSerialIoIndexGSPI0] = PchSerialIoPci, + [PchSerialIoIndexGSPI1] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI2] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI3] = PchSerialIoDisabled, + }" + + register "SerialIoGSpiCsMode" = "{ + [PchSerialIoIndexGSPI0] = 0, + [PchSerialIoIndexGSPI1] = 0, + [PchSerialIoIndexGSPI2] = 0, + [PchSerialIoIndexGSPI3] = 0, + }" + + register "SerialIoGSpiCsState" = "{ + [PchSerialIoIndexGSPI0] = 0, + [PchSerialIoIndexGSPI1] = 0, + [PchSerialIoIndexGSPI2] = 0, + [PchSerialIoIndexGSPI3] = 0, + }" + + register "SerialIoUartMode" = "{ + [PchSerialIoIndexUART0] = PchSerialIoSkipInit, + [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoDisabled, + }" + + # HD Audio + register "PchHdaDspEnable" = "1" + register "PchHdaAudioLinkHdaEnable" = "0" + register "PchHdaAudioLinkDmicEnable[0]" = "1" + register "PchHdaAudioLinkDmicEnable[1]" = "1" + register "PchHdaAudioLinkSndwEnable[0]" = "1" + register "PchHdaAudioLinkSndwEnable[1]" = "1" + # iDisp-Link T-Mode 0: 2T, 2: 4T, 3: 8T, 4: 16T + register "PchHdaIDispLinkTmode" = "2" + # iDisp-Link Freq 4: 96MHz, 3: 48MHz. + register "PchHdaIDispLinkFrequency" = "4" + # Not disconnected/enumerable + register "PchHdaIDispCodecDisconnect" = "0" + + # Intel Common SoC Config + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + }, + }" + device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Graphics @@ -107,7 +230,7 @@ device pci 17.0 on end # SATA device pci 19.0 off end # I2C4 device pci 19.1 on end # I2C5 - device pci 19.2 on end # UART2 + device pci 19.2 off end # UART2 device pci 1c.0 on end # RP1 device pci 1c.1 off end # RP2 device pci 1c.2 off end # RP3 @@ -120,9 +243,9 @@ device pci 1d.1 off end # RP10 device pci 1d.2 off end # RP11 device pci 1d.3 off end # RP12 - device pci 1e.0 off end # UART0 + device pci 1e.0 on end # UART0 device pci 1e.1 off end # UART1 - device pci 1e.2 off end # GSPI0 + device pci 1e.2 on end # GSPI0 device pci 1e.3 off end # GSPI1 device pci 1f.0 on end # eSPI device pci 1f.1 on end # P2SB diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p/gpio.c b/src/mainboard/intel/adlrvp/variants/adlrvp_p/gpio.c new file mode 100644 index 0000000..5a21992 --- /dev/null +++ b/src/mainboard/intel/adlrvp/variants/adlrvp_p/gpio.c @@ -0,0 +1,297 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <commonlib/helpers.h> + +/* Pad configuration in ramstage*/ +static const struct pad_config gpio_table[] = { + /* SSD1_PWREN CPU SSD1 */ + PAD_CFG_GPO(GPP_D14, 1, PLTRST), + /* SSD1_RESET CPU SSD1 */ + PAD_CFG_GPO(GPP_F20, 1, PLTRST), + /* BT_RF_KILL_N */ + PAD_CFG_GPO(GPP_A13, 1, PLTRST), + /* WLAN RST# */ + PAD_CFG_GPO(GPP_H2, 1, PLTRST), + /* WIFI_WAKE_N */ + PAD_CFG_GPI_IRQ_WAKE(GPP_D13, NONE, DEEP, LEVEL, INVERT), + /* x4 PCIE slot1 PWREN */ + PAD_CFG_GPO(GPP_H17, 0, PLTRST), + /* x4 PCIE slot 1 RESET */ + PAD_CFG_GPO(GPP_F10, 1, PLTRST), + /* Retimer Force Power */ + PAD_CFG_GPO(GPP_E4, 0, PLTRST), + /* PEG Slot RST# */ + PAD_CFG_GPO(GPP_B2, 1, PLTRST), + /* M.2 SSD_2 Reset */ + PAD_CFG_GPO(GPP_H0, 1, PLTRST), + /* CAM1-IRQ */ + PAD_CFG_GPO(GPP_B23, 1, PLTRST), + /* CAM_STROBE */ + PAD_CFG_GPO(GPP_B18, 0, PLTRST), + /* Audio Codec INT N */ + PAD_CFG_GPI_APIC(GPP_H3, NONE, PLTRST, LEVEL, INVERT), + /* TCH PAD Power EN */ + PAD_CFG_GPO(GPP_F7, 1, PLTRST), + /* THC1 SPI2 RST# */ + PAD_CFG_GPO(GPP_F17, 1, PLTRST), + /* THC1_SPI2_INTB */ + PAD_CFG_GPI_APIC(GPP_F18, NONE, PLTRST, EDGE_SINGLE, INVERT), + /* THC1_SPI2_INTB */ + PAD_CFG_GPI(GPP_E17, NONE, PLTRST), + /* EC_SMI_N */ + PAD_CFG_GPI_SMI(GPP_E7, NONE, PLTRST, EDGE_SINGLE, NONE), + /* EC_SLP_S0_CS_N */ + PAD_CFG_GPO(GPP_F9, 1, PLTRST), + /* WIFI RF KILL */ + PAD_CFG_GPO(GPP_E3, 1, PLTRST), + /* DISP_AUX_N_BIAS_GPIO */ + PAD_CFG_GPO(GPP_E23, 1, PLTRST), + /* WWAN WAKE N*/ + PAD_CFG_GPI_IRQ_WAKE(GPP_D18, NONE, DEEP, LEVEL, INVERT), + /* WWAN_DISABLE_N */ + PAD_CFG_GPO(GPP_D15, 1, PLTRST), + /* WWAN_RST# */ + PAD_CFG_GPO(GPP_E10, 1, PLTRST), + /* WWAN_PWR_EN */ + PAD_CFG_GPO(GPP_E13, 1, DEEP), + /* WWAN_PERST# */ + PAD_CFG_GPO(GPP_C5, 1, PLTRST), + /* PEG_SLOT_WAKE_N */ + PAD_CFG_GPI(GPP_A20, NONE, PLTRST), + /* UART_BT_WAKE_N */ + PAD_CFG_GPI_IRQ_WAKE(GPP_E0, NONE, DEEP, LEVEL, INVERT), + /* CAM CONN1 CLKEN */ + PAD_CFG_GPO(GPP_H15, 1, PLTRST), + /* CPU SSD2 PWREN */ + PAD_CFG_GPO(GPP_C2, 1, PLTRST), + /* CPU SSD2 RST# */ + PAD_CFG_GPO(GPP_H1, 1, PLTRST), + /* Sata direct Power */ + PAD_CFG_GPO(GPP_B4, 1, PLTRST), + + /* THC0 SPI1 CLK */ + PAD_CFG_NF(GPP_E11, NONE, DEEP, NF2), + /* THC0 SPI1 IO 1 */ + PAD_CFG_NF(GPP_E12, NONE, DEEP, NF2), + /* THC0 SPI1 IO 2 */ + PAD_CFG_NF(GPP_E1, NONE, DEEP, NF2), + /* THC0 SPI IO 3 */ + PAD_CFG_NF(GPP_E2, NONE, DEEP, NF2), + /* THC1 SPI1 RSTB */ + PAD_CFG_NF(GPP_E6, NONE, DEEP, NF2), + /* UART_RX(1) */ + PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), + /* UART_RX(2) */ + PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), + /* UART_RX(4) */ + PAD_CFG_NF(GPP_T4, NONE, DEEP, NF1), + /* UART_RX(5) */ + PAD_CFG_NF(GPP_T8, NONE, DEEP, NF1), + /* UART_RX(6) */ + PAD_CFG_NF(GPP_T12, NONE, DEEP, NF1), + + /* UART_TX(1) */ + PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), + /* UART_TX(2) */ + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), + /* UART_TX(4) */ + PAD_CFG_NF(GPP_T5, NONE, DEEP, NF1), + /* UART_TX(5) */ + PAD_CFG_NF(GPP_T9, NONE, DEEP, NF1), + /* UART_TX(6) */ + PAD_CFG_NF(GPP_T13, NONE, DEEP, NF1), + + /* UART_RTS(1) */ + PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1), + /* UART_RTS(2) */ + PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1), + /* UART_RTS(4) */ + PAD_CFG_NF(GPP_T6, NONE, DEEP, NF1), + /* UART_RTS(5) */ + PAD_CFG_NF(GPP_T10, NONE, DEEP, NF1), + /* UART_RTS(6) */ + PAD_CFG_NF(GPP_T14, NONE, DEEP, NF1), + + /* UART_CTS(1) */ + PAD_CFG_NF(GPP_C15, NONE, DEEP, NF1), + /* UART_CTS(2) */ + PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1), + /* UART_CTS(4) */ + PAD_CFG_NF(GPP_T7, NONE, DEEP, NF1), + /* UART_CTS(5) */ + PAD_CFG_NF(GPP_T11, NONE, DEEP, NF1), + /* UART_CTS(6) */ + PAD_CFG_NF(GPP_T15, NONE, DEEP, NF1), + + /* SPI_MOSI(1) */ + PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1), + /* SPI_MOSI(2) */ + PAD_CFG_NF(GPP_D12, NONE, DEEP, NF2), + + /* SPI_MIS0(0) */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), + /* SPI_MIS0(1) */ + PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1), + /* SPI_MIS0(2) */ + PAD_CFG_NF(GPP_D11, NONE, DEEP, NF2), + + /* SPI_CLK(0) */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), + /* SPI_CLK(1) */ + PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1), + /* SPI_CLK(2) */ + PAD_CFG_NF(GPP_D10, NONE, DEEP, NF2), + + /* SPI_CS(0, 0) */ + PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), + /* SPI_CS(0, 1) */ + PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), + /* SPI_CS(1, 0) */ + PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1), + /* SPI_CS(2, 0) */ + PAD_CFG_NF(GPP_D9, NONE, DEEP, NF2), + + /* I2C_SCL(0) */ + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), + /* I2C_SCL(1) */ + PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), + /* I2C_SCL(2) */ + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), + /* I2C_SCL(3) */ + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), + /* I2C_SCL(5) */ + PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), + /* I2C_SCL(6) */ + PAD_CFG_NF(GPP_T1, NONE, DEEP, NF1), + /* I2C_SCL(7) */ + PAD_CFG_NF(GPP_T3, NONE, DEEP, NF1), + + /* I2C_SDA(0) */ + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), + /* I2C_SDA(1) */ + PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), + /* I2C_SDA(2) */ + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), + /* I2C_SDA(3) */ + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), + /* I2C_SDA(5) */ + PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), + /* I2C_SDA(6) */ + PAD_CFG_NF(GPP_T0, NONE, DEEP, NF1), + /* I2C_SDA(7) */ + PAD_CFG_NF(GPP_T2, NONE, DEEP, NF1), + + /* I2S0_SCLK */ + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), + /* I2S0_SFRM */ + PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), + /* I2S0_TXD */ + PAD_CFG_NF(GPP_R2, NONE, DEEP, NF2), + /* I2S0_RXD */ + PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), + + /* I2S1_SCLK */ + PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1), + /* I2S1_SFRM */ + PAD_CFG_NF(GPP_R5, NONE, DEEP, NF2), + /* I2S1_TXD */ + PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2), + /* I2S1_RXD */ + PAD_CFG_NF(GPP_R7, NONE, DEEP, NF2), + + /* I2S2_SCLK */ + PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), + /* I2S2_SFRM */ + PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), + /* I2S2_TXD */ + PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), + /* I2S2_RXD */ + PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), + + /* I2S_MCLK1_OUT */ + PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), + /* I2S_MCLK2_INOUT */ + PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), + + /* SNDW1_CLK */ + PAD_CFG_NF(GPP_S0, NONE, DEEP, NF1), + /* SNDW1_DATA */ + PAD_CFG_NF(GPP_S1, NONE, DEEP, NF1), + /* SNDW2_CLK */ + PAD_CFG_NF(GPP_S2, NONE, DEEP, NF1), + /* SNDW2_DATA */ + PAD_CFG_NF(GPP_S3, NONE, DEEP, NF1), + /* SNDW3_CLK */ + PAD_CFG_NF(GPP_S4, NONE, DEEP, NF1), + /* SNDW3_DATA */ + PAD_CFG_NF(GPP_S5, NONE, DEEP, NF1), + /* SNDW4_CLK */ + PAD_CFG_NF(GPP_S6, NONE, DEEP, NF1), + /* SNDW4_DATA */ + PAD_CFG_NF(GPP_S7, NONE, DEEP, NF1), + + /* SMB_CLK */ + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), + /* SMB_DATA */ + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), + + /* SATADevSlpPin to GPIO pin mapping */ + PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), + /* SATA DIRECT DEVSLP*/ + PAD_CFG_NF(GPP_H12, NONE, DEEP, NF5), + + /* SATA LED pin */ + PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), + + /* USB2 OC0 pins */ + PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), + /* USB2 OC1 pins */ + PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), + /* USB2 OC2 pins */ + PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), + /* USB2 OC3 pins */ + PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), + + /* GPIO pin for PCIE SRCCLKREQB */ + PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), + + /* DDP1/2/3/4/A/B/C CTRLCLK and CTRLDATA pins */ + PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E22, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A21, NONE, DEEP, NF2), + PAD_CFG_NF(GPP_A22, NONE, DEEP, NF2), + + /* IMGCLKOUT */ + PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H23, NONE, DEEP, NF1), +}; + +void variant_configure_gpio_pads(void) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), +}; + +const struct cros_gpio *variant_cros_gpios(size_t *num) +{ + *num = ARRAY_SIZE(cros_gpios); + return cros_gpios; +} diff --git a/src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/ec.h b/src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/ec.h new file mode 100644 index 0000000..4303faf --- /dev/null +++ b/src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/ec.h @@ -0,0 +1,73 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __BASEBOARD_EC_H__ +#define __BASEBOARD_EC_H__ + +#include <ec/ec.h> +#include <ec/google/chromeec/ec_commands.h> +#include <baseboard/gpio.h> + +#define MAINBOARD_EC_SCI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_MUX)) + +#define MAINBOARD_EC_SMI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)) + +/* EC can wake from S5 with lid or power button */ +#define MAINBOARD_EC_S5_WAKE_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) + +/* + * EC can wake from S3 with lid or power button or key press or + * mode change event. + */ +#define MAINBOARD_EC_S3_WAKE_EVENTS \ + (MAINBOARD_EC_S5_WAKE_EVENTS |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)) + +#define MAINBOARD_EC_S0IX_WAKE_EVENTS (MAINBOARD_EC_S3_WAKE_EVENTS) + +/* Log EC wake events plus EC shutdown events */ +#define MAINBOARD_EC_LOG_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC)) + +/* + * ACPI related definitions for ASL code. + */ + +/* Enable EC backed ALS device in ACPI */ +#define EC_ENABLE_ALS_DEVICE + +/* Enable EC sync interrupt, EC_SYNC_IRQ is defined in baseboard/gpio.h */ +#define EC_ENABLE_SYNC_IRQ + +/* Enable EC backed PD MCU device in ACPI */ +#define EC_ENABLE_PD_MCU_DEVICE + +/* Enable LID switch and provide wake pin for EC */ +#define EC_ENABLE_LID_SWITCH +#define EC_ENABLE_WAKE_PIN GPE_EC_WAKE + +#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */ +#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */ +#define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */ + +#endif /* __BASEBOARD_EC_H__ */ diff --git a/src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/variants.h index 5288b6f..005ec83 100644 --- a/src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/variants.h @@ -20,7 +20,8 @@ /* The next set of functions return the gpio table and fill in the number of * entries for each table. */ const struct cros_gpio *variant_cros_gpios(size_t *num); - +/* Functions to configure GPIO as per variant schematics */ +void variant_configure_gpio_pads(void); void variant_configure_early_gpio_pads(void);
size_t variant_memory_sku(void);
-
Angel Pons (Code Review) -
Patrick Georgi (Code Review)
-
Paul Menzel (Code Review)
-
Subrata Banik (Code Review)
-
Tim Wawrzynczak (Code Review)