1 comment:
File src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb:
Patch Set #5, Line 91: s0ix_enable
So, if I understood correctly, `s0ix_enable = 0` would also disable C-states?
So most differentiation is here to have S0ix we first need to ensure C10 is hitting hence need to publish the lowest C-state capability as well
https://github.com/coreboot/coreboot/blob/master/src/soc/intel/alderlake/acpi.c#L137
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