Subrata Banik has uploaded this change for review.
mb/intel/adlrvp: Add ADL-P ramstage mainboard code
List of changes:
1. Add devicetree.cb config parameters related to FSP-S UPD
2. Configure GPIO as per ADL-P RVP
3. Add files required for Ramstage (ec.c, mainboard.c)
4. Add smihandler.c for SMM
TEST=Able to reach till payload
Change-Id: I120885956c88babfa09d24ce1079d49306919b8a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
---
M src/mainboard/intel/adlrvp/Makefile.inc
A src/mainboard/intel/adlrvp/ec.c
A src/mainboard/intel/adlrvp/mainboard.c
A src/mainboard/intel/adlrvp/smihandler.c
M src/mainboard/intel/adlrvp/variants/adlrvp_p/Makefile.inc
M src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb
A src/mainboard/intel/adlrvp/variants/adlrvp_p/gpio.c
A src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/ec.h
M src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/variants.h
9 files changed, 581 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/46265/1
diff --git a/src/mainboard/intel/adlrvp/Makefile.inc b/src/mainboard/intel/adlrvp/Makefile.inc
index e8a0eca..2ca32f3 100644
--- a/src/mainboard/intel/adlrvp/Makefile.inc
+++ b/src/mainboard/intel/adlrvp/Makefile.inc
@@ -11,7 +11,12 @@
romstage-y += romstage_fsp_params.c
romstage-y += board_id.c
+smm-y += smihandler.c
+
ramstage-$(CONFIG_CHROMEOS) += chromeos.c
+ramstage-y += ec.c
+ramstage-y += mainboard.c
+ramstage-y += board_id.c
subdirs-y += variants/baseboard
CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include
diff --git a/src/mainboard/intel/adlrvp/ec.c b/src/mainboard/intel/adlrvp/ec.c
new file mode 100644
index 0000000..14760017
--- /dev/null
+++ b/src/mainboard/intel/adlrvp/ec.c
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi.h>
+#include <ec/ec.h>
+#include <ec/google/chromeec/ec.h>
+#include <baseboard/ec.h>
+
+void mainboard_ec_init(void)
+{
+ const struct google_chromeec_event_info info = {
+ .log_events = MAINBOARD_EC_LOG_EVENTS,
+ .sci_events = MAINBOARD_EC_SCI_EVENTS,
+ .s3_wake_events = MAINBOARD_EC_S3_WAKE_EVENTS,
+ .s5_wake_events = MAINBOARD_EC_S5_WAKE_EVENTS,
+ .s0ix_wake_events = MAINBOARD_EC_S0IX_WAKE_EVENTS,
+ };
+
+ google_chromeec_events_init(&info, acpi_is_wakeup_s3());
+}
diff --git a/src/mainboard/intel/adlrvp/mainboard.c b/src/mainboard/intel/adlrvp/mainboard.c
new file mode 100644
index 0000000..d9458cd
--- /dev/null
+++ b/src/mainboard/intel/adlrvp/mainboard.c
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <device/device.h>
+#include <ec/ec.h>
+#include <soc/gpio.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+#include <smbios.h>
+#include <string.h>
+
+const char *smbios_system_sku(void)
+{
+ static char sku_str[7] = ""; /* sku{0..255} */
+ uint32_t sku_id = 255;
+
+ snprintf(sku_str, sizeof(sku_str), "sku%u", sku_id);
+ return sku_str;
+}
+
+static void mainboard_init(void *chip_info)
+{
+ variant_configure_gpio_pads();
+
+ if (CONFIG(EC_GOOGLE_CHROMEEC))
+ mainboard_ec_init();
+}
+
+static void mainboard_enable(struct device *dev)
+{
+ dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator;
+}
+
+struct chip_operations mainboard_ops = {
+ .init = mainboard_init,
+ .enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/intel/adlrvp/smihandler.c b/src/mainboard/intel/adlrvp/smihandler.c
new file mode 100644
index 0000000..a3b4323
--- /dev/null
+++ b/src/mainboard/intel/adlrvp/smihandler.c
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <cpu/x86/smm.h>
+#include <ec/google/chromeec/smm.h>
+#include <intelblocks/smihandler.h>
+#include <baseboard/ec.h>
+
+void mainboard_smi_espi_handler(void)
+{
+ if (!CONFIG(EC_GOOGLE_CHROMEEC))
+ return;
+
+ chromeec_smi_process_events();
+}
+
+void mainboard_smi_sleep(u8 slp_typ)
+{
+ if (!CONFIG(EC_GOOGLE_CHROMEEC))
+ return;
+
+ chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS, MAINBOARD_EC_S5_WAKE_EVENTS);
+}
+
+int mainboard_smi_apmc(u8 apmc)
+{
+ if (CONFIG(EC_GOOGLE_CHROMEEC))
+ chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS, MAINBOARD_EC_SMI_EVENTS);
+
+ return 0;
+}
diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p/Makefile.inc b/src/mainboard/intel/adlrvp/variants/adlrvp_p/Makefile.inc
index 8c05721..513963e 100644
--- a/src/mainboard/intel/adlrvp/variants/adlrvp_p/Makefile.inc
+++ b/src/mainboard/intel/adlrvp/variants/adlrvp_p/Makefile.inc
@@ -3,3 +3,5 @@
bootblock-y += early_gpio.c
romstage-y += memory.c
+
+ramstage-y += gpio.c
diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb b/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb
index a6b0039..3484713 100644
--- a/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb
+++ b/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb
@@ -4,6 +4,34 @@
device lapic 0 on end
end
+ # GPE configuration
+ # Note that GPE events called out in ASL code rely on this
+ # route. i.e. If this route changes then the affected GPE
+ # offset bits also need to be changed.
+ register "pmc_gpe0_dw0" = "GPP_B"
+ register "pmc_gpe0_dw1" = "GPP_D"
+ register "pmc_gpe0_dw2" = "GPP_E"
+
+ # FSP configuration
+ # Enable Speed Shift Technology/HWP support
+ register "speed_shift_enable" = "1"
+
+ register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" # Type C port - various configurations – TCP0
+ register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" # Type C port - various configurations – TCP1
+ register "usb2_ports[2]" = "USB2_PORT_MID(OC3)" # Type C port - various configurations – TCP2
+ register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # WWAN M.2 Module / USB2.0 Type-A Port-1
+ register "usb2_ports[4]" = "USB2_PORT_MID(OC3)" # Type C port - various configurations – TCP3
+ register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # FPS connector/USB2.0 Type-A Port-1
+ register "usb2_ports[6]" = "USB2_PORT_MID(OC0)" # USB3.2 Gen2x1 Type-A Port - TAP2
+ register "usb2_ports[7]" = "USB2_PORT_MID(OC0)" # USB3.2 Gen2x1 Type-A Vertical Port – TAP3
+ register "usb2_ports[8]" = "USB2_PORT_MID(OC3)" # USB3.2 Gen2x1 Type-A Port - TAP1
+ register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # WLAN M.2 Module/BT
+
+ register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC3)" # USB3.2 Gen2x1 Type-A Port - TAP1
+ register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # USB3.2 Gen2x1 Type-A Port - TAP2
+ register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)" # USB3.2 Gen2x1 Type-A Vertical Port - TAP3
+ register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # WWAN M.2 Module
+
# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
register "gen1_dec" = "0x00fc0801"
register "gen2_dec" = "0x000c0201"
@@ -41,6 +69,94 @@
# Mark LAN CLK pins as unused as GbE 0:0x1f.6 is disabled below
register "PcieClkSrcUsage[6]" = "0xff"
+ register "SataSalpSupport" = "1"
+
+ register "SataPortsEnable[0]" = "1"
+ register "SataPortsEnable[1]" = "1"
+ register "SataPortsEnable[2]" = "1"
+ register "SataPortsEnable[3]" = "1"
+
+ register "SataPortsDevSlp[0]" = "1"
+ register "SataPortsDevSlp[1]" = "1"
+ register "SataPortsDevSlp[2]" = "1"
+ register "SataPortsDevSlp[3]" = "1"
+
+ # Enable EDP in PortA
+ register "DdiPortAConfig" = "1"
+ register "DdiPortBConfig" = "1"
+
+ # TCSS USB3
+ register "TcssAuxOri" = "0"
+
+ register "s0ix_enable" = "1"
+
+ register "SerialIoI2cMode" = "{
+ [PchSerialIoIndexI2C0] = PchSerialIoPci,
+ [PchSerialIoIndexI2C1] = PchSerialIoPci,
+ [PchSerialIoIndexI2C2] = PchSerialIoPci,
+ [PchSerialIoIndexI2C3] = PchSerialIoPci,
+ [PchSerialIoIndexI2C4] = PchSerialIoDisabled,
+ [PchSerialIoIndexI2C5] = PchSerialIoPci,
+ }"
+
+ register "SerialIoGSpiMode" = "{
+ [PchSerialIoIndexGSPI0] = PchSerialIoDisabled,
+ [PchSerialIoIndexGSPI1] = PchSerialIoPci,
+ [PchSerialIoIndexGSPI2] = PchSerialIoDisabled,
+ }"
+
+ register "SerialIoGSpiCsMode" = "{
+ [PchSerialIoIndexGSPI0] = 0,
+ [PchSerialIoIndexGSPI1] = 0,
+ [PchSerialIoIndexGSPI2] = 0,
+ }"
+
+ register "SerialIoGSpiCsState" = "{
+ [PchSerialIoIndexGSPI0] = 0,
+ [PchSerialIoIndexGSPI1] = 0,
+ [PchSerialIoIndexGSPI2] = 0,
+ }"
+
+ register "SerialIoUartMode" = "{
+ [PchSerialIoIndexUART0] = PchSerialIoDisabled,
+ [PchSerialIoIndexUART1] = PchSerialIoDisabled,
+ [PchSerialIoIndexUART2] = PchSerialIoSkipInit,
+ }"
+
+ # HD Audio
+ register "PchHdaDspEnable" = "1"
+ register "PchHdaAudioLinkHdaEnable" = "0"
+ register "PchHdaAudioLinkDmicEnable[0]" = "1"
+ register "PchHdaAudioLinkDmicEnable[1]" = "1"
+ register "PchHdaAudioLinkSndwEnable[0]" = "1"
+ register "PchHdaAudioLinkSndwEnable[1]" = "1"
+ # iDisp-Link T-Mode 0: 2T, 2: 4T, 3: 8T, 4: 16T
+ register "PchHdaIDispLinkTmode" = "2"
+ # iDisp-Link Freq 4: 96MHz, 3: 48MHz.
+ register "PchHdaIDispLinkFrequency" = "4"
+ # Not disconnected/enumerable
+ register "PchHdaIDispCodecDisconnect" = "0"
+
+ # Intel Common SoC Config
+ register "common_soc_config" = "{
+ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
+ .i2c[0] = {
+ .speed = I2C_SPEED_FAST,
+ },
+ .i2c[1] = {
+ .speed = I2C_SPEED_FAST,
+ },
+ .i2c[2] = {
+ .speed = I2C_SPEED_FAST,
+ },
+ .i2c[3] = {
+ .speed = I2C_SPEED_FAST,
+ },
+ .i2c[5] = {
+ .speed = I2C_SPEED_FAST,
+ },
+ }"
+
device domain 0 on
device pci 00.0 on end # Host Bridge
device pci 02.0 on end # Graphics
diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p/gpio.c b/src/mainboard/intel/adlrvp/variants/adlrvp_p/gpio.c
new file mode 100644
index 0000000..f06e70e
--- /dev/null
+++ b/src/mainboard/intel/adlrvp/variants/adlrvp_p/gpio.c
@@ -0,0 +1,297 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <commonlib/helpers.h>
+
+/* Pad configuration in ramstage*/
+static const struct pad_config gpio_table[] = {
+ /* SSD1_PWREN CPU SSD1 */
+ PAD_CFG_GPO(GPP_D14, 1, PLTRST),
+ /* SSD1_RESET CPU SSD1 */
+ PAD_CFG_GPO(GPP_F20, 1, PLTRST),
+ /* BT_RF_KILL_N */
+ PAD_CFG_GPO(GPP_A13, 1, PLTRST),
+ /* WLAN RST# */
+ PAD_CFG_GPO(GPP_H2, 1, PLTRST),
+ /* WIFI_WAKE_N */
+ PAD_CFG_GPI_IRQ_WAKE(GPP_D13, NONE, DEEP, LEVEL, INVERT),
+ /* x4 PCIE slot1 PWREN */
+ PAD_CFG_GPO(GPP_H17, 0, PLTRST),
+ /* x4 PCIE slot 1 RESET */
+ PAD_CFG_GPO(GPP_F10, 1, PLTRST),
+ /* Retimer Force Power */
+ PAD_CFG_GPO(GPP_E4, 0, PLTRST),
+ /* PEG Slot RST# */
+ PAD_CFG_GPO(GPP_B2, 1, PLTRST),
+ /* M.2 SSD_2 Reset */
+ PAD_CFG_GPO(GPP_H0, 1, PLTRST),
+ /* CAM1-IRQ */
+ PAD_CFG_GPO(GPP_B23, 1, PLTRST),
+ /* CAM_STROBE */
+ PAD_CFG_GPO(GPP_B18, 0, PLTRST),
+ /* Audio Codec INT N */
+ PAD_CFG_GPI_APIC(GPP_H3, NONE, PLTRST, LEVEL, INVERT),
+ /* TCH PAD Power EN */
+ PAD_CFG_GPO(GPP_F7, 1, PLTRST),
+ /* THC1 SPI2 RST# */
+ PAD_CFG_GPO(GPP_F17, 1, PLTRST),
+ /* THC1_SPI2_INTB */
+ PAD_CFG_GPI_APIC(GPP_F18, NONE, PLTRST, EDGE_SINGLE, INVERT),
+ /* THC1_SPI2_INTB */
+ PAD_CFG_GPI(GPP_E17, NONE, PLTRST),
+ /* EC_SMI_N */
+ PAD_CFG_GPI_SMI_LOW(GPP_E7, NONE, PLTRST, LEVEL),
+ /* EC_SLP_S0_CS_N */
+ PAD_CFG_GPO(GPP_F9, 1, PLTRST),
+ /* WIFI RF KILL */
+ PAD_CFG_GPO(GPP_E3, 1, PLTRST),
+ /* DISP_AUX_N_BIAS_GPIO */
+ PAD_CFG_GPO(GPP_E23, 1, PLTRST),
+ /* WWAN WAKE N*/
+ PAD_CFG_GPI_IRQ_WAKE(GPP_D18, NONE, DEEP, LEVEL, INVERT),
+ /* WWAN_DISABLE_N */
+ PAD_CFG_GPO(GPP_D15, 1, PLTRST),
+ /* WWAN_RST# */
+ PAD_CFG_GPO(GPP_E10, 1, PLTRST),
+ /* WWAN_PWR_EN */
+ PAD_CFG_GPO(GPP_E13, 1, DEEP),
+ /* WWAN_PERST# */
+ PAD_CFG_GPO(GPP_C5, 1, PLTRST),
+ /* PEG_SLOT_WAKE_N */
+ PAD_CFG_GPI(GPP_A20, NONE, PLTRST),
+ /* UART_BT_WAKE_N */
+ PAD_CFG_GPI_IRQ_WAKE(GPP_E0, NONE, DEEP, LEVEL, INVERT),
+ /* CAM CONN1 CLKEN */
+ PAD_CFG_GPO(GPP_H15, 1, PLTRST),
+ /* CPU SSD2 PWREN */
+ PAD_CFG_GPO(GPP_C2, 1, PLTRST),
+ /* CPU SSD2 RST# */
+ PAD_CFG_GPO(GPP_H1, 1, PLTRST),
+ /* Sata direct Power */
+ PAD_CFG_GPO(GPP_B4, 1, PLTRST),
+
+ /* THC0 SPI1 CLK */
+ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF2),
+ /* THC0 SPI1 IO 1 */
+ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF2),
+ /* THC0 SPI1 IO 2 */
+ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF2),
+ /* THC0 SPI IO 3 */
+ PAD_CFG_NF(GPP_E2, NONE, DEEP, NF2),
+ /* THC1 SPI1 RSTB */
+ PAD_CFG_NF(GPP_E6, NONE, DEEP, NF2),
+ /* UART_RX(1) */
+ PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1),
+ /* UART_RX(2) */
+ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
+ /* UART_RX(4) */
+ PAD_CFG_NF(GPP_T4, NONE, DEEP, NF1),
+ /* UART_RX(5) */
+ PAD_CFG_NF(GPP_T8, NONE, DEEP, NF1),
+ /* UART_RX(6) */
+ PAD_CFG_NF(GPP_T12, NONE, DEEP, NF1),
+
+ /* UART_TX(1) */
+ PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1),
+ /* UART_TX(2) */
+ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
+ /* UART_TX(4) */
+ PAD_CFG_NF(GPP_T5, NONE, DEEP, NF1),
+ /* UART_TX(5) */
+ PAD_CFG_NF(GPP_T9, NONE, DEEP, NF1),
+ /* UART_TX(6) */
+ PAD_CFG_NF(GPP_T13, NONE, DEEP, NF1),
+
+ /* UART_RTS(1) */
+ PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1),
+ /* UART_RTS(2) */
+ PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1),
+ /* UART_RTS(4) */
+ PAD_CFG_NF(GPP_T6, NONE, DEEP, NF1),
+ /* UART_RTS(5) */
+ PAD_CFG_NF(GPP_T10, NONE, DEEP, NF1),
+ /* UART_RTS(6) */
+ PAD_CFG_NF(GPP_T14, NONE, DEEP, NF1),
+
+ /* UART_CTS(1) */
+ PAD_CFG_NF(GPP_C15, NONE, DEEP, NF1),
+ /* UART_CTS(2) */
+ PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1),
+ /* UART_CTS(4) */
+ PAD_CFG_NF(GPP_T7, NONE, DEEP, NF1),
+ /* UART_CTS(5) */
+ PAD_CFG_NF(GPP_T11, NONE, DEEP, NF1),
+ /* UART_CTS(6) */
+ PAD_CFG_NF(GPP_T15, NONE, DEEP, NF1),
+
+ /* SPI_MOSI(1) */
+ PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1),
+ /* SPI_MOSI(2) */
+ PAD_CFG_NF(GPP_D12, NONE, DEEP, NF2),
+
+ /* SPI_MIS0(0) */
+ PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),
+ /* SPI_MIS0(1) */
+ PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1),
+ /* SPI_MIS0(2) */
+ PAD_CFG_NF(GPP_D11, NONE, DEEP, NF2),
+
+ /* SPI_CLK(0) */
+ PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1),
+ /* SPI_CLK(1) */
+ PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1),
+ /* SPI_CLK(2) */
+ PAD_CFG_NF(GPP_D10, NONE, DEEP, NF2),
+
+ /* SPI_CS(0, 0) */
+ PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),
+ /* SPI_CS(0, 1) */
+ PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1),
+ /* SPI_CS(1, 0) */
+ PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1),
+ /* SPI_CS(2, 0) */
+ PAD_CFG_NF(GPP_D9, NONE, DEEP, NF2),
+
+ /* I2C_SCL(0) */
+ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
+ /* I2C_SCL(1) */
+ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
+ /* I2C_SCL(2) */
+ PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
+ /* I2C_SCL(3) */
+ PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
+ /* I2C_SCL(5) */
+ PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1),
+ /* I2C_SCL(6) */
+ PAD_CFG_NF(GPP_T1, NONE, DEEP, NF1),
+ /* I2C_SCL(7) */
+ PAD_CFG_NF(GPP_T3, NONE, DEEP, NF1),
+
+ /* I2C_SDA(0) */
+ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
+ /* I2C_SDA(1) */
+ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
+ /* I2C_SDA(2) */
+ PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
+ /* I2C_SDA(3) */
+ PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
+ /* I2C_SDA(5) */
+ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),
+ /* I2C_SDA(6) */
+ PAD_CFG_NF(GPP_T0, NONE, DEEP, NF1),
+ /* I2C_SDA(7) */
+ PAD_CFG_NF(GPP_T2, NONE, DEEP, NF1),
+
+ /* I2S0_SCLK */
+ PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2),
+ /* I2S0_SFRM */
+ PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2),
+ /* I2S0_TXD */
+ PAD_CFG_NF(GPP_R2, NONE, DEEP, NF2),
+ /* I2S0_RXD */
+ PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2),
+
+ /* I2S1_SCLK */
+ PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1),
+ /* I2S1_SFRM */
+ PAD_CFG_NF(GPP_R5, NONE, DEEP, NF2),
+ /* I2S1_TXD */
+ PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2),
+ /* I2S1_RXD */
+ PAD_CFG_NF(GPP_R7, NONE, DEEP, NF2),
+
+ /* I2S2_SCLK */
+ PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1),
+ /* I2S2_SFRM */
+ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
+ /* I2S2_TXD */
+ PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1),
+ /* I2S2_RXD */
+ PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1),
+
+ /* I2S_MCLK1_OUT */
+ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
+ /* I2S_MCLK2_INOUT */
+ PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1),
+
+ /* SNDW1_CLK */
+ PAD_CFG_NF(GPP_S0, NONE, DEEP, NF1),
+ /* SNDW1_DATA */
+ PAD_CFG_NF(GPP_S1, NONE, DEEP, NF1),
+ /* SNDW2_CLK */
+ PAD_CFG_NF(GPP_S2, NONE, DEEP, NF1),
+ /* SNDW2_DATA */
+ PAD_CFG_NF(GPP_S3, NONE, DEEP, NF1),
+ /* SNDW3_CLK */
+ PAD_CFG_NF(GPP_S4, NONE, DEEP, NF1),
+ /* SNDW3_DATA */
+ PAD_CFG_NF(GPP_S5, NONE, DEEP, NF1),
+ /* SNDW4_CLK */
+ PAD_CFG_NF(GPP_S6, NONE, DEEP, NF1),
+ /* SNDW4_DATA */
+ PAD_CFG_NF(GPP_S7, NONE, DEEP, NF1),
+
+ /* SMB_CLK */
+ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
+ /* SMB_DATA */
+ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
+
+ /* SATADevSlpPin to GPIO pin mapping */
+ PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1),
+ /* SATA DIRECT DEVSLP*/
+ PAD_CFG_NF(GPP_H12, NONE, DEEP, NF5),
+
+ /* SATA LED pin */
+ PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1),
+
+ /* USB2 OC0 pins */
+ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
+ /* USB2 OC1 pins */
+ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),
+ /* USB2 OC2 pins */
+ PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1),
+ /* USB2 OC3 pins */
+ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
+
+ /* GPIO pin for PCIE SRCCLKREQB */
+ PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
+
+ /* DDP1/2/3/4/A/B/C CTRLCLK and CTRLDATA pins */
+ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_E22, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_A21, NONE, DEEP, NF2),
+ PAD_CFG_NF(GPP_A22, NONE, DEEP, NF2),
+
+ /* IMGCLKOUT */
+ PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_H23, NONE, DEEP, NF1),
+};
+
+void variant_configure_gpio_pads(void)
+{
+ gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+}
+
+static const struct cros_gpio cros_gpios[] = {
+ CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
+};
+
+const struct cros_gpio *variant_cros_gpios(size_t *num)
+{
+ *num = ARRAY_SIZE(cros_gpios);
+ return cros_gpios;
+}
diff --git a/src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/ec.h b/src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/ec.h
new file mode 100644
index 0000000..4303faf
--- /dev/null
+++ b/src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/ec.h
@@ -0,0 +1,73 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __BASEBOARD_EC_H__
+#define __BASEBOARD_EC_H__
+
+#include <ec/ec.h>
+#include <ec/google/chromeec/ec_commands.h>
+#include <baseboard/gpio.h>
+
+#define MAINBOARD_EC_SCI_EVENTS \
+ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_MUX))
+
+#define MAINBOARD_EC_SMI_EVENTS \
+ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED))
+
+/* EC can wake from S5 with lid or power button */
+#define MAINBOARD_EC_S5_WAKE_EVENTS \
+ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
+
+/*
+ * EC can wake from S3 with lid or power button or key press or
+ * mode change event.
+ */
+#define MAINBOARD_EC_S3_WAKE_EVENTS \
+ (MAINBOARD_EC_S5_WAKE_EVENTS |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE))
+
+#define MAINBOARD_EC_S0IX_WAKE_EVENTS (MAINBOARD_EC_S3_WAKE_EVENTS)
+
+/* Log EC wake events plus EC shutdown events */
+#define MAINBOARD_EC_LOG_EVENTS \
+ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC))
+
+/*
+ * ACPI related definitions for ASL code.
+ */
+
+/* Enable EC backed ALS device in ACPI */
+#define EC_ENABLE_ALS_DEVICE
+
+/* Enable EC sync interrupt, EC_SYNC_IRQ is defined in baseboard/gpio.h */
+#define EC_ENABLE_SYNC_IRQ
+
+/* Enable EC backed PD MCU device in ACPI */
+#define EC_ENABLE_PD_MCU_DEVICE
+
+/* Enable LID switch and provide wake pin for EC */
+#define EC_ENABLE_LID_SWITCH
+#define EC_ENABLE_WAKE_PIN GPE_EC_WAKE
+
+#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */
+#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */
+#define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */
+
+#endif /* __BASEBOARD_EC_H__ */
diff --git a/src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/variants.h
index 5288b6f..005ec83 100644
--- a/src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/variants.h
+++ b/src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/variants.h
@@ -20,7 +20,8 @@
/* The next set of functions return the gpio table and fill in the number of
* entries for each table. */
const struct cros_gpio *variant_cros_gpios(size_t *num);
-
+/* Functions to configure GPIO as per variant schematics */
+void variant_configure_gpio_pads(void);
void variant_configure_early_gpio_pads(void);
size_t variant_memory_sku(void);
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