Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46267 )
Change subject: mb/intel/adlrvp: Add ADL-P mainboard ASL code ......................................................................
mb/intel/adlrvp: Add ADL-P mainboard ASL code
List of changes: 1. Add required files for dsdt.asl 2. Include 'acpi' directory for mainboard related ASL code
TEST=Dump dsdt.aml and verified all ACPI device present there
Change-Id: I70829e2bdb12fad20627d9aea47e745d9095f07a Signed-off-by: Subrata Banik subrata.banik@intel.com --- A src/mainboard/intel/adlrvp/acpi/mainboard.asl A src/mainboard/intel/adlrvp/acpi/mipi_camera.asl M src/mainboard/intel/adlrvp/dsdt.asl 3 files changed, 589 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/46267/1
diff --git a/src/mainboard/intel/adlrvp/acpi/mainboard.asl b/src/mainboard/intel/adlrvp/acpi/mainboard.asl new file mode 100644 index 0000000..6647ac1 --- /dev/null +++ b/src/mainboard/intel/adlrvp/acpi/mainboard.asl @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#if CONFIG(EC_GOOGLE_CHROMEEC) +Scope (_SB) +{ + Device (PWRB) + { + Name (_HID, EisaId ("PNP0C0C")) + } +} +#endif diff --git a/src/mainboard/intel/adlrvp/acpi/mipi_camera.asl b/src/mainboard/intel/adlrvp/acpi/mipi_camera.asl new file mode 100644 index 0000000..c830ea1 --- /dev/null +++ b/src/mainboard/intel/adlrvp/acpi/mipi_camera.asl @@ -0,0 +1,523 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2020 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope (_SB.PCI0.IPU0) +{ + Name (_DSD, Package (0x02) + { + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x02) + { + Package (0x02) + { + "port0", + "PRT0" + }, + + Package (0x02) + { + "port1", + "PRT1" + } + } + }) + + Name (PRT0, Package (0x04) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x01) + { + Package (0x02) + { + "port", + One + } + }, + + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "endpoint0", + "EP00" + } + } + }) + + Name (PRT1, Package (0x04) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x01) + { + Package (0x02) + { + "port", + 2 + } + }, + + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "endpoint0", + "EP10" + } + } + }) +} + +Scope (_SB.PCI0.IPU0) +{ + Name (EP00, Package (0x02) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x04) + { + Package (0x02) + { + "endpoint", + Zero + }, + + Package (0x02) + { + "clock-lanes", + Zero + }, + + Package (0x02) + { + "data-lanes", + Package (0x04) + { + One, + 0x02, + 0x03, + 0x04 + } + }, + + Package (0x02) + { + "remote-endpoint", + Package (0x03) + { + ^I2C3.CAM0, + Zero, + Zero + } + } + } + }) + Name (EP10, Package (0x02) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x04) + { + Package (0x02) + { + "endpoint", + Zero + }, + + Package (0x02) + { + "clock-lanes", + Zero + }, + + Package (0x02) + { + "data-lanes", + Package (0x04) + { + One, + 0x02, + 0x03, + 0x04 + } + }, + + Package (0x02) + { + "remote-endpoint", + Package (0x03) + { + ^I2C5.CAM1, + Zero, + Zero + } + } + } + }) +} + +Scope (_SB.PCI0.I2C3) +{ + PowerResource (RCPR, 0x00, 0x0000) + { + Name (STA, Zero) + Method (_ON, 0, Serialized) + { + If ((STA == Zero)) + { + /* Enable CLK0 with 19.2MHz */ + MCCT(0,1,1) + /* Pull PWREN(GPIO B23) high */ + STXS(GPP_B23) + Sleep(5) + /* Pull RST(GPIO C15) low */ + CTXS(GPP_C15) + Sleep(5) + /* Pull RST high */ + STXS(GPP_C15) + Sleep(5) + Store(1,STA) + } + } + + Method (_OFF, 0, Serialized) + { + If ((STA == One)) + { + /* Pull RST low */ + CTXS(GPP_C15) + /* Pull PWREN low */ + CTXS(GPP_B23) + /* Disable CLK0 */ + MCCT(0,0,1) + Store(0,STA) + } + } + + Method (_STA, 0, NotSerialized) + { + Return (STA) + } + } + + Device (CAM0) + { + Name (_HID, "OVTI8856") + Name (_UID, Zero) + Name (_DDN, "Ov 8856 Camera") + Method (_STA, 0, NotSerialized) + { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () + { + I2cSerialBus (0x0010, ControllerInitiated, 0x00061A80, + AddressingMode7Bit, "\_SB.PCI0.I2C3", + 0x00, ResourceConsumer, , + ) + }) + + Name (_PR0, Package (0x01) + { + RCPR + }) + + Name (_PR3, Package (0x01) + { + RCPR + }) + + Name (_DSD, Package (0x04) + { + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "port0", + "PRT0" + } + }, + + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x02) + { + Package (0x02) + { + "clock-frequency", + 0x0124F800 + }, + Package (0x02) + { + "lens-focus", + Package (0x01) + { + VCM0 + } + } + } + }) + + Name (PRT0, Package (0x04) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x01) + { + Package (0x02) + { + "port", + Zero + } + }, + + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "endpoint0", + "EP00" + } + } + }) + + Name (EP00, Package (0x02) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x03) + { + Package (0x02) + { + "endpoint", + Zero + }, + + Package (0x02) + { + "link-frequencies", + Package (0x01) + { + 0x325AA000 + } + }, + Package (0x02) + { + "remote-endpoint", + Package (0x03) + { + IPU0, + Zero, + Zero + } + } + } + }) + } + + Device (VCM0) + { + Name (_HID, "PRP0001") + Name (_UID, 0x03) + Name (_DDN, "DW9714 VCM") + Method (_STA, 0, NotSerialized) + { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () + { + I2cSerialBus (0x000C, ControllerInitiated, 0x00061A80, + AddressingMode7Bit, "\_SB.PCI0.I2C3", + 0x00, ResourceConsumer, , + ) + }) + Name (_DEP, Package (0x01) + { + CAM0 + }) + Name (_PR0, Package (0x01) + { + RCPR + }) + Name (_PR3, Package (0x01) + { + RCPR + }) + Name (_DSD, Package (0x02) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x01) + { + Package (0x02) + { + "compatible", + "dongwoon,dw9714" + } + } + }) + } +} + +Scope (_SB.PCI0.I2C5) +{ + PowerResource (FCPR, 0x00, 0x0000) + { + Name (STA, Zero) + Method (_ON, 0, Serialized) + { + If ((STA == Zero)) + { + /* Enable CLK1 with 19.2MHz */ + MCCT(1,1,1) + /* Pull PWREN(GPIO R6) high */ + STXS(GPP_R6) + Sleep(5) + /* Pull RST(GPIO H12) low */ + CTXS(GPP_H12) + Sleep(5) + /* Pull RST high */ + STXS(GPP_H12) + Sleep(5) + Store(1,STA) + } + } + + Method (_OFF, 0, Serialized) + { + If ((STA == One)) + { + /* Pull RST low */ + CTXS(GPP_H12) + /* Pull PWREN low */ + CTXS(GPP_R6) + /* Disable CLK1 */ + MCCT(1,0,1) + Store(0,STA) + } + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (STA) + } + } + + Device (CAM1) + { + Name (_HID, "OVTI8856") + Name (_UID, Zero) + Name (_DDN, "Ov 8856 Camera") + Method (_STA, 0, NotSerialized) + { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () + { + I2cSerialBus (0x0010, ControllerInitiated, 0x00061A80, + AddressingMode7Bit, "\_SB.PCI0.I2C5", + 0x00, ResourceConsumer, , + ) + }) + + Name (_PR0, Package (0x01) + { + FCPR + }) + + Name (_PR3, Package (0x01) + { + FCPR + }) + + Name (_DSD, Package (0x04) + { + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "port0", + "PRT0" + } + }, + + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x01) + { + Package (0x02) + { + "clock-frequency", + 0x0124F800 + } + } + }) + + Name (PRT0, Package (0x04) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x01) + { + Package (0x02) + { + "port", + Zero + } + }, + + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "endpoint0", + "EP00" + } + } + }) + + Name (EP00, Package (0x02) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x03) + { + Package (0x02) + { + "endpoint", + Zero + }, + + Package (0x02) + { + "link-frequencies", + Package (0x01) + { + 0x325AA000 + } + }, + Package (0x02) + { + "remote-endpoint", + Package (0x03) + { + IPU0, + One, + Zero + } + } + } + }) + } +} diff --git a/src/mainboard/intel/adlrvp/dsdt.asl b/src/mainboard/intel/adlrvp/dsdt.asl index fca3242..93dfc2c 100644 --- a/src/mainboard/intel/adlrvp/dsdt.asl +++ b/src/mainboard/intel/adlrvp/dsdt.asl @@ -1,6 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */
#include <acpi/acpi.h> +#include <baseboard/ec.h> +#include <baseboard/gpio.h>
DefinitionBlock( "dsdt.aml", @@ -11,5 +13,45 @@ 0x20110725 /* OEM revision */ ) { + #include <soc/intel/common/block/acpi/acpi/platform.asl>
+ /* global NVS and variables */ + #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> + + /* CPU */ + #include <cpu/intel/common/acpi/cpu.asl> + + Scope (_SB) { + Device (PCI0) + { + #include <soc/intel/common/block/acpi/acpi/northbridge.asl> + #include <soc/intel/alderlake/acpi/southbridge.asl> + #include <soc/intel/alderlake/acpi/tcss.asl> + #include <soc/intel/common/block/acpi/acpi/ipu.asl> + } + } + +#if CONFIG(CHROMEOS) + /* Chrome OS specific */ + #include <vendorcode/google/chromeos/acpi/chromeos.asl> +#endif + +#if CONFIG(EC_GOOGLE_CHROMEEC) + /* Chrome OS Embedded Controller */ + Scope (_SB.PCI0.LPCB) + { + /* ACPI code for EC SuperIO functions */ + #include <ec/google/chromeec/acpi/superio.asl> + /* ACPI code for EC functions */ + #include <ec/google/chromeec/acpi/ec.asl> + } +#endif + + #include <southbridge/intel/common/acpi/sleepstates.asl> + + /* Mainboard specific */ + #include "acpi/mainboard.asl" + + /* Camera */ + #include "acpi/mipi_camera.asl" }
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46267
to look at the new patch set (#2).
Change subject: mb/intel/adlrvp: Add ADL-P mainboard ASL code ......................................................................
mb/intel/adlrvp: Add ADL-P mainboard ASL code
List of changes: 1. Add required files for dsdt.asl 2. Include 'acpi' directory for mainboard related ASL code
TEST=Dump dsdt.aml and verified all ACPI device present there
Change-Id: I70829e2bdb12fad20627d9aea47e745d9095f07a Signed-off-by: Subrata Banik subrata.banik@intel.com --- A src/mainboard/intel/adlrvp/acpi/mainboard.asl A src/mainboard/intel/adlrvp/acpi/mipi_camera.asl M src/mainboard/intel/adlrvp/dsdt.asl 3 files changed, 563 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/46267/2
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46267 )
Change subject: mb/intel/adlrvp: Add ADL-P mainboard ASL code ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/46267/2/src/mainboard/intel/adlrvp/... File src/mainboard/intel/adlrvp/acpi/mipi_camera.asl:
https://review.coreboot.org/c/coreboot/+/46267/2/src/mainboard/intel/adlrvp/... PS2, Line 177: Store old syntax
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46267 )
Change subject: mb/intel/adlrvp: Add ADL-P mainboard ASL code ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/46267/2/src/mainboard/intel/adlrvp/... File src/mainboard/intel/adlrvp/acpi/mipi_camera.asl:
https://review.coreboot.org/c/coreboot/+/46267/2/src/mainboard/intel/adlrvp/... PS2, Line 177: Store
old syntax
Ack
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46267
to look at the new patch set (#3).
Change subject: mb/intel/adlrvp: Add ADL-P mainboard ASL code ......................................................................
mb/intel/adlrvp: Add ADL-P mainboard ASL code
List of changes: 1. Add required files for dsdt.asl 2. Include 'acpi' directory for mainboard related ASL code
TEST=Dump dsdt.aml and verified all ACPI device present there
Change-Id: I70829e2bdb12fad20627d9aea47e745d9095f07a Signed-off-by: Subrata Banik subrata.banik@intel.com --- A src/mainboard/intel/adlrvp/acpi/mainboard.asl M src/mainboard/intel/adlrvp/dsdt.asl 2 files changed, 50 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/46267/3
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46267
to look at the new patch set (#4).
Change subject: mb/intel/adlrvp: Add ADL-P mainboard ASL code ......................................................................
mb/intel/adlrvp: Add ADL-P mainboard ASL code
Add required ASL files into dsdt.asl
TEST=Dump dsdt.aml and verified all ACPI device present there
Change-Id: I70829e2bdb12fad20627d9aea47e745d9095f07a Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/mainboard/intel/adlrvp/dsdt.asl 1 file changed, 37 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/46267/4
Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46267
to look at the new patch set (#5).
Change subject: mb/intel/adlrvp: Add ADL-P mainboard ASL code ......................................................................
mb/intel/adlrvp: Add ADL-P mainboard ASL code
Add required ASL files into dsdt.asl
TEST=Dump dsdt.aml and verified all ACPI device present there
Change-Id: I70829e2bdb12fad20627d9aea47e745d9095f07a Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/mainboard/intel/adlrvp/dsdt.asl 1 file changed, 36 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/46267/5
Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46267
to look at the new patch set (#6).
Change subject: mb/intel/adlrvp: Add ADL-P mainboard ASL code ......................................................................
mb/intel/adlrvp: Add ADL-P mainboard ASL code
Add required ASL files into dsdt.asl
TEST=Dump dsdt.aml and verified all ACPI device present there
Change-Id: I70829e2bdb12fad20627d9aea47e745d9095f07a Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/mainboard/intel/adlrvp/dsdt.asl 1 file changed, 36 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/46267/6
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46267 )
Change subject: mb/intel/adlrvp: Add ADL-P mainboard ASL code ......................................................................
Patch Set 7:
Angel, Tim, If you could help to take a look this CL?
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46267 )
Change subject: mb/intel/adlrvp: Add ADL-P mainboard ASL code ......................................................................
Patch Set 7: Code-Review+1
(3 comments)
https://review.coreboot.org/c/coreboot/+/46267/7//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/46267/7//COMMIT_MSG@11 PS7, Line 11: Dump dsdt.aml and verified all ACPI device present there Dump and disassemble DSDT and verify all ACPI devices are present.
https://review.coreboot.org/c/coreboot/+/46267/7/src/mainboard/intel/adlrvp/... File src/mainboard/intel/adlrvp/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/46267/7/src/mainboard/intel/adlrvp/... PS7, Line 21: /* CPU */ I don't think this comment is useful
https://review.coreboot.org/c/coreboot/+/46267/7/src/mainboard/intel/adlrvp/... PS7, Line 24: Scope (_SB) { : Device (PCI0) These two could be replaced with:
Device (_SB.PCI0)
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46267 )
Change subject: mb/intel/adlrvp: Add ADL-P mainboard ASL code ......................................................................
Patch Set 7:
(3 comments)
https://review.coreboot.org/c/coreboot/+/46267/7//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/46267/7//COMMIT_MSG@11 PS7, Line 11: Dump dsdt.aml and verified all ACPI device present there
Dump and disassemble DSDT and verify all ACPI devices are present.
Ack
https://review.coreboot.org/c/coreboot/+/46267/7/src/mainboard/intel/adlrvp/... File src/mainboard/intel/adlrvp/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/46267/7/src/mainboard/intel/adlrvp/... PS7, Line 21: /* CPU */
I don't think this comment is useful
Ack
https://review.coreboot.org/c/coreboot/+/46267/7/src/mainboard/intel/adlrvp/... PS7, Line 24: Scope (_SB) { : Device (PCI0)
These two could be replaced with: […]
Ack
Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46267
to look at the new patch set (#8).
Change subject: mb/intel/adlrvp: Add ADL-P mainboard ASL code ......................................................................
mb/intel/adlrvp: Add ADL-P mainboard ASL code
Add required ASL files into dsdt.asl
TEST=Dump and disassemble DSDT and verify all ACPI devices are present.
Change-Id: I70829e2bdb12fad20627d9aea47e745d9095f07a Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/mainboard/intel/adlrvp/dsdt.asl 1 file changed, 32 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/46267/8
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46267 )
Change subject: mb/intel/adlrvp: Add ADL-P mainboard ASL code ......................................................................
Patch Set 8: Code-Review+2
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46267 )
Change subject: mb/intel/adlrvp: Add ADL-P mainboard ASL code ......................................................................
Patch Set 8: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46267 )
Change subject: mb/intel/adlrvp: Add ADL-P mainboard ASL code ......................................................................
mb/intel/adlrvp: Add ADL-P mainboard ASL code
Add required ASL files into dsdt.asl
TEST=Dump and disassemble DSDT and verify all ACPI devices are present.
Change-Id: I70829e2bdb12fad20627d9aea47e745d9095f07a Signed-off-by: Subrata Banik subrata.banik@intel.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/46267 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Angel Pons th3fanbus@gmail.com Reviewed-by: Tim Wawrzynczak twawrzynczak@chromium.org --- M src/mainboard/intel/adlrvp/dsdt.asl 1 file changed, 32 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved
diff --git a/src/mainboard/intel/adlrvp/dsdt.asl b/src/mainboard/intel/adlrvp/dsdt.asl index 6163d01..d4fb7a4 100644 --- a/src/mainboard/intel/adlrvp/dsdt.asl +++ b/src/mainboard/intel/adlrvp/dsdt.asl @@ -1,6 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */
#include <acpi/acpi.h> +#include <baseboard/ec.h> +#include <baseboard/gpio.h>
DefinitionBlock( "dsdt.aml", @@ -11,5 +13,35 @@ 0x20110725 /* OEM revision */ ) { + #include <soc/intel/common/block/acpi/acpi/platform.asl>
+ /* global NVS and variables */ + #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> + + #include <cpu/intel/common/acpi/cpu.asl> + + Device (_SB.PCI0) { + #include <soc/intel/common/block/acpi/acpi/northbridge.asl> + #include <soc/intel/alderlake/acpi/southbridge.asl> + #include <soc/intel/alderlake/acpi/tcss.asl> + #include <soc/intel/common/block/acpi/acpi/ipu.asl> + } + +#if CONFIG(CHROMEOS) + /* Chrome OS specific */ + #include <vendorcode/google/chromeos/acpi/chromeos.asl> +#endif + +#if CONFIG(EC_GOOGLE_CHROMEEC) + /* Chrome OS Embedded Controller */ + Scope (_SB.PCI0.LPCB) + { + /* ACPI code for EC SuperIO functions */ + #include <ec/google/chromeec/acpi/superio.asl> + /* ACPI code for EC functions */ + #include <ec/google/chromeec/acpi/ec.asl> + } +#endif + + #include <southbridge/intel/common/acpi/sleepstates.asl> }
-
Angel Pons (Code Review) -
HAOUAS Elyes (Code Review)
-
Patrick Georgi (Code Review)
-
Subrata Banik (Code Review)
-
Tim Wawrzynczak (Code Review)