coreboot-gerrit October 2020

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel: convert XTAL frequency constant to Kconfig
by Michael Niewöhner (Code Review) 14 Oct '20

14 Oct '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46018 ) Change subject: soc/intel: convert XTAL frequency constant to Kconfig ...................................................................... Patch Set 10: (1 comment) https://review.coreboot.org/c/coreboot/+/46018/10/src/soc/intel/common/bloc… File src/soc/intel/common/block/cpu/Kconfig: https://review.coreboot.org/c/coreboot/+/46018/10/src/soc/intel/common/bloc… PS10, Line 102: config SOC_INTEL_COMMON_BLOCK_XTAL_CLOCK_HZ > It reads a bit odd. It's about the CPU block, but you omit `CPU`. So maybe […] I named it like SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ, but yes, XTAL is about the cpu, while gspi isn't. I just found CPU_BCLK_MHZ, so it would make sense to name XTAL like CPU_XTAL_HZ -- To view, visit https://review.coreboot.org/c/coreboot/+/46018 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1382dd274eeb9cb748f94c34f5d9a83880624c18 Gerrit-Change-Number: 46018 Gerrit-PatchSet: 10 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 14 Oct 2020 09:49:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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Change in coreboot[master]: .gitignore: Exclude '*.fd'
by Angel Pons (Code Review) 14 Oct '20

14 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46322 ) Change subject: .gitignore: Exclude '*.fd' ...................................................................... .gitignore: Exclude '*.fd' These files are usually binaries, and should never be committed. Change-Id: I9df80f777020632e4c82a06ae3ae73c95234f3b5 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M .gitignore 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/46322/1 diff --git a/.gitignore b/.gitignore index 2fabfee..97cc9ce 100644 --- a/.gitignore +++ b/.gitignore @@ -59,6 +59,7 @@ *.debug !Kconfig.debug *.elf +*.fd *.o *.o.d *.out -- To view, visit https://review.coreboot.org/c/coreboot/+/46322 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9df80f777020632e4c82a06ae3ae73c95234f3b5 Gerrit-Change-Number: 46322 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/x4x: Place raminit definitions in raminit.h
by Angel Pons (Code Review) 14 Oct '20

14 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45424 ) Change subject: nb/intel/x4x: Place raminit definitions in raminit.h ...................................................................... nb/intel/x4x: Place raminit definitions in raminit.h There's no need to have implementation details in a public header. Tested with BUILD_TIMELESS=1, Asus P5QL PRO remains identical. Change-Id: I04d8c610d3e52adecfe96cc435f0523bedf3060a Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/x4x/dq_dqs.c M src/northbridge/intel/x4x/raminit.c A src/northbridge/intel/x4x/raminit.h M src/northbridge/intel/x4x/raminit_ddr23.c M src/northbridge/intel/x4x/raminit_tables.c M src/northbridge/intel/x4x/rcven.c M src/northbridge/intel/x4x/romstage.c M src/northbridge/intel/x4x/x4x.h 8 files changed, 259 insertions(+), 245 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/45424/1 diff --git a/src/northbridge/intel/x4x/dq_dqs.c b/src/northbridge/intel/x4x/dq_dqs.c index 1d71fe7..8e0fee9 100644 --- a/src/northbridge/intel/x4x/dq_dqs.c +++ b/src/northbridge/intel/x4x/dq_dqs.c @@ -5,6 +5,7 @@ #include <delay.h> #include <string.h> #include <types.h> +#include "raminit.h" #include "x4x.h" static void print_dll_setting(const struct dll_setting *dll_setting, diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c index 933145a..4cf1f01 100644 --- a/src/northbridge/intel/x4x/raminit.c +++ b/src/northbridge/intel/x4x/raminit.c @@ -15,6 +15,7 @@ #include <timestamp.h> #include <types.h> +#include "raminit.h" #include "x4x.h" #define MRC_CACHE_VERSION 0 diff --git a/src/northbridge/intel/x4x/raminit.h b/src/northbridge/intel/x4x/raminit.h new file mode 100644 index 0000000..ca58b1f --- /dev/null +++ b/src/northbridge/intel/x4x/raminit.h @@ -0,0 +1,247 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __X4X_RAMINIT_H__ +#define __X4X_RAMINIT_H__ + +#include <stdint.h> + +#define NOP_CMD 0x2 +#define PRECHARGE_CMD 0x4 +#define MRS_CMD 0x6 +#define EMRS_CMD 0x8 +#define EMRS1_CMD (EMRS_CMD | 0x10) +#define EMRS2_CMD (EMRS_CMD | 0x20) +#define EMRS3_CMD (EMRS_CMD | 0x30) +#define ZQCAL_CMD 0xa +#define CBR_CMD 0xc +#define NORMALOP_CMD 0xe + +#define TOTAL_CHANNELS 2 +#define TOTAL_DIMMS 4 +#define TOTAL_BYTELANES 8 +#define DIMMS_PER_CHANNEL (TOTAL_DIMMS / TOTAL_CHANNELS) +#define RAW_CARD_UNPOPULATED 0xff +#define RAW_CARD_POPULATED 0 + +#define DIMM_IS_POPULATED(dimms, idx) (dimms[idx].card_type != RAW_CARD_UNPOPULATED) +#define IF_DIMM_POPULATED(dimms, idx) if (dimms[idx].card_type != RAW_CARD_UNPOPULATED) +#define ONLY_DIMMA_IS_POPULATED(dimms, ch) ( \ + (DIMM_IS_POPULATED(dimms, (ch == 0) ? 0 : 2) && \ + !DIMM_IS_POPULATED(dimms, (ch == 0) ? 1 : 3))) +#define ONLY_DIMMB_IS_POPULATED(dimms, ch) ( \ + (DIMM_IS_POPULATED(dimms, (ch == 0) ? 1 : 3) && \ + !DIMM_IS_POPULATED(dimms, (ch == 0) ? 0 : 2))) +#define BOTH_DIMMS_ARE_POPULATED(dimms, ch) ( \ + (DIMM_IS_POPULATED(dimms, (ch == 0) ? 0 : 2) && \ + (DIMM_IS_POPULATED(dimms, (ch == 0) ? 1 : 3)))) +#define FOR_EACH_DIMM(idx) \ + for (idx = 0; idx < TOTAL_DIMMS; ++idx) +#define FOR_EACH_POPULATED_DIMM(dimms, idx) \ + FOR_EACH_DIMM(idx) IF_DIMM_POPULATED(dimms, idx) +#define FOR_EACH_DIMM_IN_CHANNEL(ch, idx) \ + for (idx = (ch) << 1; idx < ((ch) << 1) + DIMMS_PER_CHANNEL; ++idx) +#define FOR_EACH_POPULATED_DIMM_IN_CHANNEL(dimms, ch, idx) \ + FOR_EACH_DIMM_IN_CHANNEL(ch, idx) IF_DIMM_POPULATED(dimms, idx) +#define CHANNEL_IS_POPULATED(dimms, idx) \ + ((dimms[idx<<1].card_type != RAW_CARD_UNPOPULATED) \ + || (dimms[(idx<<1) + 1].card_type != RAW_CARD_UNPOPULATED)) +#define CHANNEL_IS_CARDF(dimms, idx) \ + ((dimms[idx<<1].card_type == 0xf) \ + || (dimms[(idx<<1) + 1].card_type == 0xf)) +#define IF_CHANNEL_POPULATED(dimms, idx) \ + if ((dimms[idx<<1].card_type != RAW_CARD_UNPOPULATED) \ + || (dimms[(idx<<1) + 1].card_type != RAW_CARD_UNPOPULATED)) +#define FOR_EACH_CHANNEL(idx) \ + for (idx = 0; idx < TOTAL_CHANNELS; ++idx) +#define FOR_EACH_POPULATED_CHANNEL(dimms, idx) \ + FOR_EACH_CHANNEL(idx) IF_CHANNEL_POPULATED(dimms, idx) + +#define RANKS_PER_CHANNEL 4 +#define RANK_IS_POPULATED(dimms, ch, r) \ + (((dimms[ch<<1].card_type != RAW_CARD_UNPOPULATED) && ((r) < dimms[ch<<1].ranks)) || \ + ((dimms[(ch<<1) + 1].card_type != RAW_CARD_UNPOPULATED) && ((r) >= 2) && ((r) < (dimms[(ch<<1) + 1].ranks + 2)))) +#define IF_RANK_POPULATED(dimms, ch, r) \ + if (((dimms[ch<<1].card_type != RAW_CARD_UNPOPULATED) \ + && ((r) < dimms[ch<<1].ranks)) \ + || ((dimms[(ch<<1) + 1].card_type != RAW_CARD_UNPOPULATED) \ + && ((r) >= 2) && ((r) < (dimms[(ch<<1) + 1].ranks + 2)))) +#define FOR_EACH_RANK_IN_CHANNEL(r) \ + for (r = 0; r < RANKS_PER_CHANNEL; ++r) +#define FOR_EACH_POPULATED_RANK_IN_CHANNEL(dimms, ch, r) \ + FOR_EACH_RANK_IN_CHANNEL(r) IF_RANK_POPULATED(dimms, ch, r) +#define FOR_EACH_RANK(ch, r) \ + FOR_EACH_CHANNEL(ch) FOR_EACH_RANK_IN_CHANNEL(r) +#define FOR_EACH_POPULATED_RANK(dimms, ch, r) \ + FOR_EACH_RANK(ch, r) IF_RANK_POPULATED(dimms, ch, r) +#define FOR_EACH_BYTELANE(l) \ + for (l = 0; l < TOTAL_BYTELANES; l++) +#define FOR_EACH_POPULATED_CHANNEL_AND_BYTELANE(dimms, ch, l) \ + FOR_EACH_POPULATED_CHANNEL (dimms, ch) FOR_EACH_BYTELANE(l) + +#define DDR3_MAX_CAS 18 + +enum fsb_clock { + FSB_CLOCK_800MHz = 0, + FSB_CLOCK_1066MHz = 1, + FSB_CLOCK_1333MHz = 2, +}; + +enum mem_clock { + MEM_CLOCK_400MHz = 0, + MEM_CLOCK_533MHz = 1, + MEM_CLOCK_667MHz = 2, + MEM_CLOCK_800MHz = 3, + MEM_CLOCK_1066MHz = 4, + MEM_CLOCK_1333MHz = 5, +}; + +enum ddr { + DDR2 = 2, + DDR3 = 3, +}; + +enum ddrxspd { + DDR2SPD = 0x8, + DDR3SPD = 0xb, +}; + +enum chip_width { /* as in DDR3 spd */ + CHIP_WIDTH_x4 = 0, + CHIP_WIDTH_x8 = 1, + CHIP_WIDTH_x16 = 2, + CHIP_WIDTH_x32 = 3, +}; + +enum chip_cap { /* as in DDR3 spd */ + CHIP_CAP_256M = 0, + CHIP_CAP_512M = 1, + CHIP_CAP_1G = 2, + CHIP_CAP_2G = 3, + CHIP_CAP_4G = 4, + CHIP_CAP_8G = 5, + CHIP_CAP_16G = 6, +}; + +struct dll_setting { + u8 tap; + u8 pi; + u8 db_en; + u8 db_sel; + u8 clk_delay; + u8 coarse; +}; + +struct rt_dqs_setting { + u8 tap; + u8 pi; +}; + +enum n_banks { + N_BANKS_4 = 0, + N_BANKS_8 = 1, +}; + +struct timings { + unsigned int CAS; + unsigned int tclk; + enum fsb_clock fsb_clk; + enum mem_clock mem_clk; + unsigned int tRAS; + unsigned int tRP; + unsigned int tRCD; + unsigned int tWR; + unsigned int tRFC; + unsigned int tWTR; + unsigned int tRRD; + unsigned int tRTP; +}; + +struct dimminfo { + unsigned int card_type; /* 0xff: unpopulated, 0xa - 0xf: raw card type A - F */ + enum chip_width width; + unsigned int page_size; /* of whole DIMM in Bytes (4096 or 8192) */ + enum n_banks n_banks; + unsigned int ranks; + unsigned int rows; + unsigned int cols; + u16 spd_crc; + u8 mirrored; +}; + +struct rcven_timings { + u8 min_common_coarse; + u8 coarse_offset[TOTAL_BYTELANES]; + u8 medium[TOTAL_BYTELANES]; + u8 tap[TOTAL_BYTELANES]; + u8 pi[TOTAL_BYTELANES]; +}; + +/* The setup is up to two DIMMs per channel */ +struct sysinfo { + int boot_path; + enum fsb_clock max_fsb; + + int dimm_config[2]; + int spd_type; + int channel_capacity[2]; + struct timings selected_timings; + struct dimminfo dimms[4]; + u8 spd_map[4]; + struct rcven_timings rcven_t[TOTAL_CHANNELS]; + /* + * The rt_dqs delay register for rank 0 seems to be used + * for all other ranks on the channel, so only save that + */ + struct rt_dqs_setting rt_dqs[TOTAL_CHANNELS][TOTAL_BYTELANES]; + struct dll_setting dqs_settings[TOTAL_CHANNELS][TOTAL_BYTELANES]; + struct dll_setting dq_settings[TOTAL_CHANNELS][TOTAL_BYTELANES]; + u8 nmode; + u8 stacked_mode; +}; + +enum ddr2_signals { + CLKSET0 = 0, + CTRL0, + CLKSET1, + CMD, + CTRL1, + CTRL2, + CTRL3, +}; + +void sdram_initialize(int boot_path, const u8 *spd_map); +void do_raminit(struct sysinfo *, int fast_boot); +void rcven(struct sysinfo *s); +u32 fsb_to_mhz(u32 speed); +u32 ddr_to_mhz(u32 speed); +u32 test_address(int channel, int rank); +void dqsset(u8 ch, u8 lane, const struct dll_setting *setting); +void dqset(u8 ch, u8 lane, const struct dll_setting *setting); +void rt_set_dqs(u8 channel, u8 lane, u8 rank, struct rt_dqs_setting *dqs_setting); +int do_write_training(struct sysinfo *s); +int do_read_training(struct sysinfo *s); +void search_write_leveling(struct sysinfo *s); +void send_jedec_cmd(const struct sysinfo *s, u8 r, u8 ch, u8 cmd, u32 val); + +extern const struct dll_setting default_ddr2_667_ctrl[7]; +extern const struct dll_setting default_ddr2_800_ctrl[7]; +extern const struct dll_setting default_ddr3_800_ctrl[2][7]; +extern const struct dll_setting default_ddr3_1067_ctrl[2][7]; +extern const struct dll_setting default_ddr3_1333_ctrl[2][7]; +extern const struct dll_setting default_ddr2_667_dqs[TOTAL_BYTELANES]; +extern const struct dll_setting default_ddr2_800_dqs[TOTAL_BYTELANES]; +extern const struct dll_setting default_ddr3_800_dqs[2][TOTAL_BYTELANES]; +extern const struct dll_setting default_ddr3_1067_dqs[2][TOTAL_BYTELANES]; +extern const struct dll_setting default_ddr3_1333_dqs[2][TOTAL_BYTELANES]; +extern const struct dll_setting default_ddr2_667_dq[TOTAL_BYTELANES]; +extern const struct dll_setting default_ddr2_800_dq[TOTAL_BYTELANES]; +extern const struct dll_setting default_ddr3_800_dq[2][TOTAL_BYTELANES]; +extern const struct dll_setting default_ddr3_1067_dq[2][TOTAL_BYTELANES]; +extern const struct dll_setting default_ddr3_1333_dq[2][TOTAL_BYTELANES]; +extern const u8 ddr3_emrs1_rtt_nom_config[16][4]; +extern const u8 post_jedec_tab[3][4][2]; +extern const u32 ddr3_c2_tab[2][3][6][2]; +extern const u8 ddr3_c2_x264[3][6]; +extern const u16 ddr3_c2_x23c[3][6]; + +#endif /* __X4X_RAMINIT_H__ */ diff --git a/src/northbridge/intel/x4x/raminit_ddr23.c b/src/northbridge/intel/x4x/raminit_ddr23.c index c3c2da7..f3c8415 100644 --- a/src/northbridge/intel/x4x/raminit_ddr23.c +++ b/src/northbridge/intel/x4x/raminit_ddr23.c @@ -13,6 +13,7 @@ #include <southbridge/intel/i82801jx/i82801jx.h> #endif #include <string.h> +#include "raminit.h" #include "x4x.h" #define ME_UMA_SIZEMB 0 diff --git a/src/northbridge/intel/x4x/raminit_tables.c b/src/northbridge/intel/x4x/raminit_tables.c index 3cd4879..6f905b3 100644 --- a/src/northbridge/intel/x4x/raminit_tables.c +++ b/src/northbridge/intel/x4x/raminit_tables.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <stdint.h> -#include "x4x.h" +#include "raminit.h" const struct dll_setting default_ddr2_667_ctrl[7] = { /* tap pi db delay coarse*/ diff --git a/src/northbridge/intel/x4x/rcven.c b/src/northbridge/intel/x4x/rcven.c index 82481ab..8a86ce9 100644 --- a/src/northbridge/intel/x4x/rcven.c +++ b/src/northbridge/intel/x4x/rcven.c @@ -3,6 +3,7 @@ #include <device/mmio.h> #include <console/console.h> #include <delay.h> +#include "raminit.h" #include "x4x.h" #define MAX_COARSE 15 diff --git a/src/northbridge/intel/x4x/romstage.c b/src/northbridge/intel/x4x/romstage.c index 5a30a80..648520c 100644 --- a/src/northbridge/intel/x4x/romstage.c +++ b/src/northbridge/intel/x4x/romstage.c @@ -2,7 +2,6 @@ #include <console/console.h> #include <southbridge/intel/common/pmclib.h> -#include <northbridge/intel/x4x/x4x.h> #include <arch/romstage.h> #if CONFIG(SOUTHBRIDGE_INTEL_I82801JX) @@ -11,6 +10,9 @@ #include <southbridge/intel/i82801gx/i82801gx.h> #endif +#include "raminit.h" +#include "x4x.h" + __weak void mb_pre_raminit_setup(int s3_resume) { } diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h index 2534575..ea34fe0 100644 --- a/src/northbridge/intel/x4x/x4x.h +++ b/src/northbridge/intel/x4x/x4x.h @@ -6,6 +6,10 @@ #include <stdint.h> #include "memmap.h" +#define BOOT_PATH_NORMAL 0 +#define BOOT_PATH_WARM_RESET 1 +#define BOOT_PATH_RESUME 2 + /* * D0:F0 */ @@ -161,215 +165,6 @@ #define EP_PORTARB(x) (0x100 + 4 * (x)) /* 256bit */ - - -#define NOP_CMD 0x2 -#define PRECHARGE_CMD 0x4 -#define MRS_CMD 0x6 -#define EMRS_CMD 0x8 -#define EMRS1_CMD (EMRS_CMD | 0x10) -#define EMRS2_CMD (EMRS_CMD | 0x20) -#define EMRS3_CMD (EMRS_CMD | 0x30) -#define ZQCAL_CMD 0xa -#define CBR_CMD 0xc -#define NORMALOP_CMD 0xe - -#define TOTAL_CHANNELS 2 -#define TOTAL_DIMMS 4 -#define TOTAL_BYTELANES 8 -#define DIMMS_PER_CHANNEL (TOTAL_DIMMS / TOTAL_CHANNELS) -#define RAW_CARD_UNPOPULATED 0xff -#define RAW_CARD_POPULATED 0 - -#define DIMM_IS_POPULATED(dimms, idx) (dimms[idx].card_type != RAW_CARD_UNPOPULATED) -#define IF_DIMM_POPULATED(dimms, idx) if (dimms[idx].card_type != RAW_CARD_UNPOPULATED) -#define ONLY_DIMMA_IS_POPULATED(dimms, ch) ( \ - (DIMM_IS_POPULATED(dimms, (ch == 0) ? 0 : 2) && \ - !DIMM_IS_POPULATED(dimms, (ch == 0) ? 1 : 3))) -#define ONLY_DIMMB_IS_POPULATED(dimms, ch) ( \ - (DIMM_IS_POPULATED(dimms, (ch == 0) ? 1 : 3) && \ - !DIMM_IS_POPULATED(dimms, (ch == 0) ? 0 : 2))) -#define BOTH_DIMMS_ARE_POPULATED(dimms, ch) ( \ - (DIMM_IS_POPULATED(dimms, (ch == 0) ? 0 : 2) && \ - (DIMM_IS_POPULATED(dimms, (ch == 0) ? 1 : 3)))) -#define FOR_EACH_DIMM(idx) \ - for (idx = 0; idx < TOTAL_DIMMS; ++idx) -#define FOR_EACH_POPULATED_DIMM(dimms, idx) \ - FOR_EACH_DIMM(idx) IF_DIMM_POPULATED(dimms, idx) -#define FOR_EACH_DIMM_IN_CHANNEL(ch, idx) \ - for (idx = (ch) << 1; idx < ((ch) << 1) + DIMMS_PER_CHANNEL; ++idx) -#define FOR_EACH_POPULATED_DIMM_IN_CHANNEL(dimms, ch, idx) \ - FOR_EACH_DIMM_IN_CHANNEL(ch, idx) IF_DIMM_POPULATED(dimms, idx) -#define CHANNEL_IS_POPULATED(dimms, idx) \ - ((dimms[idx<<1].card_type != RAW_CARD_UNPOPULATED) \ - || (dimms[(idx<<1) + 1].card_type != RAW_CARD_UNPOPULATED)) -#define CHANNEL_IS_CARDF(dimms, idx) \ - ((dimms[idx<<1].card_type == 0xf) \ - || (dimms[(idx<<1) + 1].card_type == 0xf)) -#define IF_CHANNEL_POPULATED(dimms, idx) \ - if ((dimms[idx<<1].card_type != RAW_CARD_UNPOPULATED) \ - || (dimms[(idx<<1) + 1].card_type != RAW_CARD_UNPOPULATED)) -#define FOR_EACH_CHANNEL(idx) \ - for (idx = 0; idx < TOTAL_CHANNELS; ++idx) -#define FOR_EACH_POPULATED_CHANNEL(dimms, idx) \ - FOR_EACH_CHANNEL(idx) IF_CHANNEL_POPULATED(dimms, idx) - -#define RANKS_PER_CHANNEL 4 -#define RANK_IS_POPULATED(dimms, ch, r) \ - (((dimms[ch<<1].card_type != RAW_CARD_UNPOPULATED) && ((r) < dimms[ch<<1].ranks)) || \ - ((dimms[(ch<<1) + 1].card_type != RAW_CARD_UNPOPULATED) && ((r) >= 2) && ((r) < (dimms[(ch<<1) + 1].ranks + 2)))) -#define IF_RANK_POPULATED(dimms, ch, r) \ - if (((dimms[ch<<1].card_type != RAW_CARD_UNPOPULATED) \ - && ((r) < dimms[ch<<1].ranks)) \ - || ((dimms[(ch<<1) + 1].card_type != RAW_CARD_UNPOPULATED) \ - && ((r) >= 2) && ((r) < (dimms[(ch<<1) + 1].ranks + 2)))) -#define FOR_EACH_RANK_IN_CHANNEL(r) \ - for (r = 0; r < RANKS_PER_CHANNEL; ++r) -#define FOR_EACH_POPULATED_RANK_IN_CHANNEL(dimms, ch, r) \ - FOR_EACH_RANK_IN_CHANNEL(r) IF_RANK_POPULATED(dimms, ch, r) -#define FOR_EACH_RANK(ch, r) \ - FOR_EACH_CHANNEL(ch) FOR_EACH_RANK_IN_CHANNEL(r) -#define FOR_EACH_POPULATED_RANK(dimms, ch, r) \ - FOR_EACH_RANK(ch, r) IF_RANK_POPULATED(dimms, ch, r) -#define FOR_EACH_BYTELANE(l) \ - for (l = 0; l < TOTAL_BYTELANES; l++) -#define FOR_EACH_POPULATED_CHANNEL_AND_BYTELANE(dimms, ch, l) \ - FOR_EACH_POPULATED_CHANNEL (dimms, ch) FOR_EACH_BYTELANE(l) - -#define DDR3_MAX_CAS 18 - -enum fsb_clock { - FSB_CLOCK_800MHz = 0, - FSB_CLOCK_1066MHz = 1, - FSB_CLOCK_1333MHz = 2, -}; - -enum mem_clock { - MEM_CLOCK_400MHz = 0, - MEM_CLOCK_533MHz = 1, - MEM_CLOCK_667MHz = 2, - MEM_CLOCK_800MHz = 3, - MEM_CLOCK_1066MHz = 4, - MEM_CLOCK_1333MHz = 5, -}; - -enum ddr { - DDR2 = 2, - DDR3 = 3, -}; - -enum ddrxspd { - DDR2SPD = 0x8, - DDR3SPD = 0xb, -}; - -enum chip_width { /* as in DDR3 spd */ - CHIP_WIDTH_x4 = 0, - CHIP_WIDTH_x8 = 1, - CHIP_WIDTH_x16 = 2, - CHIP_WIDTH_x32 = 3, -}; - -enum chip_cap { /* as in DDR3 spd */ - CHIP_CAP_256M = 0, - CHIP_CAP_512M = 1, - CHIP_CAP_1G = 2, - CHIP_CAP_2G = 3, - CHIP_CAP_4G = 4, - CHIP_CAP_8G = 5, - CHIP_CAP_16G = 6, -}; - -struct dll_setting { - u8 tap; - u8 pi; - u8 db_en; - u8 db_sel; - u8 clk_delay; - u8 coarse; -}; - -struct rt_dqs_setting { - u8 tap; - u8 pi; -}; - -enum n_banks { - N_BANKS_4 = 0, - N_BANKS_8 = 1, -}; - -struct timings { - unsigned int CAS; - unsigned int tclk; - enum fsb_clock fsb_clk; - enum mem_clock mem_clk; - unsigned int tRAS; - unsigned int tRP; - unsigned int tRCD; - unsigned int tWR; - unsigned int tRFC; - unsigned int tWTR; - unsigned int tRRD; - unsigned int tRTP; -}; - -struct dimminfo { - unsigned int card_type; /* 0xff: unpopulated, 0xa - 0xf: raw card type A - F */ - enum chip_width width; - unsigned int page_size; /* of whole DIMM in Bytes (4096 or 8192) */ - enum n_banks n_banks; - unsigned int ranks; - unsigned int rows; - unsigned int cols; - u16 spd_crc; - u8 mirrored; -}; - -struct rcven_timings { - u8 min_common_coarse; - u8 coarse_offset[TOTAL_BYTELANES]; - u8 medium[TOTAL_BYTELANES]; - u8 tap[TOTAL_BYTELANES]; - u8 pi[TOTAL_BYTELANES]; -}; - -/* The setup is up to two DIMMs per channel */ -struct sysinfo { - int boot_path; - enum fsb_clock max_fsb; - - int dimm_config[2]; - int spd_type; - int channel_capacity[2]; - struct timings selected_timings; - struct dimminfo dimms[4]; - u8 spd_map[4]; - struct rcven_timings rcven_t[TOTAL_CHANNELS]; - /* - * The rt_dqs delay register for rank 0 seems to be used - * for all other ranks on the channel, so only save that - */ - struct rt_dqs_setting rt_dqs[TOTAL_CHANNELS][TOTAL_BYTELANES]; - struct dll_setting dqs_settings[TOTAL_CHANNELS][TOTAL_BYTELANES]; - struct dll_setting dq_settings[TOTAL_CHANNELS][TOTAL_BYTELANES]; - u8 nmode; - u8 stacked_mode; -}; -#define BOOT_PATH_NORMAL 0 -#define BOOT_PATH_WARM_RESET 1 -#define BOOT_PATH_RESUME 2 - -enum ddr2_signals { - CLKSET0 = 0, - CTRL0, - CLKSET1, - CMD, - CTRL1, - CTRL2, - CTRL3, -}; - void x4x_early_init(void); void x4x_late_init(int s3resume); void mb_get_spd_map(u8 spd_map[4]); @@ -378,40 +173,6 @@ u32 decode_igd_gtt_size(u32 gsm); u32 decode_tseg_size(const u32 esmramc); int decode_pcie_bar(u32 *const base, u32 *const len); -void sdram_initialize(int boot_path, const u8 *spd_map); -void do_raminit(struct sysinfo *, int fast_boot); -void rcven(struct sysinfo *s); -u32 fsb_to_mhz(u32 speed); -u32 ddr_to_mhz(u32 speed); -u32 test_address(int channel, int rank); -void dqsset(u8 ch, u8 lane, const struct dll_setting *setting); -void dqset(u8 ch, u8 lane, const struct dll_setting *setting); -void rt_set_dqs(u8 channel, u8 lane, u8 rank, struct rt_dqs_setting *dqs_setting); -int do_write_training(struct sysinfo *s); -int do_read_training(struct sysinfo *s); -void search_write_leveling(struct sysinfo *s); -void send_jedec_cmd(const struct sysinfo *s, u8 r, u8 ch, u8 cmd, u32 val); - -extern const struct dll_setting default_ddr2_667_ctrl[7]; -extern const struct dll_setting default_ddr2_800_ctrl[7]; -extern const struct dll_setting default_ddr3_800_ctrl[2][7]; -extern const struct dll_setting default_ddr3_1067_ctrl[2][7]; -extern const struct dll_setting default_ddr3_1333_ctrl[2][7]; -extern const struct dll_setting default_ddr2_667_dqs[TOTAL_BYTELANES]; -extern const struct dll_setting default_ddr2_800_dqs[TOTAL_BYTELANES]; -extern const struct dll_setting default_ddr3_800_dqs[2][TOTAL_BYTELANES]; -extern const struct dll_setting default_ddr3_1067_dqs[2][TOTAL_BYTELANES]; -extern const struct dll_setting default_ddr3_1333_dqs[2][TOTAL_BYTELANES]; -extern const struct dll_setting default_ddr2_667_dq[TOTAL_BYTELANES]; -extern const struct dll_setting default_ddr2_800_dq[TOTAL_BYTELANES]; -extern const struct dll_setting default_ddr3_800_dq[2][TOTAL_BYTELANES]; -extern const struct dll_setting default_ddr3_1067_dq[2][TOTAL_BYTELANES]; -extern const struct dll_setting default_ddr3_1333_dq[2][TOTAL_BYTELANES]; -extern const u8 ddr3_emrs1_rtt_nom_config[16][4]; -extern const u8 post_jedec_tab[3][4][2]; -extern const u32 ddr3_c2_tab[2][3][6][2]; -extern const u8 ddr3_c2_x264[3][6]; -extern const u16 ddr3_c2_x23c[3][6]; #include <device/device.h> struct acpi_rsdp; -- To view, visit https://review.coreboot.org/c/coreboot/+/45424 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I04d8c610d3e52adecfe96cc435f0523bedf3060a Gerrit-Change-Number: 45424 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 6

Change in coreboot[master]: nb/intel/x4x: Move register headers into a subfolder
by Angel Pons (Code Review) 14 Oct '20

14 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45421 ) Change subject: nb/intel/x4x: Move register headers into a subfolder ...................................................................... nb/intel/x4x: Move register headers into a subfolder Move all files with register definitions into a `registers` subfolder. Subsequent commits will move the remaining registers into this folder. Tested with BUILD_TIMELESS=1, Asus P5QL PRO does not change. Change-Id: I74dbd985b980d8a42bfaf2984820005320a803d3 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- R src/northbridge/intel/x4x/registers/host_bridge.h M src/northbridge/intel/x4x/x4x.h 2 files changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/45421/1 diff --git a/src/northbridge/intel/x4x/hostbridge_regs.h b/src/northbridge/intel/x4x/registers/host_bridge.h similarity index 88% rename from src/northbridge/intel/x4x/hostbridge_regs.h rename to src/northbridge/intel/x4x/registers/host_bridge.h index 00b496d..f092404 100644 --- a/src/northbridge/intel/x4x/hostbridge_regs.h +++ b/src/northbridge/intel/x4x/registers/host_bridge.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __X4X_HOSTBRIDGE_REGS_H__ -#define __X4X_HOSTBRIDGE_REGS_H__ +#ifndef __X4X_REGISTERS_HOSTBRIDGE_H__ +#define __X4X_REGISTERS_HOSTBRIDGE_H__ #define D0F0_EPBAR_LO 0x40 #define D0F0_EPBAR_HI 0x44 @@ -37,4 +37,4 @@ #define D0F0_SKPD 0xdc /* Scratchpad Data */ #define D0F0_CAPID0 0xe0 -#endif /* __X4X_HOSTBRIDGE_REGS_H__ */ +#endif /* __X4X_REGISTERS_HOSTBRIDGE_H__ */ diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h index 8e4237d..6df661d 100644 --- a/src/northbridge/intel/x4x/x4x.h +++ b/src/northbridge/intel/x4x/x4x.h @@ -11,7 +11,7 @@ */ #define HOST_BRIDGE PCI_DEV(0, 0, 0) -#include "hostbridge_regs.h" +#include "registers/host_bridge.h" /* * D1:F0 PEG @@ -96,7 +96,7 @@ #define DMIVC0RCTL 0x14 #define DMIVC1RCTL 0x20 #define DMIVC1RSTS 0x26 -#define DMIESD 0x44 +#define DMIESD 0x44 #define DMILE1D 0x50 #define DMILE1A 0x58 #define DMILE2D 0x60 -- To view, visit https://review.coreboot.org/c/coreboot/+/45421 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I74dbd985b980d8a42bfaf2984820005320a803d3 Gerrit-Change-Number: 45421 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: mb/purism/librem_skl: Drop DQ and DQS byte maps
by Angel Pons (Code Review) 14 Oct '20

14 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46251 ) Change subject: mb/purism/librem_skl: Drop DQ and DQS byte maps ...................................................................... mb/purism/librem_skl: Drop DQ and DQS byte maps These settings are not necessary for DDR4 and can be dropped. Change-Id: I1946be239f0c90db995a60570474039cef45cfa9 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/purism/librem_skl/romstage.c 1 file changed, 0 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/46251/1 diff --git a/src/mainboard/purism/librem_skl/romstage.c b/src/mainboard/purism/librem_skl/romstage.c index 7be8325..4982836 100644 --- a/src/mainboard/purism/librem_skl/romstage.c +++ b/src/mainboard/purism/librem_skl/romstage.c @@ -5,28 +5,6 @@ #include <spd_bin.h> #include <string.h> -static void mainboard_fill_dq_map_data(void *dq_map_ch0, void *dq_map_ch1) -{ - /* DQ byte map */ - const u8 dq_map[2][12] = { - { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, - 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 }, - { 0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC, - 0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 } }; - memcpy(dq_map_ch0, dq_map[0], sizeof(dq_map[0])); - memcpy(dq_map_ch1, dq_map[1], sizeof(dq_map[1])); -} - -static void mainboard_fill_dqs_map_data(void *dqs_map_ch0, void *dqs_map_ch1) -{ - /* DQS CPU<>DRAM map */ - const u8 dqs_map[2][8] = { - { 0, 1, 3, 2, 4, 5, 6, 7 }, - { 1, 0, 4, 5, 2, 3, 6, 7 } }; - memcpy(dqs_map_ch0, dqs_map[0], sizeof(dqs_map[0])); - memcpy(dqs_map_ch1, dqs_map[1], sizeof(dqs_map[1])); -} - static void mainboard_fill_rcomp_res_data(void *rcomp_ptr) { /* Rcomp resistor */ @@ -54,10 +32,6 @@ dump_spd_info(&blk); assert(blk.spd_array[0][0] != 0); - mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0, - &mem_cfg->DqByteMapCh1); - mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0, - &mem_cfg->DqsMapCpu2DramCh1); mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor); mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget); -- To view, visit https://review.coreboot.org/c/coreboot/+/46251 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1946be239f0c90db995a60570474039cef45cfa9 Gerrit-Change-Number: 46251 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: nb/intel/haswell: Only hide PEG devices if ONBOARD_VGA_IS_PRIMARY
by Angel Pons (Code Review) 14 Oct '20

14 Oct '20

Angel Pons has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/44923 ) Change subject: nb/intel/haswell: Only hide PEG devices if ONBOARD_VGA_IS_PRIMARY ...................................................................... Abandoned Duplicate of CB:45534 -- To view, visit https://review.coreboot.org/c/coreboot/+/44923 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1d887a1f173b981ed7ba238fe5d7dbe6e1aab565 Gerrit-Change-Number: 44923 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-MessageType: abandon

1 0

Change in coreboot[master]: drivers/intel/gma/acpi: Convert 'common.asl' to ASL 2.0 syntax
by HAOUAS Elyes (Code Review) 14 Oct '20

14 Oct '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45781 ) Change subject: drivers/intel/gma/acpi: Convert 'common.asl' to ASL 2.0 syntax ...................................................................... drivers/intel/gma/acpi: Convert 'common.asl' to ASL 2.0 syntax Generated 'build/dsdt.dsl' are same Change-Id: I67fd585746df1556ceae0a3fdce595c6cf5e0f10 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/drivers/intel/gma/acpi/common.asl 1 file changed, 12 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/45781/1 diff --git a/src/drivers/intel/gma/acpi/common.asl b/src/drivers/intel/gma/acpi/common.asl index 79960e1..1e7d00d 100644 --- a/src/drivers/intel/gma/acpi/common.asl +++ b/src/drivers/intel/gma/acpi/common.asl @@ -6,17 +6,17 @@ Method(BRID, 1, NotSerialized) { - Store (Match (BRIG, MEQ, Arg0, MTR, Zero, 2), Local0) - If (LEqual (Local0, Ones)) + Local0 = Match (BRIG, MEQ, Arg0, MTR, Zero, 2) + If (Local0 == Ones) { - Return (Subtract(SizeOf(BRIG), One)) + Return (SizeOf(BRIG) -1) } Return (Local0) } Method (XBCL, 0, NotSerialized) { - Store (1, BRCT) + BRCT = 1 Return (BRIG) } @@ -37,12 +37,12 @@ { Notify (LCD0, 0x87) } Else { - Store (BRID (XBQC ()), Local0) - If (LNotEqual (Local0, 2)) + Local0 = BRID (XBQC ()) + If (Local0 != 2) { - Decrement (Local0) + Local0-- } - XBCM (DerefOf (Index (BRIG, Local0))) + XBCM (DerefOf (BRIG [Local0])) } } @@ -55,11 +55,11 @@ { Notify (LCD0, 0x86) } Else { - Store (BRID (XBQC ()), Local0) - If (LNotEqual (Local0, Subtract(SizeOf(BRIG), One))) + Local0 = BRID (XBQC ()) + If (Local0 != (SizeOf(BRIG) - 1)) { - Increment (Local0) + Local0++ } - XBCM (DerefOf (Index (BRIG, Local0))) + XBCM (DerefOf (BRIG [Local0])) } } -- To view, visit https://review.coreboot.org/c/coreboot/+/45781 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I67fd585746df1556ceae0a3fdce595c6cf5e0f10 Gerrit-Change-Number: 45781 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 7

Change in coreboot[master]: mb/[*.asl]: Remove unneeded comments and license headers from empty f...
by HAOUAS Elyes (Code Review) 14 Oct '20

14 Oct '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46122 ) Change subject: mb/[*.asl]: Remove unneeded comments and license headers from empty files ...................................................................... mb/[*.asl]: Remove unneeded comments and license headers from empty files Change-Id: I1b2bf0312a559d2ce5dec0042560ee5e62d59c1d Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/acer/g43t-am3/acpi/ec.asl M src/mainboard/amd/olivehill/acpi/sata.asl M src/mainboard/amd/persimmon/acpi/superio.asl M src/mainboard/asrock/g41c-gs/acpi/ec.asl M src/mainboard/asrock/g41c-gs/acpi/superio.asl M src/mainboard/asrock/imb-a180/acpi/sata.asl M src/mainboard/asus/p5gc-mx/acpi/ec.asl M src/mainboard/asus/p5gc-mx/acpi/superio.asl M src/mainboard/asus/p5qc/acpi/ec.asl M src/mainboard/asus/p5ql-em/acpi/ec.asl M src/mainboard/asus/p5qpl-am/acpi/ec.asl M src/mainboard/biostar/a68n_5200/acpi/sata.asl M src/mainboard/elmex/pcm205400/acpi/superio.asl M src/mainboard/foxconn/d41s/acpi/ec.asl M src/mainboard/foxconn/g41s-k/acpi/ec.asl M src/mainboard/gigabyte/ga-945gcm-s2l/acpi/superio.asl M src/mainboard/gigabyte/ga-g41m-es2l/acpi/ec.asl M src/mainboard/gigabyte/ga-g41m-es2l/acpi/superio.asl M src/mainboard/gizmosphere/gizmo/acpi/superio.asl M src/mainboard/gizmosphere/gizmo2/acpi/sata.asl M src/mainboard/hp/abm/acpi/sata.asl M src/mainboard/intel/d510mo/acpi/ec.asl M src/mainboard/intel/d510mo/acpi/superio.asl M src/mainboard/intel/dcp847ske/acpi/ec.asl M src/mainboard/intel/dg41wv/acpi/ec.asl M src/mainboard/intel/dg43gt/acpi/ec.asl M src/mainboard/lenovo/thinkcentre_a58/acpi/ec.asl M src/mainboard/pcengines/apu1/acpi/superio.asl 28 files changed, 0 insertions(+), 37 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/46122/1 diff --git a/src/mainboard/acer/g43t-am3/acpi/ec.asl b/src/mainboard/acer/g43t-am3/acpi/ec.asl index 2997587..e69de29 100644 --- a/src/mainboard/acer/g43t-am3/acpi/ec.asl +++ b/src/mainboard/acer/g43t-am3/acpi/ec.asl @@ -1 +0,0 @@ -/* dummy */ diff --git a/src/mainboard/amd/olivehill/acpi/sata.asl b/src/mainboard/amd/olivehill/acpi/sata.asl index 659a076..f675323 100644 --- a/src/mainboard/amd/olivehill/acpi/sata.asl +++ b/src/mainboard/amd/olivehill/acpi/sata.asl @@ -1,3 +1 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - /* No SATA functionality */ diff --git a/src/mainboard/amd/persimmon/acpi/superio.asl b/src/mainboard/amd/persimmon/acpi/superio.asl index d2d8a44..69c6108 100644 --- a/src/mainboard/amd/persimmon/acpi/superio.asl +++ b/src/mainboard/amd/persimmon/acpi/superio.asl @@ -1,3 +1 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - /* No Super I/O device or functionality yet */ diff --git a/src/mainboard/asrock/g41c-gs/acpi/ec.asl b/src/mainboard/asrock/g41c-gs/acpi/ec.asl index 2997587..e69de29 100644 --- a/src/mainboard/asrock/g41c-gs/acpi/ec.asl +++ b/src/mainboard/asrock/g41c-gs/acpi/ec.asl @@ -1 +0,0 @@ -/* dummy */ diff --git a/src/mainboard/asrock/g41c-gs/acpi/superio.asl b/src/mainboard/asrock/g41c-gs/acpi/superio.asl index 2997587..e69de29 100644 --- a/src/mainboard/asrock/g41c-gs/acpi/superio.asl +++ b/src/mainboard/asrock/g41c-gs/acpi/superio.asl @@ -1 +0,0 @@ -/* dummy */ diff --git a/src/mainboard/asrock/imb-a180/acpi/sata.asl b/src/mainboard/asrock/imb-a180/acpi/sata.asl index 659a076..f675323 100644 --- a/src/mainboard/asrock/imb-a180/acpi/sata.asl +++ b/src/mainboard/asrock/imb-a180/acpi/sata.asl @@ -1,3 +1 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - /* No SATA functionality */ diff --git a/src/mainboard/asus/p5gc-mx/acpi/ec.asl b/src/mainboard/asus/p5gc-mx/acpi/ec.asl index 2997587..e69de29 100644 --- a/src/mainboard/asus/p5gc-mx/acpi/ec.asl +++ b/src/mainboard/asus/p5gc-mx/acpi/ec.asl @@ -1 +0,0 @@ -/* dummy */ diff --git a/src/mainboard/asus/p5gc-mx/acpi/superio.asl b/src/mainboard/asus/p5gc-mx/acpi/superio.asl index 2997587..e69de29 100644 --- a/src/mainboard/asus/p5gc-mx/acpi/superio.asl +++ b/src/mainboard/asus/p5gc-mx/acpi/superio.asl @@ -1 +0,0 @@ -/* dummy */ diff --git a/src/mainboard/asus/p5qc/acpi/ec.asl b/src/mainboard/asus/p5qc/acpi/ec.asl index 2997587..e69de29 100644 --- a/src/mainboard/asus/p5qc/acpi/ec.asl +++ b/src/mainboard/asus/p5qc/acpi/ec.asl @@ -1 +0,0 @@ -/* dummy */ diff --git a/src/mainboard/asus/p5ql-em/acpi/ec.asl b/src/mainboard/asus/p5ql-em/acpi/ec.asl index 2997587..e69de29 100644 --- a/src/mainboard/asus/p5ql-em/acpi/ec.asl +++ b/src/mainboard/asus/p5ql-em/acpi/ec.asl @@ -1 +0,0 @@ -/* dummy */ diff --git a/src/mainboard/asus/p5qpl-am/acpi/ec.asl b/src/mainboard/asus/p5qpl-am/acpi/ec.asl index 2997587..e69de29 100644 --- a/src/mainboard/asus/p5qpl-am/acpi/ec.asl +++ b/src/mainboard/asus/p5qpl-am/acpi/ec.asl @@ -1 +0,0 @@ -/* dummy */ diff --git a/src/mainboard/biostar/a68n_5200/acpi/sata.asl b/src/mainboard/biostar/a68n_5200/acpi/sata.asl index 659a076..f675323 100644 --- a/src/mainboard/biostar/a68n_5200/acpi/sata.asl +++ b/src/mainboard/biostar/a68n_5200/acpi/sata.asl @@ -1,3 +1 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - /* No SATA functionality */ diff --git a/src/mainboard/elmex/pcm205400/acpi/superio.asl b/src/mainboard/elmex/pcm205400/acpi/superio.asl index d2d8a44..69c6108 100644 --- a/src/mainboard/elmex/pcm205400/acpi/superio.asl +++ b/src/mainboard/elmex/pcm205400/acpi/superio.asl @@ -1,3 +1 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - /* No Super I/O device or functionality yet */ diff --git a/src/mainboard/foxconn/d41s/acpi/ec.asl b/src/mainboard/foxconn/d41s/acpi/ec.asl index 31eb392..e69de29 100644 --- a/src/mainboard/foxconn/d41s/acpi/ec.asl +++ b/src/mainboard/foxconn/d41s/acpi/ec.asl @@ -1 +0,0 @@ -/* Dummy file - No license required. */ diff --git a/src/mainboard/foxconn/g41s-k/acpi/ec.asl b/src/mainboard/foxconn/g41s-k/acpi/ec.asl index 2997587..e69de29 100644 --- a/src/mainboard/foxconn/g41s-k/acpi/ec.asl +++ b/src/mainboard/foxconn/g41s-k/acpi/ec.asl @@ -1 +0,0 @@ -/* dummy */ diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/acpi/superio.asl b/src/mainboard/gigabyte/ga-945gcm-s2l/acpi/superio.asl index 2997587..e69de29 100644 --- a/src/mainboard/gigabyte/ga-945gcm-s2l/acpi/superio.asl +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/acpi/superio.asl @@ -1 +0,0 @@ -/* dummy */ diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/acpi/ec.asl b/src/mainboard/gigabyte/ga-g41m-es2l/acpi/ec.asl index 2997587..e69de29 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/acpi/ec.asl +++ b/src/mainboard/gigabyte/ga-g41m-es2l/acpi/ec.asl @@ -1 +0,0 @@ -/* dummy */ diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/acpi/superio.asl b/src/mainboard/gigabyte/ga-g41m-es2l/acpi/superio.asl index 2997587..e69de29 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/acpi/superio.asl +++ b/src/mainboard/gigabyte/ga-g41m-es2l/acpi/superio.asl @@ -1 +0,0 @@ -/* dummy */ diff --git a/src/mainboard/gizmosphere/gizmo/acpi/superio.asl b/src/mainboard/gizmosphere/gizmo/acpi/superio.asl index d2d8a44..69c6108 100644 --- a/src/mainboard/gizmosphere/gizmo/acpi/superio.asl +++ b/src/mainboard/gizmosphere/gizmo/acpi/superio.asl @@ -1,3 +1 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - /* No Super I/O device or functionality yet */ diff --git a/src/mainboard/gizmosphere/gizmo2/acpi/sata.asl b/src/mainboard/gizmosphere/gizmo2/acpi/sata.asl index 659a076..f675323 100644 --- a/src/mainboard/gizmosphere/gizmo2/acpi/sata.asl +++ b/src/mainboard/gizmosphere/gizmo2/acpi/sata.asl @@ -1,3 +1 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - /* No SATA functionality */ diff --git a/src/mainboard/hp/abm/acpi/sata.asl b/src/mainboard/hp/abm/acpi/sata.asl index 659a076..f675323 100644 --- a/src/mainboard/hp/abm/acpi/sata.asl +++ b/src/mainboard/hp/abm/acpi/sata.asl @@ -1,3 +1 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - /* No SATA functionality */ diff --git a/src/mainboard/intel/d510mo/acpi/ec.asl b/src/mainboard/intel/d510mo/acpi/ec.asl index 31eb392..e69de29 100644 --- a/src/mainboard/intel/d510mo/acpi/ec.asl +++ b/src/mainboard/intel/d510mo/acpi/ec.asl @@ -1 +0,0 @@ -/* Dummy file - No license required. */ diff --git a/src/mainboard/intel/d510mo/acpi/superio.asl b/src/mainboard/intel/d510mo/acpi/superio.asl index 31eb392..e69de29 100644 --- a/src/mainboard/intel/d510mo/acpi/superio.asl +++ b/src/mainboard/intel/d510mo/acpi/superio.asl @@ -1 +0,0 @@ -/* Dummy file - No license required. */ diff --git a/src/mainboard/intel/dcp847ske/acpi/ec.asl b/src/mainboard/intel/dcp847ske/acpi/ec.asl index 09f905e..e69de29 100644 --- a/src/mainboard/intel/dcp847ske/acpi/ec.asl +++ b/src/mainboard/intel/dcp847ske/acpi/ec.asl @@ -1 +0,0 @@ -/* Dummy file required by pch.asl - No license necessary. */ diff --git a/src/mainboard/intel/dg41wv/acpi/ec.asl b/src/mainboard/intel/dg41wv/acpi/ec.asl index 2997587..e69de29 100644 --- a/src/mainboard/intel/dg41wv/acpi/ec.asl +++ b/src/mainboard/intel/dg41wv/acpi/ec.asl @@ -1 +0,0 @@ -/* dummy */ diff --git a/src/mainboard/intel/dg43gt/acpi/ec.asl b/src/mainboard/intel/dg43gt/acpi/ec.asl index 2997587..e69de29 100644 --- a/src/mainboard/intel/dg43gt/acpi/ec.asl +++ b/src/mainboard/intel/dg43gt/acpi/ec.asl @@ -1 +0,0 @@ -/* dummy */ diff --git a/src/mainboard/lenovo/thinkcentre_a58/acpi/ec.asl b/src/mainboard/lenovo/thinkcentre_a58/acpi/ec.asl index 2997587..e69de29 100644 --- a/src/mainboard/lenovo/thinkcentre_a58/acpi/ec.asl +++ b/src/mainboard/lenovo/thinkcentre_a58/acpi/ec.asl @@ -1 +0,0 @@ -/* dummy */ diff --git a/src/mainboard/pcengines/apu1/acpi/superio.asl b/src/mainboard/pcengines/apu1/acpi/superio.asl index d2d8a44..69c6108 100644 --- a/src/mainboard/pcengines/apu1/acpi/superio.asl +++ b/src/mainboard/pcengines/apu1/acpi/superio.asl @@ -1,3 +1 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - /* No Super I/O device or functionality yet */ -- To view, visit https://review.coreboot.org/c/coreboot/+/46122 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1b2bf0312a559d2ce5dec0042560ee5e62d59c1d Gerrit-Change-Number: 46122 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: libpayload/x86: Try to discover invariant TSC rate
by Angel Pons (Code Review) 14 Oct '20

14 Oct '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34170 ) Change subject: libpayload/x86: Try to discover invariant TSC rate ...................................................................... Patch Set 4: Code-Review+1 (2 comments) https://review.coreboot.org/c/coreboot/+/34170/4/payloads/libpayload/arch/x… File payloads/libpayload/arch/x86/timer.c: https://review.coreboot.org/c/coreboot/+/34170/4/payloads/libpayload/arch/x… PS4, Line 90: ecx > this seems unneeded, you could just pass nominal for ecx, and if it's 0, perform the model checks `nominal` is a 64-bit variable, though https://review.coreboot.org/c/coreboot/+/34170/4/payloads/libpayload/arch/x… PS4, Line 176: _rdmsr(MSR_PLATFORM_INFO) >> 8 > nit: brackets for readability? Either this or drop the brackets in the return statement -- To view, visit https://review.coreboot.org/c/coreboot/+/34170 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic6607ee2a8b41c2be9dc1bb4f1e23e652bb33889 Gerrit-Change-Number: 34170 Gerrit-PatchSet: 4 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 14 Oct 2020 08:53:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/skylake: Rename PcieRpAspm devicetree config
by Frans Hendriks (Code Review) 14 Oct '20

14 Oct '20

Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45001 ) Change subject: soc/intel/skylake: Rename PcieRpAspm devicetree config ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/45001 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id74f043ecd549bde4501320bff1dc080bde64057 Gerrit-Change-Number: 45001 Gerrit-PatchSet: 5 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 14 Oct 2020 08:47:30 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit October 2020