coreboot-gerrit October 2020

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Change in coreboot[master]: soc/intel/common: drop default to enable the PIT if SeaBIOS is chosen
by Gerd Hoffmann (Code Review) 14 Oct '20

14 Oct '20

Gerd Hoffmann has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46301 ) Change subject: soc/intel/common: drop default to enable the PIT if SeaBIOS is chosen ...................................................................... Patch Set 1: Well. Sure that actually works? The pmtimer is used in case seabios runs on qemu and initializes the (virtual) acpi pci device. I doubt this also happens when running as coreboot payload. The TSC needs calibration, and seabios uses the PIT for that I think. Except when running virtualized on KVM, in that case (new enough) seabios can use kvmclock to figure the TSC frequency. -- To view, visit https://review.coreboot.org/c/coreboot/+/46301 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd75800678707a92110682347c7cfb93e25109a4 Gerrit-Change-Number: 46301 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Gerd Hoffmann <kraxel(a)redhat.com> Gerrit-Reviewer: Kevin O'Connor <kevin(a)koconnor.net> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 14 Oct 2020 08:17:25 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: nb/intel/haswell: Account for DPR region in memory map
by Arthur Heymans (Code Review) 14 Oct '20

14 Oct '20

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45712 ) Change subject: nb/intel/haswell: Account for DPR region in memory map ...................................................................... Patch Set 10: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/45712 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I11f23fd43188f987e35fd61f52587e567496cd78 Gerrit-Change-Number: 45712 Gerrit-PatchSet: 10 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 14 Oct 2020 07:31:00 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/poppy/variant/atlas: Reset bluetooth on boot
by Caveh Jalali (Code Review) 14 Oct '20

14 Oct '20

Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46120 ) Change subject: mb/google/poppy/variant/atlas: Reset bluetooth on boot ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/c/coreboot/+/46120/2/src/mainboard/google/poppy… File src/mainboard/google/poppy/variants/atlas/gpio.c: https://review.coreboot.org/c/coreboot/+/46120/2/src/mainboard/google/poppy… PS2, Line 335: early_gpio_table > Then this won't take effect. The early GPIO table is programmed in bootblock. that's unfortunate. so, we basically can't do this here for the installed base. i think that puts more weight on getting the BT driver to handle firmware updates. quick hack is probably to have the chromeos updater reboot at the EC on atlas. -- To view, visit https://review.coreboot.org/c/coreboot/+/46120 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I361caa49e82aa086c3c35962164fb078fa30139e Gerrit-Change-Number: 46120 Gerrit-PatchSet: 2 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 14 Oct 2020 07:08:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Caveh Jalali <caveh(a)chromium.org> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/getac/p470/acpi: Convert 'thermal.asl' to ASL 2.0 syntax
by HAOUAS Elyes (Code Review) 14 Oct '20

14 Oct '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45559 ) Change subject: mb/getac/p470/acpi: Convert 'thermal.asl' to ASL 2.0 syntax ...................................................................... mb/getac/p470/acpi: Convert 'thermal.asl' to ASL 2.0 syntax Change-Id: I08c6d706aa409563cf2c407352e8de5ecc994bda Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/getac/p470/acpi/thermal.asl 1 file changed, 9 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/45559/1 diff --git a/src/mainboard/getac/p470/acpi/thermal.asl b/src/mainboard/getac/p470/acpi/thermal.asl index 6e3dc22..4e31ef3 100644 --- a/src/mainboard/getac/p470/acpi/thermal.asl +++ b/src/mainboard/getac/p470/acpi/thermal.asl @@ -17,11 +17,11 @@ // Convert from °C to 1/10 Kelvin Method(DEGR, 1, NotSerialized) { - Store(Arg0, Local0) + Local0 = Arg0 // 10ths of degrees - Multiply(Local0, 10, Local0) + Local0 *= 10 // 0°C is 273.15 K, we need to round it. - Add(Local0, 2732, Local0) + Local0 += 2732 Return(Local0) } @@ -35,24 +35,24 @@ // Critical shutdown temperature Method (_CRT, 0, Serialized) { - Store(\_SB.PCI0.LPCB.EC0.CRTT, Local0) - Store(DEGR(Local0), Local0) + Local0 = \_SB.PCI0.LPCB.EC0.CRTT + Local0 = DEGR (Local0) Return(Local0) } // CPU throttling start temperature Method (_PSV, 0, Serialized) { - Store(\_SB.PCI0.LPCB.EC0.CTRO, Local0) - Store(DEGR(Local0), Local0) + Local0 = \_SB.PCI0.LPCB.EC0.CTRO + Local0 = DEGR (Local0) Return(Local0) } // Get DTS Temperature Method (_TMP, 0, Serialized) { - Store(\_SB.PCI0.LPCB.EC0.CTMP, Local0) - Store(DEGR(Local0), Local0) + Local0 = \_SB.PCI0.LPCB.EC0.CTMP + Local0 = DEGR (Local0) Return(Local0) } -- To view, visit https://review.coreboot.org/c/coreboot/+/45559 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I08c6d706aa409563cf2c407352e8de5ecc994bda Gerrit-Change-Number: 45559 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/getac/p470/acpi: Convert 'superio.asl' to ASL 2.0 syntax
by HAOUAS Elyes (Code Review) 14 Oct '20

14 Oct '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45558 ) Change subject: mb/getac/p470/acpi: Convert 'superio.asl' to ASL 2.0 syntax ...................................................................... mb/getac/p470/acpi: Convert 'superio.asl' to ASL 2.0 syntax Change-Id: I620b9d3befd0a1a1440c6cc8908214b7b7a233bc Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/getac/p470/acpi/superio.asl 1 file changed, 174 insertions(+), 171 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/45558/1 diff --git a/src/mainboard/getac/p470/acpi/superio.asl b/src/mainboard/getac/p470/acpi/superio.asl index 705b2b9..342aae8 100644 --- a/src/mainboard/getac/p470/acpi/superio.asl +++ b/src/mainboard/getac/p470/acpi/superio.asl @@ -19,13 +19,13 @@ Method (READ, 3) { Acquire (SIOM, 0xffff) - If (LEqual(Arg0, 0)) { - Store (0x55, INDX) - Store (Arg1, INDX) - Store (DATA, Local1) - Store (0xaa, INDX) + If (Arg0 == 0) { + INDX = 0x55 + INDX = Arg1 + Local1 = DATA + INDX = 0xaa } - And (Local1, Arg2, Local1) + Local1 &= Arg2 Release(SIOM) Return(Local1) } @@ -33,11 +33,11 @@ Method (WRIT, 3) { Acquire (SIOM, 0xffff) - If (LEqual(Arg0, 0)) { - Store (0x55, INDX) - Store (Arg1, INDX) - Store (Arg2, DATA) - Store (0xaa, INDX) + If (Arg0 == 0) { + INDX = 0x55 + INDX = Arg1 + DATA = Arg2 + INDX = 0xaa } Release(SIOM) } @@ -55,13 +55,13 @@ Acquire (SIOM, 0xffff) // Is the hardware enabled? - Store (READ(0, 0x24, 0xff), Local0) - If (LEqual(Local0, 0)) { + Local0 = READ (0, 0x24, 0xff) + If (Local0 == 0) { Return (0xd) } Else { // Power Enabled? - Store (READ(0, 0x02, 0x08), Local0) - If (LEqual(Local0, 0)) { + Local0 = READ (0, 0x02, 0x08) + If (Local0 == 0) { Return (0x0d) } Else { Return (0x0f) @@ -74,12 +74,12 @@ { WRIT(0, 0x24, 0x00) - Store(READ(0, 0x28, 0x0f), Local0) + Local0 = READ (0, 0x28, 0x0f) WRIT(0, 0x28, Local0) - Store(READ(0, 0x02, 0xff), Local0) - Not(0x08, Local1) - And(Local0, Local1, Local0) + Local0 = READ (0, 0x02, 0xff) + Local1 = ~0x08 + Local0 &= Local1 WRIT(0, 0x02, Local0) } @@ -104,8 +104,8 @@ IRQNoFlags(_IRA) { 4 } }) - And (_STA(), 0x02, Local0) - If (LEqual(Local0, 0)) { + Local0 = (_STA () & 0x02) + If (Local0 == 0) { Return(NONE) } @@ -117,15 +117,16 @@ \_SB.PCI0.LPCB.SIO1.UAR1._CRS._IRA._INT, IRQ) /* I/O Base */ - Store (READ(0, 0x24, 0xfe), Local0) + Local0 = READ (0, 0x24, 0xfe) ShiftLeft(Local0, 0x02, Local0) - Store(Local0, IOMN) - Store(Local0, IOMX) + Local0 <<= 2 + IOMN = Local0 + IOMX = Local0 /* Interrupt */ - Store(READ(0, 0x28, 0xf0), Local0) - ShiftRight(Local0, 4, Local0) - ShiftLeft(1, Local0, IRQ) + Local0 = READ (0, 0x28, 0xf0) + Local0 >>= 4 + IRQ = 1 << Local0 Return(RSRC) } @@ -138,29 +139,29 @@ WRIT(0, 0x24, 0) FindSetRightBit(IRQL, Local0) - Decrement(Local0) - ShiftLeft(Local0, 4, Local0) + Local0-- + Local0 <<= 4 - Store(READ(0, 0x28, 0x0f), Local1) - Or(Local0, Local1, Local0) + Local1 = READ (0, 0x28, 0x0f) + Local0 |= Local1 WRIT(0, 0x28, Local0) - Store(IOLO, Local0) - ShiftRight(Local0, 2, Local0) - And(Local0, 0xfe, Local0) + Local0 = IOLO + Local0 >>= 2 + Local0 &= 0xfe - Store(IOHI, Local1) - ShiftLeft(Local1, 6, Local1) - Or (Local0, Local1, Local0) + Local1 = IOHI + Local1 <<= 6 + Local0 |= Local1 WRIT(0, 0x24, Local0) - Store(READ(0, 0x02, 0xff), Local0) - Or(Local0, 0x08, Local0) + Local0 = READ (0, 0x02, 0xff) + Local0 |= 0x08 WRIT(0, 0x02, Local0) - Store(READ(0, 0x07, 0xff), Local0) - Not(0x40, Local1) - And (Local0, Local1, Local0) + Local0 = READ (0, 0x07, 0xff) + Local1 = ~0x40 + Local0 &= Local1 WRIT(0, 0x07, Local0) } @@ -168,22 +169,23 @@ /* D0 state - Line drivers are on */ Method (_PS0, 0) { - Store(READ(0, 0x02, 0xff), Local0) - Or(Local0, 0x08, Local0) + Local0 = READ (0, 0x02, 0xff) + Local0 |= 0x08 WRIT(0, 0x02, Local0) - Store (READ(0, 0x07, 0xff), Local0) - Not(0x40, Local1) - And(Local0, Local1, Local0) + Local0 = READ (0, 0x07, 0xff) + Local1 = ~0x40 + Local0 &= Local1 WRIT(0, 0x07, Local0) } /* D3 State - Line drivers are off */ Method(_PS3, 0) { - Store(READ(0, 0x02, 0xff), Local0) + Local0 = READ (0, 0x02, 0xff) + Local1 = ~0x08 Not(0x08, Local1) - And(Local0, Local1, Local0) + Local0 &= Local1 WRIT(0, 0x02, Local0) } } @@ -200,18 +202,18 @@ { /* IRDA? */ Store(READ(0, 0x0c, 0x38), Local0) - If (LNotEqual(Local0, Zero)) { + If (Local0 != 0) { Return (0) } // Is the hardware enabled? - Store (READ(0, 0x25, 0xff), Local0) - If (LEqual(Local0, 0)) { + Local0 = READ (0, 0x25, 0xff) + If (Local0 == 0) { Return (0xd) } Else { // Power Enabled? - Store (READ(0, 0x02, 0x80), Local0) - If (LEqual(Local0, 0)) { + Local0 = READ (0, 0x02, 0x80) + If (Local0 == 0) { Return (0x0d) } Else { Return (0x0f) @@ -224,12 +226,12 @@ { WRIT(0, 0x25, 0x00) - Store(READ(0, 0x28, 0xf0), Local0) + Local0 = READ (0, 0x28, 0xf0) WRIT(0, 0x28, Local0) - Store(READ(0, 0x02, 0xff), Local0) - Not(0x80, Local1) - And(Local0, Local1, Local0) + Local0 = READ (0, 0x02, 0xff) + Local1 = ~0x80 + Local0 &= Local1 WRIT(0, 0x02, Local0) } @@ -254,8 +256,8 @@ IRQNoFlags(_IRB) { 3 } }) - And (_STA(), 0x02, Local0) - If (LEqual(Local0, 0)) { + Local0 = _STA () & 0x02 + If (Local0 == 0) { Return(NONE) } @@ -267,15 +269,15 @@ \_SB.PCI0.LPCB.SIO1.UAR2._CRS._IRB._INT, IRQ) /* I/O Base */ - Store (READ(0, 0x25, 0xfe), Local0) - ShiftLeft(Local0, 0x02, Local0) - Store(Local0, IOMN) - Store(Local0, IOMX) + Local0 = READ (0, 0x25, 0xfe) + Local0 <<= 2 + IOMN = Local0 + IOMX = Local0 /* Interrupt */ - Store(READ(0, 0x28, 0x0f), Local0) - ShiftRight(Local0, 4, Local0) - ShiftLeft(1, Local0, IRQ) + Local0 = READ (0, 0x28, 0x0f) + Local0 >>= 4 + IRQ = 1 << Local0 Return(RSRC) } @@ -288,55 +290,55 @@ WRIT(0, 0x25, 0) FindSetRightBit(IRQL, Local0) - Decrement(Local0) + Local0-- - Store(READ(0, 0x28, 0xf0), Local1) - Or(Local0, Local1, Local0) + Local1 = READ (0x00, 0x28, 0xf0) + Local0 |= Local1 WRIT(0, 0x28, Local0) - Store(IOLO, Local0) - ShiftRight(Local0, 2, Local0) - And(Local0, 0xfe, Local0) + Local0 = IOLO + Local0 >>= 2 + Local0 &= 0xfe - Store(IOHI, Local1) - ShiftLeft(Local1, 6, Local1) - Or (Local0, Local1, Local0) + Local1 = IOHI + Local1 <<= 6 + Local0 |= Local1 WRIT(0, 0x25, Local0) - Store(READ(0, 0x0c, 0xff), Local0) - Not(0x38, Local1) - And(Local0, Local1, Local0) + Local0 = READ (0, 0x0c, 0xff) + Local1 = ~0x38 + Local0 &= Local1 WRIT(0, 0x0c, Local0) - Store(READ(0, 0x02, 0xff), Local0) - Or(Local0, 0x80, Local0) + Local0 = READ (0, 0x02, 0xff) + Local0 |= 0x80 WRIT(0, 0x02, Local0) - Store(READ(0, 0x07, 0xff), Local0) - Not(0x20, Local1) - And (Local0, Local1, Local0) + Local0 = READ (0, 0x07, 0xff) + Local1 = ~0x20 + Local0 &= Local1 WRIT(0, 0x07, Local0) } /* D0 state - Line drivers are on */ Method (_PS0, 0) { - Store(READ(0, 0x02, 0xff), Local0) - Or(Local0, 0x80, Local0) + Local0 = READ (0, 0x02, 0xff) + Local0 |= 0x80 WRIT(0, 0x02, Local0) - Store (READ(0, 0x07, 0xff), Local0) - Not(0x20, Local1) - And(Local0, Local1, Local0) + Local0 = READ (0, 0x07, 0xff) + Local1 = ~0x20 + Local0 &= Local1 WRIT(0, 0x07, Local0) } /* D3 State - Line drivers are off */ Method(_PS3, 0) { - Store(READ(0, 0x02, 0xff), Local0) - Not(0x80, Local1) - And(Local0, Local1, Local0) + Local0 = READ (0, 0x02, 0xff) + Local1 = ~0x80 + Local0 &= Local1 WRIT(0, 0x02, Local0) } } @@ -354,13 +356,13 @@ Acquire (SIOM, 0xffff) // Is the hardware enabled? - Store (READ(0, 0x1b, 0xff), Local0) - If (LEqual(Local0, 0)) { + Local0 = READ (0, 0x1b, 0xff) + If (Local0 == 0) { Return (0xd) } Else { // Power Enabled? - Store (READ(0, 0x02, 0x02), Local0) - If (LEqual(Local0, 0)) { + Local0 = READ (0, 0x02, 0x02) + If (Local0 == 0) { Return (0x0d) } Else { Return (0x0f) @@ -373,12 +375,12 @@ { WRIT(0, 0x1b, 0x00) - Store(READ(0, 0x1d, 0x0f), Local0) + Local0 = READ (0, 0x1d, 0x0f) WRIT(0, 0x1d, Local0) - Store(READ(0, 0x02, 0xff), Local0) - Not(0x02, Local1) - And(Local0, Local1, Local0) + Local0 = READ (0, 0x02, 0xff) + Local1 = ~0x02 + Local0 &= Local1 WRIT(0, 0x02, Local0) } @@ -403,8 +405,8 @@ IRQNoFlags(_IRA) { 5 } }) - And (_STA(), 0x02, Local0) - If (LEqual(Local0, 0)) { + Local0 = _STA () & 0x02 + If (Local0 == 0) { Return(NONE) } @@ -416,15 +418,15 @@ \_SB.PCI0.LPCB.SIO1.UAR3._CRS._IRA._INT, IRQ) /* I/O Base */ - Store (READ(0, 0x1b, 0xfe), Local0) - ShiftLeft(Local0, 0x02, Local0) - Store(Local0, IOMN) - Store(Local0, IOMX) + Local0 = READ (0x00, 0x1b, 0xfe) + Local0 <<= 2 + IOMN = Local0 + IOMX = Local0 /* Interrupt */ - Store(READ(0, 0x1d, 0xf0), Local0) - ShiftRight(Local0, 4, Local0) - ShiftLeft(1, Local0, IRQ) + Local0 = READ (0, 0x1d, 0xf0) + Local0 >>= 4 + IRQ = 1 << Local0 Return(RSRC) } @@ -437,29 +439,30 @@ WRIT(0, 0x1b, 0) FindSetRightBit(IRQL, Local0) - Decrement(Local0) - ShiftLeft(Local0, 4, Local0) + Local0-- + Local0 <<= 4 - Store(READ(0, 0x1d, 0x0f), Local1) - Or(Local0, Local1, Local0) + Local1 = READ (0, 0x1d, 0x0f) + Local0 |= Local1 WRIT(0, 0x1d, Local0) - Store(IOLO, Local0) - ShiftRight(Local0, 2, Local0) + Local0 = IOLO + Local0 >>= 2 + Local0 &= 0xfe And(Local0, 0xfe, Local0) - Store(IOHI, Local1) - ShiftLeft(Local1, 6, Local1) - Or (Local0, Local1, Local0) + Local1 = IOHI + Local1 <<= 6 + Local0 |= Local1 WRIT(0, 0x1b, Local0) - Store(READ(0, 0x02, 0xff), Local0) - Or(Local0, 0x02, Local0) + Local0 = READ (0, 0x02, 0xff) + Local0 |= 0x02 WRIT(0, 0x02, Local0) - Store(READ(0, 0x07, 0xff), Local0) - Not(0x04, Local1) - And (Local0, Local1, Local0) + Local0 = READ (0, 0x07, 0xff) + Local1 = ~0x04 + Local0 &= Local1 WRIT(0, 0x07, Local0) } @@ -467,22 +470,22 @@ /* D0 state - Line drivers are on */ Method (_PS0, 0) { - Store(READ(0, 0x02, 0xff), Local0) - Or(Local0, 0x02, Local0) + Local0 = READ (0, 0x02, 0xff) + Local0 |= 0x02 WRIT(0, 0x02, Local0) - Store (READ(0, 0x07, 0xff), Local0) - Not(0x04, Local1) - And(Local0, Local1, Local0) + Local0 = READ (0, 0x07, 0xff) + Local1 = ~0x04 + Local0 &= Local1 WRIT(0, 0x07, Local0) } /* D3 State - Line drivers are off */ Method(_PS3, 0) { - Store(READ(0, 0x02, 0xff), Local0) - Not(0x02, Local1) - And(Local0, Local1, Local0) + Local0 = READ (0, 0x02, 0xff) + Local1 = ~0x02 + Local0 &= Local1 WRIT(0, 0x02, Local0) } } @@ -501,13 +504,13 @@ Acquire (SIOM, 0xffff) // Is the hardware enabled? - Store (READ(0, 0x1c, 0xff), Local0) - If (LEqual(Local0, 0)) { + Local0 = READ (0, 0x1c, 0xff) + If (Local0 == 0) { Return (0xd) } Else { // Power Enabled? - Store (READ(0, 0x02, 0x04), Local0) - If (LEqual(Local0, 0)) { + Local0 = READ (0, 0x02, 0x04) + If (Local0 == 0) { Return (0x0d) } Else { Return (0x0f) @@ -520,12 +523,12 @@ { WRIT(0, 0x1c, 0x00) - Store(READ(0, 0x1d, 0x0f), Local0) + Local0 = READ (0, 0x1d, 0x0f) WRIT(0, 0x1d, Local0) - Store(READ(0, 0x02, 0xff), Local0) - Not(0x04, Local1) - And(Local0, Local1, Local0) + Local0 = READ (0, 0x02, 0xff) + Local1 = ~0x04 + Local0 &= Local1 WRIT(0, 0x02, Local0) } @@ -550,8 +553,8 @@ IRQNoFlags(_IRA) { 11 } }) - And (_STA(), 0x02, Local0) - If (LEqual(Local0, 0)) { + Local0 = _STA () & 0x02 + If (Local0 == 0) { Return(NONE) } @@ -563,15 +566,15 @@ \_SB.PCI0.LPCB.SIO1.UAR4._CRS._IRA._INT, IRQ) /* I/O Base */ - Store (READ(0, 0x1c, 0xfe), Local0) - ShiftLeft(Local0, 0x02, Local0) - Store(Local0, IOMN) - Store(Local0, IOMX) + Local0 = READ (0, 0x1c, 0xfe) + Local0 <<= 2 + IOMN = Local0 + IOMX = Local0 /* Interrupt */ - Store(READ(0, 0x1d, 0xf0), Local0) - ShiftRight(Local0, 4, Local0) - ShiftLeft(1, Local0, IRQ) + Local0 = READ (0, 0x1d, 0xf0) + Local0 >>= 4 + IRQ = 1 << Local0 Return(RSRC) } @@ -584,29 +587,29 @@ WRIT(0, 0x1c, 0) FindSetRightBit(IRQL, Local0) - Decrement(Local0) - ShiftLeft(Local0, 4, Local0) + Local0-- + Local0 <<= 4 - Store(READ(0, 0x1d, 0x0f), Local1) - Or(Local0, Local1, Local0) + Local1 = READ (0x00, 0x1d, 0x0f) + Local0 |= Local1 WRIT(0, 0x1d, Local0) - Store(IOLO, Local0) - ShiftRight(Local0, 2, Local0) - And(Local0, 0xfe, Local0) + Local0 = IOLO + Local0 >>= 2 + Local0 &= 0xfe - Store(IOHI, Local1) - ShiftLeft(Local1, 6, Local1) - Or (Local0, Local1, Local0) + Local1 = IOHI + Local1 <<= 6 + Local0 |= Local1 WRIT(0, 0x1c, Local0) - Store(READ(0, 0x02, 0xff), Local0) - Or(Local0, 0x04, Local0) + Local0 = READ (0, 0x02, 0xff) + Local0 |= 0x04 WRIT(0, 0x02, Local0) - Store(READ(0, 0x07, 0xff), Local0) - Not(0x08, Local1) - And (Local0, Local1, Local0) + Local0 = READ (0, 0x07, 0xff) + Local1 = ~0x08 + Local0 &= Local1 WRIT(0, 0x07, Local0) } @@ -614,22 +617,22 @@ /* D0 state - Line drivers are on */ Method (_PS0, 0) { - Store(READ(0, 0x02, 0xff), Local0) - Or(Local0, 0x04, Local0) + Local0 = READ (0, 0x02, 0xff) + Local0 |= 0x04 WRIT(0, 0x02, Local0) - Store (READ(0, 0x07, 0xff), Local0) - Not(0x08, Local1) - And(Local0, Local1, Local0) + Local0 = READ (0, 0x07, 0xff) + Local1 = ~0x08 + Local0 &= Local1 WRIT(0, 0x07, Local0) } /* D3 State - Line drivers are off */ Method(_PS3, 0) { - Store(READ(0, 0x02, 0xff), Local0) - Not(0x04, Local1) - And(Local0, Local1, Local0) + Local0 = READ (0, 0x02, 0xff) + Local1 = ~0x04 + Local0 &= Local1 WRIT(0, 0x02, Local0) } } -- To view, visit https://review.coreboot.org/c/coreboot/+/45558 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I620b9d3befd0a1a1440c6cc8908214b7b7a233bc Gerrit-Change-Number: 45558 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 4

Change in coreboot[master]: mb/getac/p470/acpi: Convert 'platform.asl' to ASL 2.0 syntax
by HAOUAS Elyes (Code Review) 14 Oct '20

14 Oct '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45557 ) Change subject: mb/getac/p470/acpi: Convert 'platform.asl' to ASL 2.0 syntax ...................................................................... mb/getac/p470/acpi: Convert 'platform.asl' to ASL 2.0 syntax Change-Id: I41778aff742749934da1ed122f3aa13821638604 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/getac/p470/acpi/platform.asl 1 file changed, 21 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/45557/1 diff --git a/src/mainboard/getac/p470/acpi/platform.asl b/src/mainboard/getac/p470/acpi/platform.asl index 98cecbc..3c092cf 100644 --- a/src/mainboard/getac/p470/acpi/platform.asl +++ b/src/mainboard/getac/p470/acpi/platform.asl @@ -9,23 +9,23 @@ TRAP(0xed) Sleep(1000) - Store(0, \_SB.ACFG) + \_SB.ACFG = 0 // Are we going to S4? - If (Lequal(Arg0, 4)) { + If (Arg0 == 4) { TRAP(0xe7) TRAP(0xea) } // Are we going to S5? - If (Lequal(Arg0, 5)) { + If (Arg0 == 5) { TRAP(0xde) } // The 2.6.12.5 ACPI engine seems to optimize the - // If(LEqual(Arg0, 5)) path away. This keeps it from doing so: + // If((Arg0 == 5) path away. This keeps it from doing so: TRAP(Arg0) - Store(Arg0, DBG0) + Arg0, DBG0 = Arg0 // End of ugly OS bug workaround } @@ -34,12 +34,12 @@ Method(_WAK,1) { // Enable GPS - Store (1, GP11) // GPSE + GP11 = 1 // GPSE // Wake from S3 or S4? - If (LOr(LEqual(Arg0, 3), LEqual(Arg0, 4))) { - If (And(CFGD, 0x01000000)) { - If (LAnd(And(CFGD, 0xf0), LEqual(OSYS, 2001))) { + If ((Arg0 == 0x03) || (Arg0 == 0x04)) { + If (CFGD & 0x01000000) { + If ((CFGD & 0xF0) && (OSYS == 2001)) { TRAP(0x3d) } } @@ -48,26 +48,26 @@ // Notify PCI Express slots in case a card // was inserted while a sleep state was active. - If (LEqual(RP1D, 0)) { + If (RP1D == 0) { Notify(\_SB.PCI0.RP01, 0) } - If (LEqual(RP3D, 0)) { + If (RP3D == 0) { Notify(\_SB.PCI0.RP03, 0) } - If (LEqual(RP4D, 0)) { + If (RP4D == 0) { Notify(\_SB.PCI0.RP04, 0) } // Are we coming from S3? - If (LEqual(Arg0, 3)) { + If (Arg0 == 3) { TRAP(0xeb) TRAP(0x46) } // Are we coming from S4? - If (LEqual(Arg0, 4)) { + If (Arg0 == 4) { Notify(SLPB, 0x02) If (DTSE) { TRAP(0x47) @@ -75,16 +75,16 @@ } // Windows XP SP2 P-State restore - If (LAnd(LEqual(OSYS, 2002), And(CFGD, 1))) { - If (LGreater(\_SB.CP00._PPC, 0)) { - Subtract(\_SB.CP00._PPC, 1, \_SB.CP00._PPC) + If ((OSYS == 2002) && (CFGD & 0x01)) { + If (\_SB.CP00._PPC > 0) { + \_SB.CP00._PPC -= 1 PNOT() - Add(\_SB.CP00._PPC, 1, \_SB.CP00._PPC) + \_SB.CP00._PPC += 1 PNOT() } Else { - Add(\_SB.CP00._PPC, 1, \_SB.CP00._PPC) + \_SB.CP00._PPC += 1 PNOT() - Subtract(\_SB.CP00._PPC, 1, \_SB.CP00._PPC) + \_SB.CP00._PPC -= 1 PNOT() } } @@ -118,7 +118,7 @@ * running: Windows XP SP1 needs to have C-State coordination * enabled in SMM. */ - If (LAnd(LEqual(OSYS, 2001), MPEN)) { + If ((OSYS == 0x07D1) && MPEN) { TRAP(0x3d) } -- To view, visit https://review.coreboot.org/c/coreboot/+/45557 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I41778aff742749934da1ed122f3aa13821638604 Gerrit-Change-Number: 45557 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 4

Change in coreboot[master]: soc/intel/jasperlake: Set the GpioOverride configuration
by Ronak Kanabar (Code Review) 14 Oct '20

14 Oct '20

Ronak Kanabar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45901 ) Change subject: soc/intel/jasperlake: Set the GpioOverride configuration ...................................................................... Patch Set 8: (1 comment) https://review.coreboot.org/c/coreboot/+/45901/6/src/soc/intel/jasperlake/r… File src/soc/intel/jasperlake/romstage/fsp_params.c: https://review.coreboot.org/c/coreboot/+/45901/6/src/soc/intel/jasperlake/r… PS6, Line 120: /* Set GpioOverride */ > I think it would be helpful to have a comment that explains what setting this UPD does. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/45901 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia4036cf0be3a6036d70920743958dc327a652077 Gerrit-Change-Number: 45901 Gerrit-PatchSet: 8 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 14 Oct 2020 05:44:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/jasperlake: Set the GpioOverride configuration
by Ronak Kanabar (Code Review) 14 Oct '20

14 Oct '20

Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Maulik V Vaghela, Angel Pons, Subrata Banik, Aamir Bohra, Patrick Rudolph, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/45901 to look at the new patch set (#8). Change subject: soc/intel/jasperlake: Set the GpioOverride configuration ...................................................................... soc/intel/jasperlake: Set the GpioOverride configuration Set "GpioOverride" config to override FSP gpio configuration. FSP will not configure any GPIOs and rely on GPIO setings before moved to FSP. BUG=b:150666058 TEST=Build and boot JSLRVP Change-Id: Ia4036cf0be3a6036d70920743958dc327a652077 Signed-off-by: Ronak Kanabar <ronak.kanabar(a)intel.com> --- M src/soc/intel/jasperlake/romstage/fsp_params.c 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/45901/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/45901 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia4036cf0be3a6036d70920743958dc327a652077 Gerrit-Change-Number: 45901 Gerrit-PatchSet: 8 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: acpi/device: Add GPIO binding property for an array of GPIOs
by Karthik Ramasubramanian (Code Review) 14 Oct '20

14 Oct '20

Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46056 ) Change subject: acpi/device: Add GPIO binding property for an array of GPIOs ...................................................................... acpi/device: Add GPIO binding property for an array of GPIOs This change is required for use-cases like GPIO based I2C multiplexer where more than one GPIOs are used as select lines. BUG=b:169444894 TEST=Build and boot waddledee to OS. Ensure that the GPIO bindings for an array of GPIOs are added to the ACPI table as follows: Device (MUX0) { ... Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings { GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, IoRestrictionOutputOnly, "\\_SB.PCI0.GPIO", 0x00, ResourceConsumer, , ) { // Pin list 0x0125 } GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, IoRestrictionOutputOnly, "\\_SB.PCI0.GPIO", 0x00, ResourceConsumer, , ) { // Pin list 0x0126 } }) Name (_DSD, Package (0x02) // _DSD: Device-Specific Data { ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties for _DSD */, Package (0x01) { Package (0x02) { "mux-gpios", Package (0x08) { \_SB.PCI0.I2C3.MUX0, Zero, Zero, Zero, \_SB.PCI0.I2C3.MUX0, One, Zero, Zero } } } }) } Change-Id: I7c6cc36b1bfca2d48c84f169e6b43fd4be8ba330 Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/acpi/device.c M src/include/acpi/acpi_device.h 2 files changed, 40 insertions(+), 23 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/46056/1 diff --git a/src/acpi/device.c b/src/acpi/device.c index 450427d..06002c9 100644 --- a/src/acpi/device.c +++ b/src/acpi/device.c @@ -1019,33 +1019,45 @@ return dp_array; } +struct acpi_dp *acpi_dp_add_gpio_array(struct acpi_dp *dp, const char *name, + const char *ref, int index, int pin, + uint32_t gpio_count, int active_low) +{ + struct acpi_dp *gpio; + uint32_t i; + + if (!dp || !gpio_count) + return NULL; + + gpio = acpi_dp_new_table(name); + if (!gpio) + return NULL; + + for (i = 0; i < gpio_count; i++) { + /* The device that has _CRS containing GpioIO()/GpioInt() */ + acpi_dp_add_reference(gpio, NULL, ref); + + /* Index of the GPIO resource in _CRS starting from zero */ + acpi_dp_add_integer(gpio, NULL, index + i); + + /* Pin in the GPIO resource, typically zero */ + acpi_dp_add_integer(gpio, NULL, pin); + + /* Set if pin is active low */ + acpi_dp_add_integer(gpio, NULL, active_low); + } + acpi_dp_add_array(dp, gpio); + + return gpio; + +} + + struct acpi_dp *acpi_dp_add_gpio(struct acpi_dp *dp, const char *name, const char *ref, int index, int pin, int active_low) { - if (!dp) - return NULL; - - struct acpi_dp *gpio = acpi_dp_new_table(name); - - if (!gpio) - return NULL; - - /* The device that has _CRS containing GpioIO()/GpioInt() */ - acpi_dp_add_reference(gpio, NULL, ref); - - /* Index of the GPIO resource in _CRS starting from zero */ - acpi_dp_add_integer(gpio, NULL, index); - - /* Pin in the GPIO resource, typically zero */ - acpi_dp_add_integer(gpio, NULL, pin); - - /* Set if pin is active low */ - acpi_dp_add_integer(gpio, NULL, active_low); - - acpi_dp_add_array(dp, gpio); - - return gpio; + return acpi_dp_add_gpio_array(dp, name, ref, index, pin, 1, active_low); } /* diff --git a/src/include/acpi/acpi_device.h b/src/include/acpi/acpi_device.h index be13bd7..6fcdc2d 100644 --- a/src/include/acpi/acpi_device.h +++ b/src/include/acpi/acpi_device.h @@ -545,6 +545,11 @@ const char *ref, int index, int pin, int active_low); +/* Add a GPIO binding device property for array of GPIOs */ +struct acpi_dp *acpi_dp_add_gpio_array(struct acpi_dp *dp, const char *name, + const char *ref, int index, int pin, + uint32_t gpio_count, int active_low); + /* Add a child table of Device Properties */ struct acpi_dp *acpi_dp_add_child(struct acpi_dp *dp, const char *name, struct acpi_dp *child); -- To view, visit https://review.coreboot.org/c/coreboot/+/46056 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7c6cc36b1bfca2d48c84f169e6b43fd4be8ba330 Gerrit-Change-Number: 46056 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/jasperlake: Set the GpioOverride configuration
by Ronak Kanabar (Code Review) 14 Oct '20

14 Oct '20

Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Maulik V Vaghela, Angel Pons, Subrata Banik, Aamir Bohra, Patrick Rudolph, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/45901 to look at the new patch set (#7). Change subject: soc/intel/jasperlake: Set the GpioOverride configuration ...................................................................... soc/intel/jasperlake: Set the GpioOverride configuration Set "GpioOverride" config to override FSP gpio configuration. FSP will not configure any GPIOs and rely on GPIO setings before moved to FSP. BUG=b:150666058 TEST=Build and boot JSLRVP Change-Id: Ia4036cf0be3a6036d70920743958dc327a652077 Signed-off-by: Ronak Kanabar <ronak.kanabar(a)intel.com> --- M src/soc/intel/jasperlake/romstage/fsp_params.c 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/45901/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/45901 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia4036cf0be3a6036d70920743958dc327a652077 Gerrit-Change-Number: 45901 Gerrit-PatchSet: 7 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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coreboot-gerrit October 2020