Change in coreboot[master]: {cpu,soc}/intel: deduplicate cpu code

[Michael Niewöhner (Code Review)]

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46274 )

Change subject: {cpu,soc}/intel: deduplicate cpu code
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Patch Set 10:

(1 comment)

https://review.coreboot.org/c/coreboot/+/46274/9/src/soc/intel/cannonlake/cp... 
File src/soc/intel/cannonlake/cpu.c:

https://review.coreboot.org/c/coreboot/+/46274/9/src/soc/intel/cannonlake/cp... 
PS9, Line 109: /*
             :  * The emulated ACPI timer allows replacing of the ACPI timer
             :  * (PM1_TMR) to have no impart on the system.
             :  */
             : static void enable_pm_timer_emulation(void)
             : {
             : 	const struct soc_intel_cannonlake_config *config;
             : 	msr_t msr;
             : 
             : 	config = config_of_soc();
             : 
             : 	/* Enable PM timer emulation only if ACPI PM timer is disabled */
             : 	if (!config->PmTimerDisabled)
             : 		return;
             : 	/*
             : 	 * The derived frequency is calculated as follows:
             : 	 *    (CTC_FREQ * msr[63:32]) >> 32 = target frequency.
             : 	 * Back solve the multiplier so the 3.579545MHz ACPI timer
             : 	 * frequency is used.
             : 	 */
             : 	msr.hi = (3579545ULL << 32) / CTC_FREQ;
             : 	/* Set PM1 timer IO port and enable */
             : 	msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) |
             : 			EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR);
             : 	wrmsr(MSR_EMULATE_PM_TIMER, msr);
             : }
that was unintended and is done in a separate patch series. see CB:45951