Bora Guvendik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45828 )
Change subject: mb/intel/tglrvp: Enable Pcie WWAN m.2 ......................................................................
mb/intel/tglrvp: Enable Pcie WWAN m.2
Change-Id: Ie9b7915062b2ef65d881d478e64322c0b8765614 Signed-off-by: Bora Guvendik bora.guvendik@intel.com --- M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c 4 files changed, 22 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/45828/1
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index ad7eabe..be3ba0f 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -20,7 +20,7 @@ register "SmbusEnable" = "1"
register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" # Type-C Port1 - register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN + register "usb2_ports[1]" = "USB2_PORT_EMPTY" # M.2 WWAN register "usb2_ports[2]" = "USB2_PORT_MID(OC3)" # M.2 Bluetooth register "usb2_ports[3]" = "USB2_PORT_MID(OC0)" # USB3/2 Type A port1 register "usb2_ports[4]" = "USB2_PORT_MID(OC0)" # Type-C Port2 diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c index 49946c8..b63ee98 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c @@ -94,6 +94,15 @@ PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), /* HPD_1 */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), /* DDP_1_CTRCLK */ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), /* DDP_1_CTRDATA */ + + /* WWAN */ + PAD_CFG_GPO(GPP_H23, 1, PLTRST), /* WWAN_PWREN */ + PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), /* CLK SRC 2 */ + PAD_CFG_GPI_SCI(GPP_C9, NONE, DEEP, LEVEL, INVERT), /* WWAN_WAKE_N */ + PAD_CFG_GPO(GPP_C11, 1, PLTRST), /* FULL_CARD_POWER_OFF_N */ + PAD_CFG_GPO(GPP_C10, 1, PLTRST), /* WWAN_RST_N */ + PAD_CFG_GPO(GPP_B17, 1, PLTRST), /* WWAN_PERST_N */ + PAD_CFG_GPO(GPP_D15, 1, PLTRST), /* WWAN_DISABLE_N */ };
const struct pad_config *variant_gpio_table(size_t *num) diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index 3e2b342..1ba6bd6 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -20,9 +20,9 @@ register "SmbusEnable" = "1"
register "usb2_ports[0]" = "USB2_PORT_MID(OC3)" # Type-C Port1 - register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN - register "usb2_ports[2]" = "USB2_PORT_MID(OC0)" # M.2 Bluetooth, USB3/2 Type A port1 - register "usb2_ports[3]" = "USB2_PORT_MID(OC3)" # USB3/2 Type A port1 + register "usb2_ports[1]" = "USB2_PORT_EMPTY" # M.2 WWAN + register "usb2_ports[2]" = "USB2_PORT_MID(OC0)" # M.2 Bluetooth, USB3/2 Type A Port1 + register "usb2_ports[3]" = "USB2_PORT_MID(OC3)" # USB3/2 Type A Port 1 register "usb2_ports[4]" = "USB2_PORT_MID(OC3)" # Type-C Port2 register "usb2_ports[5]" = "USB2_PORT_MID(OC3)" # Type-C Port3 register "usb2_ports[9]" = "USB2_PORT_MID(OC3)" # CNVi/BT diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c index 91bbe93..eee3234 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c @@ -90,6 +90,15 @@ PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), /* HPD_1 */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), /* DDP_1_CTRCLK */ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), /* DDP_1_CTRDATA */ + + /* WWAN */ + PAD_CFG_GPO(GPP_D11, 1, PLTRST), /* WWAN_PWREN */ + PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), /* CLK SRC 2 */ + PAD_CFG_GPI_SCI(GPP_C9, NONE, DEEP, LEVEL, INVERT), /* WWAN_WAKE_N */ + PAD_CFG_GPO(GPP_C11, 1, PLTRST), /* FULL_CARD_POWER_OFF_N */ + PAD_CFG_GPO(GPP_C10, 1, PLTRST), /* WWAN_RST_N */ + PAD_CFG_GPO(GPP_B17, 1, PLTRST), /* WWAN_PERST_N */ + PAD_CFG_GPO(GPP_D15, 1, PLTRST), /* WWAN_DISABLE_N */ };
const struct pad_config *variant_gpio_table(size_t *num)
Hello build bot (Jenkins), Wonkyu Kim, Shreesh Chhabbi, Selma Bensaid, Ravishankar Sarawadi,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45828
to look at the new patch set (#2).
Change subject: mb/intel/tglrvp: Enable Pcie WWAN m.2 ......................................................................
mb/intel/tglrvp: Enable Pcie WWAN m.2
Change-Id: Ie9b7915062b2ef65d881d478e64322c0b8765614 Signed-off-by: Bora Guvendik bora.guvendik@intel.com --- M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c 4 files changed, 21 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/45828/2
Hello build bot (Jenkins), Wonkyu Kim, Shreesh Chhabbi, Selma Bensaid, Ravishankar Sarawadi,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45828
to look at the new patch set (#3).
Change subject: mb/intel/tglrvp: Enable Pcie WWAN m.2 ......................................................................
mb/intel/tglrvp: Enable Pcie WWAN m.2
Change-Id: Ie9b7915062b2ef65d881d478e64322c0b8765614 Signed-off-by: Bora Guvendik bora.guvendik@intel.com --- M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c 4 files changed, 20 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/45828/3
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45828 )
Change subject: mb/intel/tglrvp: Enable Pcie WWAN m.2 ......................................................................
Patch Set 3:
(4 comments)
https://review.coreboot.org/c/coreboot/+/45828/3/src/mainboard/intel/tglrvp/... File src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c:
https://review.coreboot.org/c/coreboot/+/45828/3/src/mainboard/intel/tglrvp/... PS3, Line 99: PLTRST Can we use DEEP? We used DEEP for other configuration.
https://review.coreboot.org/c/coreboot/+/45828/3/src/mainboard/intel/tglrvp/... PS3, Line 102: PAD_CFG_GPO(GPP_C11, 1, PLTRST), /* FULL_CARD_POWER_OFF_N */ : PAD_CFG_GPO(GPP_C10, 1, PLTRST), /* WWAN_RST_N */ : PAD_CFG_GPO(GPP_B17, 1, PLTRST), /* WWAN_PERST_N */ : PAD_CFG_GPO(GPP_D15, 1, PLTRST), /* WWAN_DISABLE_N */ Can we use DEEP? We used DEEP for other configuration.
https://review.coreboot.org/c/coreboot/+/45828/3/src/mainboard/intel/tglrvp/... File src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c:
https://review.coreboot.org/c/coreboot/+/45828/3/src/mainboard/intel/tglrvp/... PS3, Line 95: PAD_CFG_GPO(GPP_D11, 1, PLTRST), /* WWAN_PWREN */ Can we use DEEP? We used DEEP for other configuration.
https://review.coreboot.org/c/coreboot/+/45828/3/src/mainboard/intel/tglrvp/... PS3, Line 98: PAD_CFG_GPO(GPP_C11, 1, PLTRST), /* FULL_CARD_POWER_OFF_N */ : PAD_CFG_GPO(GPP_C10, 1, PLTRST), /* WWAN_RST_N */ : PAD_CFG_GPO(GPP_B17, 1, PLTRST), /* WWAN_PERST_N */ : PAD_CFG_GPO(GPP_D15, 1, PLTRST), /* WWAN_DISABLE_N */ Can we use DEEP? We used DEEP for other configuration.
Bora Guvendik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45828 )
Change subject: mb/intel/tglrvp: Enable Pcie WWAN m.2 ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45828/3/src/mainboard/intel/tglrvp/... File src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c:
https://review.coreboot.org/c/coreboot/+/45828/3/src/mainboard/intel/tglrvp/... PS3, Line 102: PAD_CFG_GPO(GPP_C11, 1, PLTRST), /* FULL_CARD_POWER_OFF_N */ : PAD_CFG_GPO(GPP_C10, 1, PLTRST), /* WWAN_RST_N */ : PAD_CFG_GPO(GPP_B17, 1, PLTRST), /* WWAN_PERST_N */ : PAD_CFG_GPO(GPP_D15, 1, PLTRST), /* WWAN_DISABLE_N */
Can we use DEEP? We used DEEP for other configuration.
thanks we will check
Hello build bot (Jenkins), Wonkyu Kim, Shreesh Chhabbi, Selma Bensaid, Ravishankar Sarawadi,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45828
to look at the new patch set (#4).
Change subject: mb/intel/tglrvp: Enable Pcie WWAN m.2 ......................................................................
mb/intel/tglrvp: Enable Pcie WWAN m.2
Change-Id: Ie9b7915062b2ef65d881d478e64322c0b8765614 Signed-off-by: Bora Guvendik bora.guvendik@intel.com --- M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c 4 files changed, 20 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/45828/4
Bora Guvendik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45828 )
Change subject: mb/intel/tglrvp: Enable Pcie WWAN m.2 ......................................................................
Patch Set 4:
(4 comments)
https://review.coreboot.org/c/coreboot/+/45828/3/src/mainboard/intel/tglrvp/... File src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c:
https://review.coreboot.org/c/coreboot/+/45828/3/src/mainboard/intel/tglrvp/... PS3, Line 99: PLTRST
Can we use DEEP? We used DEEP for other configuration.
Done
https://review.coreboot.org/c/coreboot/+/45828/3/src/mainboard/intel/tglrvp/... PS3, Line 102: PAD_CFG_GPO(GPP_C11, 1, PLTRST), /* FULL_CARD_POWER_OFF_N */ : PAD_CFG_GPO(GPP_C10, 1, PLTRST), /* WWAN_RST_N */ : PAD_CFG_GPO(GPP_B17, 1, PLTRST), /* WWAN_PERST_N */ : PAD_CFG_GPO(GPP_D15, 1, PLTRST), /* WWAN_DISABLE_N */
thanks we will check
Done
https://review.coreboot.org/c/coreboot/+/45828/3/src/mainboard/intel/tglrvp/... File src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c:
https://review.coreboot.org/c/coreboot/+/45828/3/src/mainboard/intel/tglrvp/... PS3, Line 95: PAD_CFG_GPO(GPP_D11, 1, PLTRST), /* WWAN_PWREN */
Can we use DEEP? We used DEEP for other configuration.
Done
https://review.coreboot.org/c/coreboot/+/45828/3/src/mainboard/intel/tglrvp/... PS3, Line 98: PAD_CFG_GPO(GPP_C11, 1, PLTRST), /* FULL_CARD_POWER_OFF_N */ : PAD_CFG_GPO(GPP_C10, 1, PLTRST), /* WWAN_RST_N */ : PAD_CFG_GPO(GPP_B17, 1, PLTRST), /* WWAN_PERST_N */ : PAD_CFG_GPO(GPP_D15, 1, PLTRST), /* WWAN_DISABLE_N */
Can we use DEEP? We used DEEP for other configuration.
Done
Hello build bot (Jenkins), Wonkyu Kim, Shreesh Chhabbi, Selma Bensaid, Ravishankar Sarawadi,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45828
to look at the new patch set (#5).
Change subject: mb/intel/tglrvp: Enable Pcie WWAN m.2 ......................................................................
mb/intel/tglrvp: Enable Pcie WWAN m.2
Change-Id: Ie9b7915062b2ef65d881d478e64322c0b8765614 Signed-off-by: Bora Guvendik bora.guvendik@intel.com --- M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c 4 files changed, 20 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/45828/5
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45828 )
Change subject: mb/intel/tglrvp: Enable Pcie WWAN m.2 ......................................................................
Patch Set 5:
(1 comment)
Warm reset case is also tested?
https://review.coreboot.org/c/coreboot/+/45828/5/src/mainboard/intel/tglrvp/... File src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/45828/5/src/mainboard/intel/tglrvp/... PS5, Line 23: register "usb2_ports[1]" = "USB2_PORT_EMPTY" # M.2 WWAN Can you add more info for this change and RP interface for WWAN?
Hello build bot (Jenkins), Wonkyu Kim, Shreesh Chhabbi, Selma Bensaid, Ravishankar Sarawadi,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45828
to look at the new patch set (#6).
Change subject: mb/intel/tglrvp: Enable Pcie WWAN m.2 ......................................................................
mb/intel/tglrvp: Enable Pcie WWAN m.2
Enables Pcie M.2 support for WWAN and disable M.2 USB. RP4 is already on and PcieRpEnable[3] is enabled. Clock source 2 is already configured. Added missing gpio configuration.
BUG=none TEST=Boot to OS, check WWAN functionality
Change-Id: Ie9b7915062b2ef65d881d478e64322c0b8765614 Signed-off-by: Bora Guvendik bora.guvendik@intel.com --- M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c 4 files changed, 20 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/45828/6
Bora Guvendik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45828 )
Change subject: mb/intel/tglrvp: Enable Pcie WWAN m.2 ......................................................................
Patch Set 6:
Patch Set 5:
(1 comment)
Warm reset case is also tested?
Yes tested warm/cold reboot.
Bora Guvendik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45828 )
Change subject: mb/intel/tglrvp: Enable Pcie WWAN m.2 ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45828/5/src/mainboard/intel/tglrvp/... File src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/45828/5/src/mainboard/intel/tglrvp/... PS5, Line 23: register "usb2_ports[1]" = "USB2_PORT_EMPTY" # M.2 WWAN
Can you add more info for this change and RP interface for WWAN?
Done
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45828 )
Change subject: mb/intel/tglrvp: Enable Pcie WWAN m.2 ......................................................................
Patch Set 6: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45828 )
Change subject: mb/intel/tglrvp: Enable Pcie WWAN m.2 ......................................................................
mb/intel/tglrvp: Enable Pcie WWAN m.2
Enables Pcie M.2 support for WWAN and disable M.2 USB. RP4 is already on and PcieRpEnable[3] is enabled. Clock source 2 is already configured. Added missing gpio configuration.
BUG=none TEST=Boot to OS, check WWAN functionality
Change-Id: Ie9b7915062b2ef65d881d478e64322c0b8765614 Signed-off-by: Bora Guvendik bora.guvendik@intel.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/45828 Reviewed-by: Wonkyu Kim wonkyu.kim@intel.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c 4 files changed, 20 insertions(+), 2 deletions(-)
Approvals: build bot (Jenkins): Verified Wonkyu Kim: Looks good to me, approved
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index 2abdce4..09ab258 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -20,7 +20,7 @@ register "SmbusEnable" = "1"
register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" # Type-C Port1 - register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN + register "usb2_ports[1]" = "USB2_PORT_EMPTY" # M.2 WWAN register "usb2_ports[2]" = "USB2_PORT_MID(OC3)" # M.2 Bluetooth register "usb2_ports[3]" = "USB2_PORT_MID(OC0)" # USB3/2 Type A port1 register "usb2_ports[4]" = "USB2_PORT_MID(OC0)" # Type-C Port2 diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c index c9de9c6..51b301d 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c @@ -104,6 +104,15 @@ PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1), /* B22 : GSPI1_MOSI */ PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1), + + /* WWAN */ + PAD_CFG_GPO(GPP_H23, 1, DEEP), /* WWAN_PWREN */ + PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), /* CLK SRC 2 */ + PAD_CFG_GPI_SCI(GPP_C9, NONE, DEEP, LEVEL, INVERT), /* WWAN_WAKE_N */ + PAD_CFG_GPO(GPP_C11, 1, DEEP), /* FULL_CARD_POWER_OFF_N */ + PAD_CFG_GPO(GPP_C10, 1, DEEP), /* WWAN_RST_N */ + PAD_CFG_GPO(GPP_B17, 1, DEEP), /* WWAN_PERST_N */ + PAD_CFG_GPO(GPP_D15, 1, DEEP), /* WWAN_DISABLE_N */ };
const struct pad_config *variant_gpio_table(size_t *num) diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index b46a1cf..25c2293 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -20,7 +20,7 @@ register "SmbusEnable" = "1"
register "usb2_ports[0]" = "USB2_PORT_MID(OC3)" # Type-C Port1 - register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN + register "usb2_ports[1]" = "USB2_PORT_EMPTY" # M.2 WWAN register "usb2_ports[2]" = "USB2_PORT_MID(OC0)" # M.2 Bluetooth, USB3/2 Type A Port1 register "usb2_ports[3]" = "USB2_PORT_MID(OC3)" # USB3/2 Type A Port 1 register "usb2_ports[4]" = "USB2_PORT_MID(OC3)" # Type-C Port2 diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c index 303350b..77da5cc 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c @@ -100,6 +100,15 @@ PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1), /* B22 : GSPI1_MOSI */ PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1), + + /* WWAN */ + PAD_CFG_GPO(GPP_D11, 1, DEEP), /* WWAN_PWREN */ + PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), /* CLK SRC 2 */ + PAD_CFG_GPI_SCI(GPP_C9, NONE, DEEP, LEVEL, INVERT), /* WWAN_WAKE_N */ + PAD_CFG_GPO(GPP_C11, 1, DEEP), /* FULL_CARD_POWER_OFF_N */ + PAD_CFG_GPO(GPP_C10, 1, DEEP), /* WWAN_RST_N */ + PAD_CFG_GPO(GPP_B17, 1, DEEP), /* WWAN_PERST_N */ + PAD_CFG_GPO(GPP_D15, 1, DEEP), /* WWAN_DISABLE_N */ };
const struct pad_config *variant_gpio_table(size_t *num)
-
Bora Guvendik (Code Review) -
Patrick Georgi (Code Review)
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Wonkyu Kim (Code Review)