Change in coreboot[master]: mb/google/zork: Enable wake on wireless lan

[Rob Barnes (Code Review)]

Rob Barnes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45745 )

Change subject: mb/google/zork: Enable wake on wireless lan
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mb/google/zork: Enable wake on wireless lan

Add generic wifi ACPI entry for wake on lan event.
Change configuration of GPIO 2/WIFI_PCIE_WAKE_ODL to SCI.

BUG=b:162605108
TEST=$ iw phy phy0 wowlan enable disconnect
     $ cat /proc/acpi/wakeup | grep WF
       WF00	  S3	*enabled   pci:0000:01:00.0
     $ powerd_dbus_suspend
     Reboot wifi router, DUT wakes up

Change-Id: Idbeb2cfbc4995b8382ffc26cbe7b53764fc9252d
Signed-off-by: Rob Barnes 
---
M src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb
M src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb
M src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c
M src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c
4 files changed, 18 insertions(+), 6 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/45745/1

diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb
index 42219d7..7e1c0ad 100644
--- a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb
+++ b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb
@@ -200,7 +200,13 @@
    	device pci 0.2 on  end # IOMMU
    	device pci 1.0 on  end # Dummy Host Bridge, must be enabled
    	device pci 1.1 off end # GPP Bridge 0
-		device pci 1.2 on  end # GPP Bridge 1 - Wifi
+		device pci 1.2 on      # GPP Bridge 1 - Wifi
+			chip drivers/wifi/generic
+				register "wake" = "GEVENT_8"
+				register "maxsleep" = "3"
+				device pci 00.0 on  end
+			end
+		end
    	device pci 1.3 on  end # GPP Bridge 2 - SD
    	device pci 1.4 off end # GPP Bridge 3
    	device pci 1.5 off end # GPP Bridge 4
diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb
index 1620643..f707465 100644
--- a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb
+++ b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb
@@ -200,7 +200,13 @@
    	device pci 0.2 on  end # IOMMU
    	device pci 1.0 on  end # Dummy Host Bridge, must be enabled
    	device pci 1.1 off end # GPP Bridge 0
-		device pci 1.2 on  end # GPP Bridge 1 - Wifi
+		device pci 1.2 on      # GPP Bridge 1 - Wifi
+			chip drivers/wifi/generic
+				register "wake" = "GEVENT_8"
+				register "maxsleep" = "3"
+				device pci 00.0 on  end
+			end
+		end
    	device pci 1.3 on  end # GPP Bridge 2 - SD
    	device pci 1.4 off end # GPP Bridge 3
    	device pci 1.5 off end # GPP Bridge 4
diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c
index e69b47f..ab054ff 100644
--- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c
+++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c
@@ -14,8 +14,8 @@
    PAD_NF(GPIO_0, PWR_BTN_L, PULL_NONE),
    /* SYS_RESET_L */
    PAD_NF(GPIO_1, SYS_RESET_L, PULL_NONE),
-	/* PCIE_WAKE_L */
-	PAD_NF(GPIO_2, WAKE_L, PULL_NONE),
+	/* WIFI_PCIE_WAKE_ODL */
+	PAD_SCI(GPIO_2, PULL_NONE, EDGE_LOW),
    /* H1_FCH_INT_ODL */
    PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS_DELIVERY),
    /* PEN_DETECT_ODL */
diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c
index bf25da3..a941087 100644
--- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c
+++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c
@@ -14,8 +14,8 @@
    PAD_NF(GPIO_0, PWR_BTN_L, PULL_NONE),
    /* SYS_RESET_L */
    PAD_NF(GPIO_1, SYS_RESET_L, PULL_NONE),
-	/* PCIE_WAKE_L */
-	PAD_NF(GPIO_2, WAKE_L, PULL_NONE),
+	/* WIFI_PCIE_WAKE_ODL */
+	PAD_SCI(GPIO_2, PULL_NONE, EDGE_LOW),
    /* H1_FCH_INT_ODL */
    PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS_DELIVERY),
    /* PEN_DETECT_ODL */