coreboot-gerrit May 2019

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Change in ...coreboot[master]: intel/quark/storage_test.h: Drop external variable declaration
by Arthur Heymans (Code Review) 29 May '19

29 May '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33022 Change subject: intel/quark/storage_test.h: Drop external variable declaration ...................................................................... intel/quark/storage_test.h: Drop external variable declaration These are only used where they are initially declared. Change-Id: I0a81a945b771b6c29a170c479b9e72c98e8f3c5a Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/quark/include/soc/storage_test.h 1 file changed, 0 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/33022/1 diff --git a/src/soc/intel/quark/include/soc/storage_test.h b/src/soc/intel/quark/include/soc/storage_test.h index 62c9e79..1c93f1c 100644 --- a/src/soc/intel/quark/include/soc/storage_test.h +++ b/src/soc/intel/quark/include/soc/storage_test.h @@ -48,9 +48,4 @@ #define LOG_ENTRIES 256 -extern struct log_entry log[LOG_ENTRIES]; -extern uint8_t log_index; -extern int log_full; -extern long log_start_time; - #endif /* __STORAGE_TEST_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/33022 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0a81a945b771b6c29a170c479b9e72c98e8f3c5a Gerrit-Change-Number: 33022 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/braswell: Don't use CAR_GLOBAL
by Arthur Heymans (Code Review) 29 May '19

29 May '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32997 Change subject: soc/intel/braswell: Don't use CAR_GLOBAL ...................................................................... soc/intel/braswell: Don't use CAR_GLOBAL Now that this soc supports NO_CAR_GLOBAL_MIGRATION CAR_GLOBAL and car_get/set_x are not needed anymore. Change-Id: Ia7fa97135a4b376ac0bd8b30093a77614cc2cf55 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/braswell/romstage/romstage.c 1 file changed, 16 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/32997/1 diff --git a/src/soc/intel/braswell/romstage/romstage.c b/src/soc/intel/braswell/romstage/romstage.c index 22b0df2..054a49c 100644 --- a/src/soc/intel/braswell/romstage/romstage.c +++ b/src/soc/intel/braswell/romstage/romstage.c @@ -17,7 +17,6 @@ #include <cbmem.h> #include <stddef.h> -#include <arch/early_variables.h> #include <arch/io.h> #include <device/mmio.h> #include <device/pci_ops.h> @@ -105,47 +104,43 @@ cmos_init(rtc_failed); } -static struct chipset_power_state power_state CAR_GLOBAL; +static struct chipset_power_state power_state; static void migrate_power_state(int is_recovery) { struct chipset_power_state *ps_cbmem; - struct chipset_power_state *ps_car; - ps_car = car_get_var_ptr(&power_state); ps_cbmem = cbmem_add(CBMEM_ID_POWER_STATE, sizeof(*ps_cbmem)); if (ps_cbmem == NULL) { printk(BIOS_DEBUG, "Not adding power state to cbmem!\n"); return; } - memcpy(ps_cbmem, ps_car, sizeof(*ps_cbmem)); + memcpy(ps_cbmem, &power_state, sizeof(*ps_cbmem)); } ROMSTAGE_CBMEM_INIT_HOOK(migrate_power_state); struct chipset_power_state *fill_power_state(void) { - struct chipset_power_state *ps = car_get_var_ptr(&power_state); + power_state.pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS); + power_state.pm1_en = inw(ACPI_BASE_ADDRESS + PM1_EN); + power_state.pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT); + power_state.gpe0_sts = inl(ACPI_BASE_ADDRESS + GPE0_STS); + power_state.gpe0_en = inl(ACPI_BASE_ADDRESS + GPE0_EN); + power_state.tco_sts = inl(ACPI_BASE_ADDRESS + TCO_STS); + power_state.prsts = read32((void *)(PMC_BASE_ADDRESS + PRSTS)); + power_state.gen_pmcon1 = read32((void *)(PMC_BASE_ADDRESS + GEN_PMCON1)); + power_state.gen_pmcon2 = read32((void *)(PMC_BASE_ADDRESS + GEN_PMCON2)); - ps->pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS); - ps->pm1_en = inw(ACPI_BASE_ADDRESS + PM1_EN); - ps->pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT); - ps->gpe0_sts = inl(ACPI_BASE_ADDRESS + GPE0_STS); - ps->gpe0_en = inl(ACPI_BASE_ADDRESS + GPE0_EN); - ps->tco_sts = inl(ACPI_BASE_ADDRESS + TCO_STS); - ps->prsts = read32((void *)(PMC_BASE_ADDRESS + PRSTS)); - ps->gen_pmcon1 = read32((void *)(PMC_BASE_ADDRESS + GEN_PMCON1)); - ps->gen_pmcon2 = read32((void *)(PMC_BASE_ADDRESS + GEN_PMCON2)); - - ps->prev_sleep_state = chipset_prev_sleep_state(ps); + power_state.prev_sleep_state = chipset_prev_sleep_state(ps); printk(BIOS_DEBUG, "pm1_sts: %04x pm1_en: %04x pm1_cnt: %08x\n", - ps->pm1_sts, ps->pm1_en, ps->pm1_cnt); + power_state.pm1_sts, power_state.pm1_en, power_state.pm1_cnt); printk(BIOS_DEBUG, "gpe0_sts: %08x gpe0_en: %08x tco_sts: %08x\n", - ps->gpe0_sts, ps->gpe0_en, ps->tco_sts); + power_state.gpe0_sts, power_state.gpe0_en, power_state.tco_sts); printk(BIOS_DEBUG, "prsts: %08x gen_pmcon1: %08x gen_pmcon2: %08x\n", - ps->prsts, ps->gen_pmcon1, ps->gen_pmcon2); - printk(BIOS_DEBUG, "prev_sleep_state %d\n", ps->prev_sleep_state); + power_state.prsts, power_state.gen_pmcon1, power_state.gen_pmcon2); + printk(BIOS_DEBUG, "prev_sleep_state %d\n", power_state.prev_sleep_state); return ps; } -- To view, visit https://review.coreboot.org/c/coreboot/+/32997 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia7fa97135a4b376ac0bd8b30093a77614cc2cf55 Gerrit-Change-Number: 32997 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: Clean up unused arch/early_variables.h header
by Arthur Heymans (Code Review) 29 May '19

29 May '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32996 Change subject: Clean up unused arch/early_variables.h header ...................................................................... Clean up unused arch/early_variables.h header Change-Id: Ib863e23863ba6d7504b6c4d32de2f1fea4e57fec Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/drivers/intel/fsp1_1/car.c M src/drivers/intel/fsp1_1/hob.c M src/drivers/intel/fsp1_1/romstage.c M src/drivers/intel/fsp2_0/hand_off_block.c M src/mainboard/packardbell/ms2290/romstage.c M src/soc/intel/broadwell/romstage/romstage.c M src/soc/intel/broadwell/romstage/uart.c M src/soc/intel/common/block/fast_spi/fast_spi_flash.c M src/soc/intel/common/block/scs/early_mmc.c M src/soc/intel/skylake/romstage/romstage.c M src/soc/intel/skylake/romstage/romstage_fsp20.c 11 files changed, 0 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/32996/1 diff --git a/src/drivers/intel/fsp1_1/car.c b/src/drivers/intel/fsp1_1/car.c index 34b2518..7bebde3 100644 --- a/src/drivers/intel/fsp1_1/car.c +++ b/src/drivers/intel/fsp1_1/car.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <arch/early_variables.h> #include <console/console.h> #include <cpu/x86/mtrr.h> #include <fsp/car.h> diff --git a/src/drivers/intel/fsp1_1/hob.c b/src/drivers/intel/fsp1_1/hob.c index ee1a6a3..0a123cf 100644 --- a/src/drivers/intel/fsp1_1/hob.c +++ b/src/drivers/intel/fsp1_1/hob.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ -#include <arch/early_variables.h> #include <arch/hlt.h> #include <bootstate.h> #include <console/console.h> diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c index 40c5988..1cc98b2 100644 --- a/src/drivers/intel/fsp1_1/romstage.c +++ b/src/drivers/intel/fsp1_1/romstage.c @@ -18,7 +18,6 @@ #include <stddef.h> #include <arch/acpi.h> #include <arch/cbfs.h> -#include <arch/early_variables.h> #include <assert.h> #include <console/console.h> #include <cbmem.h> diff --git a/src/drivers/intel/fsp2_0/hand_off_block.c b/src/drivers/intel/fsp2_0/hand_off_block.c index c5c78ca..589bb7a 100644 --- a/src/drivers/intel/fsp2_0/hand_off_block.c +++ b/src/drivers/intel/fsp2_0/hand_off_block.c @@ -10,7 +10,6 @@ * (at your option) any later version. */ -#include <arch/early_variables.h> #include <device/mmio.h> #include <cbmem.h> #include <commonlib/helpers.h> diff --git a/src/mainboard/packardbell/ms2290/romstage.c b/src/mainboard/packardbell/ms2290/romstage.c index efaa9e4..0ab5544 100644 --- a/src/mainboard/packardbell/ms2290/romstage.c +++ b/src/mainboard/packardbell/ms2290/romstage.c @@ -31,7 +31,6 @@ #include <timestamp.h> #include <arch/acpi.h> -#include "arch/early_variables.h" #include <southbridge/intel/ibexpeak/pch.h> #include <northbridge/intel/nehalem/nehalem.h> diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c index f857167..9bca716 100644 --- a/src/soc/intel/broadwell/romstage/romstage.c +++ b/src/soc/intel/broadwell/romstage/romstage.c @@ -16,7 +16,6 @@ #include <stddef.h> #include <stdint.h> #include <arch/cbfs.h> -#include <arch/early_variables.h> #include <bootblock_common.h> #include <bootmode.h> #include <cbmem.h> diff --git a/src/soc/intel/broadwell/romstage/uart.c b/src/soc/intel/broadwell/romstage/uart.c index 58450dd..a1a29b6 100644 --- a/src/soc/intel/broadwell/romstage/uart.c +++ b/src/soc/intel/broadwell/romstage/uart.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <arch/early_variables.h> #include <device/pci_def.h> #include <reg_script.h> #include <stdint.h> diff --git a/src/soc/intel/common/block/fast_spi/fast_spi_flash.c b/src/soc/intel/common/block/fast_spi/fast_spi_flash.c index 97e231c..0a43442 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi_flash.c +++ b/src/soc/intel/common/block/fast_spi/fast_spi_flash.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <arch/early_variables.h> #include <device/mmio.h> #include <console/console.h> #include <fast_spi_def.h> diff --git a/src/soc/intel/common/block/scs/early_mmc.c b/src/soc/intel/common/block/scs/early_mmc.c index 4b15bb4..8f47ec7 100644 --- a/src/soc/intel/common/block/scs/early_mmc.c +++ b/src/soc/intel/common/block/scs/early_mmc.c @@ -14,7 +14,6 @@ */ #include <arch/acpi.h> -#include <arch/early_variables.h> #include <cbmem.h> #include <commonlib/storage/sd_mmc.h> #include <commonlib/sd_mmc_ctrlr.h> diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index 12239ae..29c4774 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -15,7 +15,6 @@ */ #include <arch/cbfs.h> -#include <arch/early_variables.h> #include <assert.h> #include <console/console.h> #include <cpu/x86/mtrr.h> diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c index 96937d6..04c369b 100644 --- a/src/soc/intel/skylake/romstage/romstage_fsp20.c +++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c @@ -14,7 +14,6 @@ */ #include <arch/cpu.h> -#include <arch/early_variables.h> #include <arch/symbols.h> #include <assert.h> #include <cpu/x86/mtrr.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/32996 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib863e23863ba6d7504b6c4d32de2f1fea4e57fec Gerrit-Change-Number: 32996 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/apollolake: Don't use CAR_GLOBAL
by Arthur Heymans (Code Review) 29 May '19

29 May '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30510 Change subject: soc/intel/apollolake: Don't use CAR_GLOBAL ...................................................................... soc/intel/apollolake: Don't use CAR_GLOBAL All platforms using this code have NO_CAR_GLOBAL_MIGRATION. Change-Id: I0f393385aa94f18c2e05af3b5a54999575323d18 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/apollolake/meminit.c M src/soc/intel/apollolake/mmap_boot.c M src/soc/intel/apollolake/romstage.c 3 files changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/30510/1 diff --git a/src/soc/intel/apollolake/meminit.c b/src/soc/intel/apollolake/meminit.c index 889bbde..a230222 100644 --- a/src/soc/intel/apollolake/meminit.c +++ b/src/soc/intel/apollolake/meminit.c @@ -21,7 +21,7 @@ #include <fsp/soc_binding.h> #include <string.h> -static size_t memory_size_mib CAR_GLOBAL; +static size_t memory_size_mib; size_t memory_in_system_in_mib(void) { diff --git a/src/soc/intel/apollolake/mmap_boot.c b/src/soc/intel/apollolake/mmap_boot.c index 1c3077e..8174502 100644 --- a/src/soc/intel/apollolake/mmap_boot.c +++ b/src/soc/intel/apollolake/mmap_boot.c @@ -57,10 +57,10 @@ * */ -static size_t bios_size CAR_GLOBAL; +static size_t bios_size; -static struct mem_region_device shadow_dev CAR_GLOBAL; -static struct xlate_region_device real_dev CAR_GLOBAL; +static struct mem_region_device shadow_dev; +static struct xlate_region_device real_dev; static void bios_mmap_init(void) { diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 4f4f9f5..4133946 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -58,7 +58,7 @@ 0x8d, 0xe6, 0xc0, 0x44, 0x64, 0x1d, 0xe9, 0x42, }; -static uint32_t fsp_version CAR_GLOBAL; +static uint32_t fsp_version; /* High Performance Event Timer Configuration */ #define P2SB_HPTC 0x60 -- To view, visit https://review.coreboot.org/c/coreboot/+/30510 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0f393385aa94f18c2e05af3b5a54999575323d18 Gerrit-Change-Number: 30510 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: intel/sandybridge: Make timC training more robust.
by Patrick Georgi (Code Review) 29 May '19

29 May '19

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/22776 ) Change subject: intel/sandybridge: Make timC training more robust. ...................................................................... intel/sandybridge: Make timC training more robust. When using native raminit with https://review.coreboot.org/#/c/22683/ I've found that timC training usually fails unless the ram is overspecced (i.e. DDR3L-1600 rated for 1.35V works most of the time with native raminit as DDR3-1333 @1.5V). Looking at the training data I've found that during timC training it is reading register values in the 0-4000 range and checking for runs of 0, but with the failing training the values don't go all the way down to 0. The solution for me has been to do a thresholing pre-pass, after which both the DDR3-1333 @1.5V and the DDR3L-1600 @1.35V work fine for me. Tested: - Intel NUC DCP847SKE - RAM slots with 2x4GB Kingston KVR1333D3S9/4G (DDR3-1333 1.5V), boots fine with native raminit @1.5V - RAM slots with 2x4GB Kingston KVR16LS11/4G (DDR3L-1600 1.35V), boots fine with native raminit @1.35V - Casual use with these settings - Tested on Lenovo T520 with Crucial HyperX DDR3-1833. - Memtest86+ stable. Change-Id: I9986616e86560c4980ccd8e3e549af53caa15c71 Signed-off-by: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/22776 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/sandybridge/raminit_common.c 1 file changed, 34 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 5347c5c..53f28c6 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -1524,6 +1524,24 @@ wait_428c(channel); } +static void timC_threshold_process(int *data, const int count) +{ + int min = data[0]; + int max = min; + int i; + for (i = 1; i < count; i++) { + if (min > data[i]) + min = data[i]; + if (max < data[i]) + max = data[i]; + } + int threshold = min/2 + max/2; + for (i = 0; i < count; i++) + data[i] = data[i] > threshold; + printram("threshold=%d min=%d max=%d\n", + threshold, min, max); +} + static int discover_timC(ramctr_timing *ctrl, int channel, int slotrank) { int timC; @@ -1554,14 +1572,25 @@ } } FOR_ALL_LANES { - struct run rn = - get_longest_zero_run(statistics[lane], MAX_TIMC + 1); - ctrl->timings[channel][slotrank].lanes[lane].timC = rn.middle; - if (rn.all) { + struct run rn = get_longest_zero_run( + statistics[lane], ARRAY_SIZE(statistics[lane])); + if (rn.all || rn.length < 8) { printk(BIOS_EMERG, "timC discovery failed: %d, %d, %d\n", channel, slotrank, lane); - return MAKE_ERR; + /* With command training not happend yet, the lane can + * be erroneous. Take the avarage as reference and try + * again to find a run. + */ + timC_threshold_process(statistics[lane], + ARRAY_SIZE(statistics[lane])); + rn = get_longest_zero_run(statistics[lane], + ARRAY_SIZE(statistics[lane])); + if (rn.all || rn.length < 8) { + printk(BIOS_EMERG, "timC recovery failed\n"); + return MAKE_ERR; + } } + ctrl->timings[channel][slotrank].lanes[lane].timC = rn.middle; printram("timC: %d, %d, %d: 0x%02x-0x%02x-0x%02x\n", channel, slotrank, lane, rn.start, rn.middle, rn.end); } -- To view, visit https://review.coreboot.org/c/coreboot/+/22776 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9986616e86560c4980ccd8e3e549af53caa15c71 Gerrit-Change-Number: 22776 Gerrit-PatchSet: 4 Gerrit-Owner: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: mb/gigabyte/ga-b75m-d3{h,v}: Switch to a variant setup
by Alex James (Code Review) 29 May '19

29 May '19

Alex James has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32708 Change subject: mb/gigabyte/ga-b75m-d3{h,v}: Switch to a variant setup ...................................................................... mb/gigabyte/ga-b75m-d3{h,v}: Switch to a variant setup The Gigabyte GA-B75M_D3H/D3V mainboard trees share a lot of duplicate code, and can serve as a base for porting other Gigabyte 7 series motherboards. Switch the Gigabyte GA-B75M-D3H/D3V mainboard trees to a variant setup, defining ga-panther-point as a new common baseboard. Signed-off-by: Alex James <theracermaster(a)gmail.com> Change-Id: Ia175207a2568aefe1aa9bd8d4d990de6a26f1657 --- D src/mainboard/gigabyte/ga-b75m-d3h/Kconfig D src/mainboard/gigabyte/ga-b75m-d3h/Kconfig.name D src/mainboard/gigabyte/ga-b75m-d3h/mainboard.c D src/mainboard/gigabyte/ga-b75m-d3v/Kconfig D src/mainboard/gigabyte/ga-b75m-d3v/Kconfig.name D src/mainboard/gigabyte/ga-b75m-d3v/Makefile.inc D src/mainboard/gigabyte/ga-b75m-d3v/acpi/ec.asl D src/mainboard/gigabyte/ga-b75m-d3v/acpi/platform.asl D src/mainboard/gigabyte/ga-b75m-d3v/acpi/superio.asl D src/mainboard/gigabyte/ga-b75m-d3v/acpi/thermal.asl D src/mainboard/gigabyte/ga-b75m-d3v/acpi_tables.c D src/mainboard/gigabyte/ga-b75m-d3v/cmos.default D src/mainboard/gigabyte/ga-b75m-d3v/cmos.layout D src/mainboard/gigabyte/ga-b75m-d3v/dsdt.asl D src/mainboard/gigabyte/ga-b75m-d3v/mainboard.c D src/mainboard/gigabyte/ga-b75m-d3v/thermal.h A src/mainboard/gigabyte/ga-panther-point/Kconfig A src/mainboard/gigabyte/ga-panther-point/Kconfig.name R src/mainboard/gigabyte/ga-panther-point/Makefile.inc R src/mainboard/gigabyte/ga-panther-point/acpi/ec.asl R src/mainboard/gigabyte/ga-panther-point/acpi/mainboard.asl R src/mainboard/gigabyte/ga-panther-point/acpi/platform.asl R src/mainboard/gigabyte/ga-panther-point/acpi/thermal.asl R src/mainboard/gigabyte/ga-panther-point/acpi_tables.c A src/mainboard/gigabyte/ga-panther-point/board_info.txt R src/mainboard/gigabyte/ga-panther-point/cmos.default R src/mainboard/gigabyte/ga-panther-point/cmos.layout R src/mainboard/gigabyte/ga-panther-point/dsdt.asl R src/mainboard/gigabyte/ga-panther-point/hda_verb.c A src/mainboard/gigabyte/ga-panther-point/mainboard.c R src/mainboard/gigabyte/ga-panther-point/thermal.h R src/mainboard/gigabyte/ga-panther-point/variants/ga-b75m-d3h/board_info.txt R src/mainboard/gigabyte/ga-panther-point/variants/ga-b75m-d3h/devicetree.cb R src/mainboard/gigabyte/ga-panther-point/variants/ga-b75m-d3h/gma-mainboard.ads R src/mainboard/gigabyte/ga-panther-point/variants/ga-b75m-d3h/gpio.c R src/mainboard/gigabyte/ga-panther-point/variants/ga-b75m-d3h/include/variant/acpi/superio.asl C src/mainboard/gigabyte/ga-panther-point/variants/ga-b75m-d3h/include/variant/hda_verb.h A src/mainboard/gigabyte/ga-panther-point/variants/ga-b75m-d3h/include/variant/mainboard_init.h R src/mainboard/gigabyte/ga-panther-point/variants/ga-b75m-d3h/romstage.c R src/mainboard/gigabyte/ga-panther-point/variants/ga-b75m-d3v/board_info.txt R src/mainboard/gigabyte/ga-panther-point/variants/ga-b75m-d3v/devicetree.cb R src/mainboard/gigabyte/ga-panther-point/variants/ga-b75m-d3v/gma-mainboard.ads R src/mainboard/gigabyte/ga-panther-point/variants/ga-b75m-d3v/gpio.c C src/mainboard/gigabyte/ga-panther-point/variants/ga-b75m-d3v/include/variant/acpi/superio.asl R src/mainboard/gigabyte/ga-panther-point/variants/ga-b75m-d3v/include/variant/hda_verb.h A src/mainboard/gigabyte/ga-panther-point/variants/ga-b75m-d3v/include/variant/mainboard_init.h R src/mainboard/gigabyte/ga-panther-point/variants/ga-b75m-d3v/romstage.c 47 files changed, 236 insertions(+), 609 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/32708/1 diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig b/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig deleted file mode 100644 index 659f47c..0000000 --- a/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig +++ /dev/null @@ -1,48 +0,0 @@ -if BOARD_GIGABYTE_GA_B75M_D3H - -config BOARD_SPECIFIC_OPTIONS - def_bool y - select ARCH_X86 - select NORTHBRIDGE_INTEL_IVYBRIDGE - select USE_NATIVE_RAMINIT - select SOUTHBRIDGE_INTEL_C216 - select SUPERIO_ITE_IT8728F - select BOARD_ROMSIZE_KB_8192 - select HAVE_ACPI_TABLES - select HAVE_OPTION_TABLE - select HAVE_CMOS_DEFAULT - select HAVE_ACPI_RESUME - select INTEL_INT15 - select SERIRQ_CONTINUOUS_MODE - select MAINBOARD_HAS_LIBGFXINIT - select MAINBOARD_HAS_LPC_TPM - -config DRAM_RESET_GATE_GPIO - int - default 25 - -config USBDEBUG_HCD_INDEX - int - default 2 - -config MAINBOARD_DIR - string - default gigabyte/ga-b75m-d3h - -config MAINBOARD_PART_NUMBER - string - default "GA-B75M-D3H" - -config MAX_CPUS - int - default 8 - -config VGA_BIOS_ID - string - default "8086,0162" - -config VGA_BIOS_FILE - string - default "pci8086,0162.rom" - -endif # BOARD_GIGABYTE_GA_B75M_D3H diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig.name b/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig.name deleted file mode 100644 index 571f6d1..0000000 --- a/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_GIGABYTE_GA_B75M_D3H - bool "GA-B75M-D3H" diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/mainboard.c b/src/mainboard/gigabyte/ga-b75m-d3h/mainboard.c deleted file mode 100644 index 4e8d9f5..0000000 --- a/src/mainboard/gigabyte/ga-b75m-d3h/mainboard.c +++ /dev/null @@ -1,72 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011-2012 Google Inc. - * Copyright (C) 2014 Vladimir Serbinenko - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <device/device.h> -#include <drivers/intel/gma/int15.h> -#include <southbridge/intel/bd82x6x/pch.h> - -static void mainboard_init(struct device *dev) -{ - RCBA32(0x38c8) = 0x00002005; - RCBA32(0x38c4) = 0x00802005; - RCBA32(0x2240) = 0x00330e71; - RCBA32(0x2244) = 0x003f0eb1; - RCBA32(0x2248) = 0x002102cd; - RCBA32(0x224c) = 0x00f60000; - RCBA32(0x2250) = 0x00020000; - RCBA32(0x2254) = 0x00e3004c; - RCBA32(0x2258) = 0x00e20bef; - RCBA32(0x2260) = 0x003304ed; - RCBA32(0x2278) = 0x001107c1; - RCBA32(0x227c) = 0x001d07e9; - RCBA32(0x2280) = 0x00e20000; - RCBA32(0x2284) = 0x00ee0000; - RCBA32(0x2288) = 0x005b05d3; - RCBA32(0x2318) = 0x04b8ff2e; - RCBA32(0x231c) = 0x03930f2e; - RCBA32(0x3808) = 0x005044a3; - RCBA32(0x3810) = 0x52410000; - RCBA32(0x3814) = 0x0000008a; - RCBA32(0x3818) = 0x00000006; - RCBA32(0x381c) = 0x0000072e; - RCBA32(0x3820) = 0x0000000a; - RCBA32(0x3824) = 0x00000123; - RCBA32(0x3828) = 0x00000009; - RCBA32(0x382c) = 0x00000001; - RCBA32(0x3834) = 0x0000061a; - RCBA32(0x3838) = 0x00000003; - RCBA32(0x383c) = 0x00000a76; - RCBA32(0x3840) = 0x00000004; - RCBA32(0x3844) = 0x0000e5e4; - RCBA32(0x3848) = 0x0000000e; -} - -// mainboard_enable is executed as first thing after -// enumerate_buses(). - -static void mainboard_enable(struct device *dev) -{ - dev->ops->init = mainboard_init; - - install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_NONE, - GMA_INT15_PANEL_FIT_DEFAULT, - GMA_INT15_BOOT_DISPLAY_CRT, 0); -} - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, -}; diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/Kconfig b/src/mainboard/gigabyte/ga-b75m-d3v/Kconfig deleted file mode 100644 index e01d484..0000000 --- a/src/mainboard/gigabyte/ga-b75m-d3v/Kconfig +++ /dev/null @@ -1,47 +0,0 @@ -if BOARD_GIGABYTE_GA_B75M_D3V - -config BOARD_SPECIFIC_OPTIONS - def_bool y - select ARCH_X86 - select NORTHBRIDGE_INTEL_IVYBRIDGE - select USE_NATIVE_RAMINIT - select SOUTHBRIDGE_INTEL_C216 - select SUPERIO_ITE_IT8728F - select BOARD_ROMSIZE_KB_8192 - select HAVE_ACPI_TABLES - select HAVE_OPTION_TABLE - select HAVE_CMOS_DEFAULT - select HAVE_ACPI_RESUME - select INTEL_INT15 - select SERIRQ_CONTINUOUS_MODE - select MAINBOARD_HAS_LIBGFXINIT - -config DRAM_RESET_GATE_GPIO - int - default 25 - -config USBDEBUG_HCD_INDEX - int - default 2 - -config MAINBOARD_DIR - string - default gigabyte/ga-b75m-d3v - -config MAINBOARD_PART_NUMBER - string - default "GA-B75M-D3V" - -config MAX_CPUS - int - default 8 - -config VGA_BIOS_ID - string - default "8086,0102" - -config VGA_BIOS_FILE - string - default "pci8086,0102.rom" - -endif # BOARD_GIGABYTE_GA_B75M_D3V diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/Kconfig.name b/src/mainboard/gigabyte/ga-b75m-d3v/Kconfig.name deleted file mode 100644 index 92f5744..0000000 --- a/src/mainboard/gigabyte/ga-b75m-d3v/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_GIGABYTE_GA_B75M_D3V - bool "GA-B75M-D3V" diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/Makefile.inc b/src/mainboard/gigabyte/ga-b75m-d3v/Makefile.inc deleted file mode 100644 index 63976c4..0000000 --- a/src/mainboard/gigabyte/ga-b75m-d3v/Makefile.inc +++ /dev/null @@ -1,17 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -romstage-y += gpio.c -ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/acpi/ec.asl b/src/mainboard/gigabyte/ga-b75m-d3v/acpi/ec.asl deleted file mode 100644 index e69de29..0000000 --- a/src/mainboard/gigabyte/ga-b75m-d3v/acpi/ec.asl +++ /dev/null diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/acpi/platform.asl b/src/mainboard/gigabyte/ga-b75m-d3v/acpi/platform.asl deleted file mode 100644 index d8d3320..0000000 --- a/src/mainboard/gigabyte/ga-b75m-d3v/acpi/platform.asl +++ /dev/null @@ -1,29 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* The _PTS method (Prepare To Sleep) is called before the OS is - * entering a sleep state. The sleep state number is passed in Arg0 - */ - -Method(_PTS,1) -{ -} - -/* The _WAK method is called on system wakeup */ - -Method(_WAK,1) -{ - Return(Package(){0,0}) -} diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/acpi/superio.asl b/src/mainboard/gigabyte/ga-b75m-d3v/acpi/superio.asl deleted file mode 100644 index 4c50b6c..0000000 --- a/src/mainboard/gigabyte/ga-b75m-d3v/acpi/superio.asl +++ /dev/null @@ -1,4 +0,0 @@ -/* mainboard configuration */ - -#define SIO_EC_ENABLE_PS2K // Enable PS/2 Keyboard -#define SIO_ENABLE_PS2M // Enable PS/2 Mouse diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/acpi/thermal.asl b/src/mainboard/gigabyte/ga-b75m-d3v/acpi/thermal.asl deleted file mode 100644 index ca561a5..0000000 --- a/src/mainboard/gigabyte/ga-b75m-d3v/acpi/thermal.asl +++ /dev/null @@ -1,63 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -// Thermal Zone - -External (\PPKG, MethodObj) - -Scope (\_TZ) -{ - ThermalZone (THRM) - { - Name (_TC1, 0x02) - Name (_TC2, 0x03) - - // Thermal zone polling frequency: 10 seconds - Name (_TZP, 100) - - // Thermal sampling period for passive cooling: 10 seconds - Name (_TSP, 100) - - // Convert from Degrees C to 1/10 Kelvin for ACPI - Method (CTOK, 1) - { - // 10th of Degrees C - Multiply (Arg0, 10, Local0) - - // Convert to Kelvin - Add (Local0, 2732, Local0) - - Return (Local0) - } - - // Threshold for OS to shutdown - Method (_CRT, 0, Serialized) - { - Return (CTOK (\TCRT)) - } - - // Threshold for passive cooling - Method (_PSV, 0, Serialized) - { - Return (CTOK (\TPSV)) - } - - // Processors used for passive cooling - Method (_PSL, 0, Serialized) - { - Return (\PPKG ()) - } - } -} diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/acpi_tables.c b/src/mainboard/gigabyte/ga-b75m-d3v/acpi_tables.c deleted file mode 100644 index 5c09059..0000000 --- a/src/mainboard/gigabyte/ga-b75m-d3v/acpi_tables.c +++ /dev/null @@ -1,39 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <string.h> -#include <southbridge/intel/bd82x6x/nvs.h> -#include "thermal.h" - -static void acpi_update_thermal_table(global_nvs_t *gnvs) -{ - gnvs->tcrt = CRITICAL_TEMPERATURE; - gnvs->tpsv = PASSIVE_TEMPERATURE; -} - -void acpi_create_gnvs(global_nvs_t *gnvs) -{ - memset((void *)gnvs, 0, sizeof(*gnvs)); - - /* Disable USB ports in S3 by default */ - gnvs->s3u0 = 0; - gnvs->s3u1 = 0; - - /* Disable USB ports in S5 by default */ - gnvs->s5u0 = 0; - gnvs->s5u1 = 0; - - acpi_update_thermal_table(gnvs); -} diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/cmos.default b/src/mainboard/gigabyte/ga-b75m-d3v/cmos.default deleted file mode 100644 index 6f3cec7..0000000 --- a/src/mainboard/gigabyte/ga-b75m-d3v/cmos.default +++ /dev/null @@ -1,6 +0,0 @@ -boot_option=Fallback -debug_level=Debug -power_on_after_fail=Enable -nmi=Enable -sata_mode=AHCI -gfx_uma_size=32M diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/cmos.layout b/src/mainboard/gigabyte/ga-b75m-d3v/cmos.layout deleted file mode 100644 index 095e383..0000000 --- a/src/mainboard/gigabyte/ga-b75m-d3v/cmos.layout +++ /dev/null @@ -1,107 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007-2008 coresystems GmbH -## Copyright (C) 2014 Vladimir Serbinenko -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -# ----------------------------------------------------------------- -entries - -# ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - -# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused - -# ----------------------------------------------------------------- -# RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#390 2 r 0 unused? - -# ----------------------------------------------------------------- -# coreboot config options: console -#392 3 r 0 unused -395 4 e 6 debug_level -#399 1 r 0 unused - -# coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail - -#411 10 r 0 unused -421 1 e 9 sata_mode -#422 2 r 0 unused - -# coreboot config options: cpu -#425 7 r 0 unused - -# coreboot config options: northbridge -432 3 e 11 gfx_uma_size -#435 549 r 0 unused - -# coreboot config options: check sums -984 16 h 0 check_sum - -# ----------------------------------------------------------------- - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -9 0 AHCI -9 1 IDE -11 0 32M -11 1 64M -11 2 96M -11 3 128M -11 4 160M -11 5 192M -11 6 224M - -# ----------------------------------------------------------------- -checksums - -checksum 392 439 984 diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/dsdt.asl b/src/mainboard/gigabyte/ga-b75m-d3v/dsdt.asl deleted file mode 100644 index 67054cc..0000000 --- a/src/mainboard/gigabyte/ga-b75m-d3v/dsdt.asl +++ /dev/null @@ -1,41 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/acpi.h> -DefinitionBlock( - "dsdt.aml", - "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up - OEM_ID, - ACPI_TABLE_CREATOR, - 0x20141018 // OEM revision -) -{ - #include <southbridge/intel/bd82x6x/acpi/platform.asl> - - // Some generic macros - #include "acpi/platform.asl" - #include <cpu/intel/common/acpi/cpu.asl> - /* global NVS and variables. */ - #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> - #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> - - Scope (\_SB) { - Device (PCI0) - { - #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> - #include <southbridge/intel/bd82x6x/acpi/pch.asl> - #include <drivers/intel/gma/acpi/default_brightness_levels.asl> - } - } -} diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/mainboard.c b/src/mainboard/gigabyte/ga-b75m-d3v/mainboard.c deleted file mode 100644 index 4e8d9f5..0000000 --- a/src/mainboard/gigabyte/ga-b75m-d3v/mainboard.c +++ /dev/null @@ -1,72 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011-2012 Google Inc. - * Copyright (C) 2014 Vladimir Serbinenko - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <device/device.h> -#include <drivers/intel/gma/int15.h> -#include <southbridge/intel/bd82x6x/pch.h> - -static void mainboard_init(struct device *dev) -{ - RCBA32(0x38c8) = 0x00002005; - RCBA32(0x38c4) = 0x00802005; - RCBA32(0x2240) = 0x00330e71; - RCBA32(0x2244) = 0x003f0eb1; - RCBA32(0x2248) = 0x002102cd; - RCBA32(0x224c) = 0x00f60000; - RCBA32(0x2250) = 0x00020000; - RCBA32(0x2254) = 0x00e3004c; - RCBA32(0x2258) = 0x00e20bef; - RCBA32(0x2260) = 0x003304ed; - RCBA32(0x2278) = 0x001107c1; - RCBA32(0x227c) = 0x001d07e9; - RCBA32(0x2280) = 0x00e20000; - RCBA32(0x2284) = 0x00ee0000; - RCBA32(0x2288) = 0x005b05d3; - RCBA32(0x2318) = 0x04b8ff2e; - RCBA32(0x231c) = 0x03930f2e; - RCBA32(0x3808) = 0x005044a3; - RCBA32(0x3810) = 0x52410000; - RCBA32(0x3814) = 0x0000008a; - RCBA32(0x3818) = 0x00000006; - RCBA32(0x381c) = 0x0000072e; - RCBA32(0x3820) = 0x0000000a; - RCBA32(0x3824) = 0x00000123; - RCBA32(0x3828) = 0x00000009; - RCBA32(0x382c) = 0x00000001; - RCBA32(0x3834) = 0x0000061a; - RCBA32(0x3838) = 0x00000003; - RCBA32(0x383c) = 0x00000a76; - RCBA32(0x3840) = 0x00000004; - RCBA32(0x3844) = 0x0000e5e4; - RCBA32(0x3848) = 0x0000000e; -} - -// mainboard_enable is executed as first thing after -// enumerate_buses(). - -static void mainboard_enable(struct device *dev) -{ - dev->ops->init = mainboard_init; - - install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_NONE, - GMA_INT15_PANEL_FIT_DEFAULT, - GMA_INT15_BOOT_DISPLAY_CRT, 0); -} - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, -}; diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/thermal.h b/src/mainboard/gigabyte/ga-b75m-d3v/thermal.h deleted file mode 100644 index 9db6910..0000000 --- a/src/mainboard/gigabyte/ga-b75m-d3v/thermal.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. - * Copyright (C) 2014 Vladimir Serbinenko - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef GAB75MD3H_THERMAL_H -#define GAB75MD3H_THERMAL_H - - /* Temperature which OS will shutdown at */ - #define CRITICAL_TEMPERATURE 100 - - /* Temperature which OS will throttle CPU */ - #define PASSIVE_TEMPERATURE 90 - -#endif diff --git a/src/mainboard/gigabyte/ga-panther-point/Kconfig b/src/mainboard/gigabyte/ga-panther-point/Kconfig new file mode 100644 index 0000000..583e967 --- /dev/null +++ b/src/mainboard/gigabyte/ga-panther-point/Kconfig @@ -0,0 +1,73 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2018 Angel Pons <th3fanbus(a)gmail.com> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +config BOARD_GIGABYTE_BASEBOARD_GA_PANTHER_POINT + def_bool n + select ARCH_X86 + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_INT15 + select NORTHBRIDGE_INTEL_SANDYBRIDGE + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_BD82X6X + select USE_NATIVE_RAMINIT + select SUPERIO_ITE_IT8728F + select MAINBOARD_HAS_LIBGFXINIT + select INTEL_GMA_HAVE_VBT + select HAVE_OPTION_TABLE + select HAVE_CMOS_DEFAULT + +if BOARD_GIGABYTE_BASEBOARD_GA_PANTHER_POINT + +config MAINBOARD_DIR + string + default "gigabyte/ga-panther-point" + +config VARIANT_DIR + string + default "ga-b75m-d3h" if BOARD_GIGABYTE_GA_B75M_D3H + default "ga-b75m-d3v" if BOARD_GIGABYTE_GA_B75M_D3V + +config MAINBOARD_PART_NUMBER + string + default "GA-B75M-D3H" if BOARD_GIGABYTE_GA_B75M_D3H + default "GA-B75M-D3V" if BOARD_GIGABYTE_GA_B75M_D3V + +config DEVICETREE + string + default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" + +config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID + hex + default 0x5001 + +config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID + hex + default 0x1458 + +config MAX_CPUS + int + default 8 + +config VGA_BIOS_ID + string + default "8086,0162" + +config VGA_BIOS_FILE + string + default "pci8086,0162.rom" + +endif # BOARD_GIGABYTE_BASEBOARD_GA_PANTHER_POINT diff --git a/src/mainboard/gigabyte/ga-panther-point/Kconfig.name b/src/mainboard/gigabyte/ga-panther-point/Kconfig.name new file mode 100644 index 0000000..19216e2 --- /dev/null +++ b/src/mainboard/gigabyte/ga-panther-point/Kconfig.name @@ -0,0 +1,7 @@ +config BOARD_GIGABYTE_GA_B75M_D3H + bool "GA-B75M-D3H" + select BOARD_GIGABYTE_BASEBOARD_GA_PANTHER_POINT + +config BOARD_GIGABYTE_GA_B75M_D3V + bool "GA-B75M-D3V" + select BOARD_GIGABYTE_BASEBOARD_GA_PANTHER_POINT diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/Makefile.inc b/src/mainboard/gigabyte/ga-panther-point/Makefile.inc similarity index 65% rename from src/mainboard/gigabyte/ga-b75m-d3h/Makefile.inc rename to src/mainboard/gigabyte/ga-panther-point/Makefile.inc index 63976c4..08a9957 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/Makefile.inc +++ b/src/mainboard/gigabyte/ga-panther-point/Makefile.inc @@ -13,5 +13,11 @@ ## GNU General Public License for more details. ## -romstage-y += gpio.c -ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +romstage-y += variants/$(VARIANT_DIR)/gpio.c +romstage-y += variants/$(VARIANT_DIR)/romstage.c + +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainboard.ads + +subdirs-y += variants/$(VARIANT_DIR) + +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/acpi/ec.asl b/src/mainboard/gigabyte/ga-panther-point/acpi/ec.asl similarity index 100% rename from src/mainboard/gigabyte/ga-b75m-d3h/acpi/ec.asl rename to src/mainboard/gigabyte/ga-panther-point/acpi/ec.asl diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/acpi/mainboard.asl b/src/mainboard/gigabyte/ga-panther-point/acpi/mainboard.asl similarity index 100% rename from src/mainboard/gigabyte/ga-b75m-d3h/acpi/mainboard.asl rename to src/mainboard/gigabyte/ga-panther-point/acpi/mainboard.asl diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/acpi/platform.asl b/src/mainboard/gigabyte/ga-panther-point/acpi/platform.asl similarity index 92% rename from src/mainboard/gigabyte/ga-b75m-d3h/acpi/platform.asl rename to src/mainboard/gigabyte/ga-panther-point/acpi/platform.asl index 0603164..7a3e682 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/acpi/platform.asl +++ b/src/mainboard/gigabyte/ga-panther-point/acpi/platform.asl @@ -17,14 +17,13 @@ * entering a sleep state. The sleep state number is passed in Arg0 */ -Method(_PTS,1) +Method (_PTS, 1) { - } /* The _WAK method is called on system wakeup */ -Method(_WAK,1) +Method (_WAK, 1) { - Return(Package(){0,0}) + Return (Package () {0,0}) } diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/acpi/thermal.asl b/src/mainboard/gigabyte/ga-panther-point/acpi/thermal.asl similarity index 100% rename from src/mainboard/gigabyte/ga-b75m-d3h/acpi/thermal.asl rename to src/mainboard/gigabyte/ga-panther-point/acpi/thermal.asl diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/acpi_tables.c b/src/mainboard/gigabyte/ga-panther-point/acpi_tables.c similarity index 93% rename from src/mainboard/gigabyte/ga-b75m-d3h/acpi_tables.c rename to src/mainboard/gigabyte/ga-panther-point/acpi_tables.c index 5c09059..3009a1c 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/acpi_tables.c +++ b/src/mainboard/gigabyte/ga-panther-point/acpi_tables.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <string.h> #include <southbridge/intel/bd82x6x/nvs.h> #include "thermal.h" @@ -25,8 +24,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs) { - memset((void *)gnvs, 0, sizeof(*gnvs)); - /* Disable USB ports in S3 by default */ gnvs->s3u0 = 0; gnvs->s3u1 = 0; diff --git a/src/mainboard/gigabyte/ga-panther-point/board_info.txt b/src/mainboard/gigabyte/ga-panther-point/board_info.txt new file mode 100644 index 0000000..0116ddb --- /dev/null +++ b/src/mainboard/gigabyte/ga-panther-point/board_info.txt @@ -0,0 +1,6 @@ +Category: desktop +Board name: Gigabyte Panther Point (7 series) baseboard +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/cmos.default b/src/mainboard/gigabyte/ga-panther-point/cmos.default similarity index 100% rename from src/mainboard/gigabyte/ga-b75m-d3h/cmos.default rename to src/mainboard/gigabyte/ga-panther-point/cmos.default diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/cmos.layout b/src/mainboard/gigabyte/ga-panther-point/cmos.layout similarity index 100% rename from src/mainboard/gigabyte/ga-b75m-d3h/cmos.layout rename to src/mainboard/gigabyte/ga-panther-point/cmos.layout diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl b/src/mainboard/gigabyte/ga-panther-point/dsdt.asl similarity index 85% rename from src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl rename to src/mainboard/gigabyte/ga-panther-point/dsdt.asl index 67054cc..d7590c1 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl +++ b/src/mainboard/gigabyte/ga-panther-point/dsdt.asl @@ -1,6 +1,8 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2018 Angel Pons <th3fanbus(a)gmail.com> + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -21,12 +23,15 @@ 0x20141018 // OEM revision ) { + // Some generic macros + #include "acpi/mainboard.asl" + #include "acpi/platform.asl" + #include <variant/acpi/superio.asl> + #include "acpi/thermal.asl" + #include <cpu/intel/common/acpi/cpu.asl> #include <southbridge/intel/bd82x6x/acpi/platform.asl> - // Some generic macros - #include "acpi/platform.asl" - #include <cpu/intel/common/acpi/cpu.asl> - /* global NVS and variables. */ + /* global NVS and variables. */ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> @@ -34,8 +39,8 @@ Device (PCI0) { #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> - #include <southbridge/intel/bd82x6x/acpi/pch.asl> #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> } } } diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/hda_verb.c b/src/mainboard/gigabyte/ga-panther-point/hda_verb.c similarity index 88% rename from src/mainboard/gigabyte/ga-b75m-d3h/hda_verb.c rename to src/mainboard/gigabyte/ga-panther-point/hda_verb.c index 23cd570..34610f0 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/hda_verb.c +++ b/src/mainboard/gigabyte/ga-panther-point/hda_verb.c @@ -13,9 +13,7 @@ #include <device/azalia_device.h> -const u32 cim_verb_data[] = { - /* FIXME: Add configuration for sound */ -}; +#include <variant/hda_verb.h> const u32 pc_beep_verbs[] = {}; diff --git a/src/mainboard/gigabyte/ga-panther-point/mainboard.c b/src/mainboard/gigabyte/ga-panther-point/mainboard.c new file mode 100644 index 0000000..a7cad83 --- /dev/null +++ b/src/mainboard/gigabyte/ga-panther-point/mainboard.c @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Angel Pons <th3fanbus(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <drivers/intel/gma/int15.h> +#include <southbridge/intel/bd82x6x/pch.h> + +#include <variant/mainboard_init.h> + +static void mainboard_enable(struct device *dev) +{ + dev->ops->init = mainboard_init; + + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_NONE, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/thermal.h b/src/mainboard/gigabyte/ga-panther-point/thermal.h similarity index 73% rename from src/mainboard/gigabyte/ga-b75m-d3h/thermal.h rename to src/mainboard/gigabyte/ga-panther-point/thermal.h index 9db6910..87c420b 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/thermal.h +++ b/src/mainboard/gigabyte/ga-panther-point/thermal.h @@ -14,13 +14,13 @@ * GNU General Public License for more details. */ -#ifndef GAB75MD3H_THERMAL_H -#define GAB75MD3H_THERMAL_H +#ifndef GA_PANTHER_POINT_THERMAL_H +#define GA_PANTHER_POINT_THERMAL_H - /* Temperature which OS will shutdown at */ - #define CRITICAL_TEMPERATURE 100 +/* Temperature which OS will shutdown at */ +#define CRITICAL_TEMPERATURE 100 - /* Temperature which OS will throttle CPU */ - #define PASSIVE_TEMPERATURE 90 +/* Temperature which OS will throttle CPU */ +#define PASSIVE_TEMPERATURE 90 #endif diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/board_info.txt b/src/mainboard/gigabyte/ga-panther-point/variants/ga-b75m-d3h/board_info.txt similarity index 100% rename from src/mainboard/gigabyte/ga-b75m-d3h/board_info.txt rename to src/mainboard/gigabyte/ga-panther-point/variants/ga-b75m-d3h/board_info.txt diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb b/src/mainboard/gigabyte/ga-panther-point/variants/ga-b75m-d3h/devicetree.cb similarity index 100% rename from src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb rename to src/mainboard/gigabyte/ga-panther-point/variants/ga-b75m-d3h/devicetree.cb diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/gma-mainboard.ads b/src/mainboard/gigabyte/ga-panther-point/variants/ga-b75m-d3h/gma-mainboard.ads similarity index 100% rename from src/mainboard/gigabyte/ga-b75m-d3h/gma-mainboard.ads rename to src/mainboard/gigabyte/ga-panther-point/variants/ga-b75m-d3h/gma-mainboard.ads diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/gpio.c b/src/mainboard/gigabyte/ga-panther-point/variants/ga-b75m-d3h/gpio.c similarity index 100% rename from src/mainboard/gigabyte/ga-b75m-d3h/gpio.c rename to src/mainboard/gigabyte/ga-panther-point/variants/ga-b75m-d3h/gpio.c diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/acpi/superio.asl b/src/mainboard/gigabyte/ga-panther-point/variants/ga-b75m-d3h/include/variant/acpi/superio.asl similarity index 100% rename from src/mainboard/gigabyte/ga-b75m-d3h/acpi/superio.asl rename to src/mainboard/gigabyte/ga-panther-point/variants/ga-b75m-d3h/include/variant/acpi/superio.asl diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/hda_verb.c b/src/mainboard/gigabyte/ga-panther-point/variants/ga-b75m-d3h/include/variant/hda_verb.h similarity index 86% copy from src/mainboard/gigabyte/ga-b75m-d3h/hda_verb.c copy to src/mainboard/gigabyte/ga-panther-point/variants/ga-b75m-d3h/include/variant/hda_verb.h index 23cd570..fdc86d3 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/hda_verb.c +++ b/src/mainboard/gigabyte/ga-panther-point/variants/ga-b75m-d3h/include/variant/hda_verb.h @@ -1,3 +1,6 @@ +#ifndef GA_B75M_D3H_HDA_VERB_H +#define GA_B75M_D3H_HDA_VERB_H + /* * This file is part of the coreboot project. * @@ -11,12 +14,8 @@ * GNU General Public License for more details. */ -#include <device/azalia_device.h> - const u32 cim_verb_data[] = { /* FIXME: Add configuration for sound */ }; -const u32 pc_beep_verbs[] = {}; - -AZALIA_ARRAY_SIZES; +#endif diff --git a/src/mainboard/gigabyte/ga-panther-point/variants/ga-b75m-d3h/include/variant/mainboard_init.h b/src/mainboard/gigabyte/ga-panther-point/variants/ga-b75m-d3h/include/variant/mainboard_init.h new file mode 100644 index 0000000..d1fa56a --- /dev/null +++ b/src/mainboard/gigabyte/ga-panther-point/variants/ga-b75m-d3h/include/variant/mainboard_init.h @@ -0,0 +1,40 @@ +#ifndef GA_B75M_D3H_MAINBOARD_INIT_H +#define GA_B75M_D3H_MAINBOARD_INIT_H + +static void mainboard_init(struct device *dev) +{ + RCBA32(0x38c8) = 0x00002005; + RCBA32(0x38c4) = 0x00802005; + RCBA32(0x2240) = 0x00330e71; + RCBA32(0x2244) = 0x003f0eb1; + RCBA32(0x2248) = 0x002102cd; + RCBA32(0x224c) = 0x00f60000; + RCBA32(0x2250) = 0x00020000; + RCBA32(0x2254) = 0x00e3004c; + RCBA32(0x2258) = 0x00e20bef; + RCBA32(0x2260) = 0x003304ed; + RCBA32(0x2278) = 0x001107c1; + RCBA32(0x227c) = 0x001d07e9; + RCBA32(0x2280) = 0x00e20000; + RCBA32(0x2284) = 0x00ee0000; + RCBA32(0x2288) = 0x005b05d3; + RCBA32(0x2318) = 0x04b8ff2e; + RCBA32(0x231c) = 0x03930f2e; + RCBA32(0x3808) = 0x005044a3; + RCBA32(0x3810) = 0x52410000; + RCBA32(0x3814) = 0x0000008a; + RCBA32(0x3818) = 0x00000006; + RCBA32(0x381c) = 0x0000072e; + RCBA32(0x3820) = 0x0000000a; + RCBA32(0x3824) = 0x00000123; + RCBA32(0x3828) = 0x00000009; + RCBA32(0x382c) = 0x00000001; + RCBA32(0x3834) = 0x0000061a; + RCBA32(0x3838) = 0x00000003; + RCBA32(0x383c) = 0x00000a76; + RCBA32(0x3840) = 0x00000004; + RCBA32(0x3844) = 0x0000e5e4; + RCBA32(0x3848) = 0x0000000e; +} + +#endif diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c b/src/mainboard/gigabyte/ga-panther-point/variants/ga-b75m-d3h/romstage.c similarity index 100% rename from src/mainboard/gigabyte/ga-b75m-d3h/romstage.c rename to src/mainboard/gigabyte/ga-panther-point/variants/ga-b75m-d3h/romstage.c diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/board_info.txt b/src/mainboard/gigabyte/ga-panther-point/variants/ga-b75m-d3v/board_info.txt similarity index 89% rename from src/mainboard/gigabyte/ga-b75m-d3v/board_info.txt rename to src/mainboard/gigabyte/ga-panther-point/variants/ga-b75m-d3v/board_info.txt index ede1945..5c78691 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3v/board_info.txt +++ b/src/mainboard/gigabyte/ga-panther-point/variants/ga-b75m-d3v/board_info.txt @@ -4,4 +4,4 @@ ROM protocol: SPI ROM socketed: n Flashrom support: y -Release date: 2012 +Release year: 2012 diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/devicetree.cb b/src/mainboard/gigabyte/ga-panther-point/variants/ga-b75m-d3v/devicetree.cb similarity index 100% rename from src/mainboard/gigabyte/ga-b75m-d3v/devicetree.cb rename to src/mainboard/gigabyte/ga-panther-point/variants/ga-b75m-d3v/devicetree.cb diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/gma-mainboard.ads b/src/mainboard/gigabyte/ga-panther-point/variants/ga-b75m-d3v/gma-mainboard.ads similarity index 100% rename from src/mainboard/gigabyte/ga-b75m-d3v/gma-mainboard.ads rename to src/mainboard/gigabyte/ga-panther-point/variants/ga-b75m-d3v/gma-mainboard.ads diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/gpio.c b/src/mainboard/gigabyte/ga-panther-point/variants/ga-b75m-d3v/gpio.c similarity index 100% rename from src/mainboard/gigabyte/ga-b75m-d3v/gpio.c rename to src/mainboard/gigabyte/ga-panther-point/variants/ga-b75m-d3v/gpio.c diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/acpi/superio.asl b/src/mainboard/gigabyte/ga-panther-point/variants/ga-b75m-d3v/include/variant/acpi/superio.asl similarity index 100% copy from src/mainboard/gigabyte/ga-b75m-d3h/acpi/superio.asl copy to src/mainboard/gigabyte/ga-panther-point/variants/ga-b75m-d3v/include/variant/acpi/superio.asl diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/hda_verb.c b/src/mainboard/gigabyte/ga-panther-point/variants/ga-b75m-d3v/include/variant/hda_verb.h similarity index 92% rename from src/mainboard/gigabyte/ga-b75m-d3v/hda_verb.c rename to src/mainboard/gigabyte/ga-panther-point/variants/ga-b75m-d3v/include/variant/hda_verb.h index 3ae6b5d..120e347 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3v/hda_verb.c +++ b/src/mainboard/gigabyte/ga-panther-point/variants/ga-b75m-d3v/include/variant/hda_verb.h @@ -1,3 +1,6 @@ +#ifndef GA_B75M_D3V_HDA_VERB_H +#define GA_B75M_D3V_HDA_VERB_H + /* * This file is part of the coreboot project. * @@ -11,8 +14,6 @@ * GNU General Public License for more details. */ -#include <device/azalia_device.h> - const u32 cim_verb_data[] = { /* coreboot specific header */ 0x10ec0887, // Realtek 887 @@ -36,6 +37,4 @@ AZALIA_PIN_CFG(0, 0x1f, 0x411111f0) }; -const u32 pc_beep_verbs[] = {}; - -AZALIA_ARRAY_SIZES; +#endif diff --git a/src/mainboard/gigabyte/ga-panther-point/variants/ga-b75m-d3v/include/variant/mainboard_init.h b/src/mainboard/gigabyte/ga-panther-point/variants/ga-b75m-d3v/include/variant/mainboard_init.h new file mode 100644 index 0000000..7f10282 --- /dev/null +++ b/src/mainboard/gigabyte/ga-panther-point/variants/ga-b75m-d3v/include/variant/mainboard_init.h @@ -0,0 +1,40 @@ +#ifndef GA_B75M_D3V_MAINBOARD_INIT_H +#define GA_B75M_D3V_MAINBOARD_INIT_H + +static void mainboard_init(struct device *dev) +{ + RCBA32(0x38c8) = 0x00002005; + RCBA32(0x38c4) = 0x00802005; + RCBA32(0x2240) = 0x00330e71; + RCBA32(0x2244) = 0x003f0eb1; + RCBA32(0x2248) = 0x002102cd; + RCBA32(0x224c) = 0x00f60000; + RCBA32(0x2250) = 0x00020000; + RCBA32(0x2254) = 0x00e3004c; + RCBA32(0x2258) = 0x00e20bef; + RCBA32(0x2260) = 0x003304ed; + RCBA32(0x2278) = 0x001107c1; + RCBA32(0x227c) = 0x001d07e9; + RCBA32(0x2280) = 0x00e20000; + RCBA32(0x2284) = 0x00ee0000; + RCBA32(0x2288) = 0x005b05d3; + RCBA32(0x2318) = 0x04b8ff2e; + RCBA32(0x231c) = 0x03930f2e; + RCBA32(0x3808) = 0x005044a3; + RCBA32(0x3810) = 0x52410000; + RCBA32(0x3814) = 0x0000008a; + RCBA32(0x3818) = 0x00000006; + RCBA32(0x381c) = 0x0000072e; + RCBA32(0x3820) = 0x0000000a; + RCBA32(0x3824) = 0x00000123; + RCBA32(0x3828) = 0x00000009; + RCBA32(0x382c) = 0x00000001; + RCBA32(0x3834) = 0x0000061a; + RCBA32(0x3838) = 0x00000003; + RCBA32(0x383c) = 0x00000a76; + RCBA32(0x3840) = 0x00000004; + RCBA32(0x3844) = 0x0000e5e4; + RCBA32(0x3848) = 0x0000000e; +} + +#endif diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c b/src/mainboard/gigabyte/ga-panther-point/variants/ga-b75m-d3v/romstage.c similarity index 100% rename from src/mainboard/gigabyte/ga-b75m-d3v/romstage.c rename to src/mainboard/gigabyte/ga-panther-point/variants/ga-b75m-d3v/romstage.c -- To view, visit https://review.coreboot.org/c/coreboot/+/32708 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia175207a2568aefe1aa9bd8d4d990de6a26f1657 Gerrit-Change-Number: 32708 Gerrit-PatchSet: 1 Gerrit-Owner: Alex James <theracermaster(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: Documentation: Warn about ME cleaner on Sandy Bridge
by Patrick Rudolph (Code Review) 29 May '19

29 May '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32889 Change subject: Documentation: Warn about ME cleaner on Sandy Bridge ...................................................................... Documentation: Warn about ME cleaner on Sandy Bridge Document known issues with 'disabled' ME. Change-Id: I364f3ed49341523c781eb2f3b41e866f33632a7e Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M Documentation/northbridge/intel/sandybridge/index.md A Documentation/northbridge/intel/sandybridge/me_cleaner.md 2 files changed, 13 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/32889/1 diff --git a/Documentation/northbridge/intel/sandybridge/index.md b/Documentation/northbridge/intel/sandybridge/index.md index dcb090a..c1d4b99 100644 --- a/Documentation/northbridge/intel/sandybridge/index.md +++ b/Documentation/northbridge/intel/sandybridge/index.md @@ -6,3 +6,4 @@ - [Native Ram Initialization](nri.md) - [RAM initialization feature matrix](nri_features.md) +- [ME Cleaner](me_cleaner.md) diff --git a/Documentation/northbridge/intel/sandybridge/me_cleaner.md b/Documentation/northbridge/intel/sandybridge/me_cleaner.md new file mode 100644 index 0000000..25938a5 --- /dev/null +++ b/Documentation/northbridge/intel/sandybridge/me_cleaner.md @@ -0,0 +1,12 @@ +# ME Cleaner +It's possible to 'clean' the ME partition within the flash medium as part +of the build process. Using a 'cleaned' ME partition is *not* +recommomended. + +## Observations with 'cleaned' ME + +* Instable LPC bus + * SuperIO is malfunctioning + * TPM is malfunctioning + * Random system shutdowns on high bus activity + -- To view, visit https://review.coreboot.org/c/coreboot/+/32889 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I364f3ed49341523c781eb2f3b41e866f33632a7e Gerrit-Change-Number: 32889 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

6 12

Change in ...coreboot[master]: mb/google/sarien: Send post code to the EC
by EricR Lai (Code Review) 29 May '19

29 May '19

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33047 Change subject: mb/google/sarien: Send post code to the EC ...................................................................... mb/google/sarien: Send post code to the EC Use the mainboard post code hook to inform the wilco EC driver of the every stage. BUG=b:124401932,b:133466714,b:133600566 BRANCH=sarien TEST=Remove DIMM module, confirm diagnostic LED pattern for memory failure (2 amber, 4 white). Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: Ic71e4a6e62b63ca2fd189957c4d6f49b61b934de --- M src/mainboard/google/sarien/Makefile.inc A src/mainboard/google/sarien/ec.c M src/mainboard/google/sarien/ramstage.c M src/mainboard/google/sarien/romstage.c M src/mainboard/google/sarien/variants/sarien/include/variant/ec.h 5 files changed, 33 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/33047/1 diff --git a/src/mainboard/google/sarien/Makefile.inc b/src/mainboard/google/sarien/Makefile.inc index 6fd23ce..7c37bc9 100644 --- a/src/mainboard/google/sarien/Makefile.inc +++ b/src/mainboard/google/sarien/Makefile.inc @@ -29,5 +29,10 @@ ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB) += hda_verb.c +bootblock-$(CONFIG_EC_GOOGLE_WILCO) += ec.c +ramstage-$(CONFIG_EC_GOOGLE_WILCO) += ec.c +romstage-$(CONFIG_EC_GOOGLE_WILCO) += ec.c +verstage-$(CONFIG_EC_GOOGLE_WILCO) += ec.c + subdirs-y += variants/$(VARIANT_DIR) CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include diff --git a/src/mainboard/google/sarien/ec.c b/src/mainboard/google/sarien/ec.c new file mode 100644 index 0000000..acf6877 --- /dev/null +++ b/src/mainboard/google/sarien/ec.c @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <ec/google/wilco/commands.h> +#include <variant/ec.h> + +void mainboard_post(uint8_t value) +{ + wilco_ec_save_post_code(value); +} + diff --git a/src/mainboard/google/sarien/ramstage.c b/src/mainboard/google/sarien/ramstage.c index e246419..2c296dc 100644 --- a/src/mainboard/google/sarien/ramstage.c +++ b/src/mainboard/google/sarien/ramstage.c @@ -15,12 +15,12 @@ #include <arch/acpi.h> #include <drivers/vpd/vpd.h> -#include <ec/google/wilco/commands.h> #include <smbios.h> #include <soc/gpio.h> #include <soc/ramstage.h> #include <variant/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> +#include <variant/ec.h> #if CONFIG(GENERATE_SMBIOS_TABLES) #define VPD_KEY_SYSTEM_SERIAL "serial_number" @@ -70,11 +70,6 @@ cnl_configure_pads(gpio_table, num_gpios); } -void mainboard_post(uint8_t value) -{ - wilco_ec_save_post_code(value); -} - static void mainboard_enable(struct device *dev) { dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; diff --git a/src/mainboard/google/sarien/romstage.c b/src/mainboard/google/sarien/romstage.c index 20eee7f..fe8d03e 100644 --- a/src/mainboard/google/sarien/romstage.c +++ b/src/mainboard/google/sarien/romstage.c @@ -16,6 +16,7 @@ #include <ec/google/wilco/romstage.h> #include <soc/cnl_memcfg_init.h> #include <soc/romstage.h> +#include <variant/ec.h> static const struct cnl_mb_cfg memcfg = { /* Access memory info through SMBUS. */ diff --git a/src/mainboard/google/sarien/variants/sarien/include/variant/ec.h b/src/mainboard/google/sarien/variants/sarien/include/variant/ec.h index 01a17b5..9358deb 100644 --- a/src/mainboard/google/sarien/variants/sarien/include/variant/ec.h +++ b/src/mainboard/google/sarien/variants/sarien/include/variant/ec.h @@ -18,6 +18,7 @@ #include <soc/gpe.h> #include <soc/gpio.h> +#include <console/console.h> /* EC wake pin */ #define EC_WAKE_PIN GPE0_DW1_12 @@ -31,4 +32,6 @@ /* Enable DPTF */ #define EC_ENABLE_DPTF +void mainboard_post(uint8_t value); + #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/33047 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic71e4a6e62b63ca2fd189957c4d6f49b61b934de Gerrit-Change-Number: 33047 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

4 6

Change in ...coreboot[master]: sb/intel/common/smihandler: Hook up smmstore
by Arthur Heymans (Code Review) 29 May '19

29 May '19

Hello Matthew Garrett, Patrick Rudolph, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/30012 to look at the new patch set (#15). Change subject: sb/intel/common/smihandler: Hook up smmstore ...................................................................... sb/intel/common/smihandler: Hook up smmstore TESTED on Asus P5QC. Change-Id: I20b87f3dcb898656ad31478820dd5153e4053cb2 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/southbridge/intel/common/Kconfig M src/southbridge/intel/common/smihandler.c 2 files changed, 26 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/30012/15 -- To view, visit https://review.coreboot.org/c/coreboot/+/30012 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I20b87f3dcb898656ad31478820dd5153e4053cb2 Gerrit-Change-Number: 30012 Gerrit-PatchSet: 15 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matthew Garrett <mjg59(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newpatchset

1 0

Change in ...coreboot[master]: arch/x86: Do not add properties to null DP packages
by Jacob Garber (Code Review) 29 May '19

29 May '19

Jacob Garber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32971 Change subject: arch/x86: Do not add properties to null DP packages ...................................................................... arch/x86: Do not add properties to null DP packages It doesn't make sense to add a property to a non-existent device property package. However, some of these functions will proceed anyway and allocate a new device property package, add the property to that, and then immediately leak the new package. This changes all the acpi_dp_add_* functions to ignore a null package. Signed-off-by: Jacob Garber <jgarber1(a)ualberta.ca> Found-by: Coverity CID 135745{6,7}, 138029{2-6} Change-Id: I664dcdbaa6b1b8a3aeb9a0126d622e2ffb736efd --- M src/arch/x86/acpi_device.c 1 file changed, 18 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/32971/1 diff --git a/src/arch/x86/acpi_device.c b/src/arch/x86/acpi_device.c index 5d8777f..89708d5 100644 --- a/src/arch/x86/acpi_device.c +++ b/src/arch/x86/acpi_device.c @@ -740,6 +740,9 @@ const struct acpi_dp *prop; size_t i, properties_added = 0; + if (!dp) + return 0; + for (i = 0; i < property_count; i++) { prop = &property_list[i]; @@ -775,6 +778,9 @@ struct acpi_dp *acpi_dp_add_integer(struct acpi_dp *dp, const char *name, uint64_t value) { + if (!dp) + return NULL; + struct acpi_dp *new = acpi_dp_new(dp, ACPI_DP_TYPE_INTEGER, name); if (new) @@ -786,6 +792,9 @@ struct acpi_dp *acpi_dp_add_string(struct acpi_dp *dp, const char *name, const char *string) { + if (!dp) + return NULL; + struct acpi_dp *new = acpi_dp_new(dp, ACPI_DP_TYPE_STRING, name); if (new) @@ -797,6 +806,9 @@ struct acpi_dp *acpi_dp_add_reference(struct acpi_dp *dp, const char *name, const char *reference) { + if (!dp) + return NULL; + struct acpi_dp *new = acpi_dp_new(dp, ACPI_DP_TYPE_REFERENCE, name); if (new) @@ -810,7 +822,7 @@ { struct acpi_dp *new; - if (!child || child->type != ACPI_DP_TYPE_TABLE) + if (!dp || !child || child->type != ACPI_DP_TYPE_TABLE) return NULL; new = acpi_dp_new(dp, ACPI_DP_TYPE_CHILD, name); @@ -826,7 +838,7 @@ { struct acpi_dp *new; - if (!array || array->type != ACPI_DP_TYPE_TABLE) + if (!dp || !array || array->type != ACPI_DP_TYPE_TABLE) return NULL; new = acpi_dp_new(dp, ACPI_DP_TYPE_ARRAY, array->name); @@ -842,7 +854,7 @@ struct acpi_dp *dp_array; int i; - if (len <= 0) + if (!dp || len <= 0) return NULL; dp_array = acpi_dp_new_table(name); @@ -862,6 +874,9 @@ const char *ref, int index, int pin, int active_low) { + if (!dp) + return NULL; + struct acpi_dp *gpio = acpi_dp_new_table(name); if (!gpio) -- To view, visit https://review.coreboot.org/c/coreboot/+/32971 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I664dcdbaa6b1b8a3aeb9a0126d622e2ffb736efd Gerrit-Change-Number: 32971 Gerrit-PatchSet: 1 Gerrit-Owner: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-MessageType: newchange

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coreboot-gerrit May 2019