coreboot-gerrit May 2019

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Change in ...coreboot[master]: src/drivers/xgi: Move coreboot related includes to xgi_coreboot.h
by Patrick Georgi (Code Review) 29 May '19

29 May '19

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/29307 ) Change subject: src/drivers/xgi: Move coreboot related includes to xgi_coreboot.h ...................................................................... src/drivers/xgi: Move coreboot related includes to xgi_coreboot.h Change-Id: Ia18c77876121594a272a07d56acfaa863d0ccb25 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29307 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/drivers/xgi/common/vb_init.c M src/drivers/xgi/common/vb_setmode.c M src/drivers/xgi/common/vb_util.c M src/drivers/xgi/common/xgi_coreboot.h 4 files changed, 5 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Kyösti Mälkki: Looks good to me, approved Angel Pons: Looks good to me, but someone else must approve diff --git a/src/drivers/xgi/common/vb_init.c b/src/drivers/xgi/common/vb_init.c index a20c068..b9191ab 100644 --- a/src/drivers/xgi/common/vb_init.c +++ b/src/drivers/xgi/common/vb_init.c @@ -17,7 +17,7 @@ * GNU General Public License for more details. */ -#include <delay.h> +/* coreboot related includes come indirectly from xgi_coreboot.h */ #include "xgi_coreboot.h" #include "vstruct.h" diff --git a/src/drivers/xgi/common/vb_setmode.c b/src/drivers/xgi/common/vb_setmode.c index 162d00c..6441256 100644 --- a/src/drivers/xgi/common/vb_setmode.c +++ b/src/drivers/xgi/common/vb_setmode.c @@ -14,7 +14,7 @@ * GNU General Public License for more details. */ -#include <delay.h> +/* coreboot related includes come indirectly from xgi_coreboot.h */ #include "xgi_coreboot.h" #include "vstruct.h" diff --git a/src/drivers/xgi/common/vb_util.c b/src/drivers/xgi/common/vb_util.c index f71ad56..248b8af 100644 --- a/src/drivers/xgi/common/vb_util.c +++ b/src/drivers/xgi/common/vb_util.c @@ -14,8 +14,9 @@ * GNU General Public License for more details. */ -#include "xgi_coreboot.h" +/* coreboot related includes come indirectly from xgi_coreboot.h */ +#include "xgi_coreboot.h" #include "vgatypes.h" #include "vb_util.h" diff --git a/src/drivers/xgi/common/xgi_coreboot.h b/src/drivers/xgi/common/xgi_coreboot.h index 41952d6..5e593eb 100644 --- a/src/drivers/xgi/common/xgi_coreboot.h +++ b/src/drivers/xgi/common/xgi_coreboot.h @@ -22,6 +22,7 @@ #include <stdlib.h> #include <stdint.h> #include <arch/io.h> +#include <delay.h> #include <device/mmio.h> #include <console/console.h> #include <device/device.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/29307 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia18c77876121594a272a07d56acfaa863d0ccb25 Gerrit-Change-Number: 29307 Gerrit-PatchSet: 24 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-MessageType: merged

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Change in ...coreboot[master]: commonlib: fix typo LB_TAB_* (instead of LB_TAG_*)
by Patrick Georgi (Code Review) 29 May '19

29 May '19

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32956 Change subject: commonlib: fix typo LB_TAB_* (instead of LB_TAG_*) ...................................................................... commonlib: fix typo LB_TAB_* (instead of LB_TAG_*) Also adapt all users of these symbols Change-Id: Ibf924a283d438de49a93ce661b0d9ca1a81cd6d1 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M src/commonlib/include/commonlib/coreboot_tables.h M src/lib/coreboot_table.c M src/mainboard/google/daisy/mainboard.c M src/mainboard/google/gale/mainboard.c M src/mainboard/google/nyan/mainboard.c M src/mainboard/google/nyan_big/mainboard.c M src/mainboard/google/nyan_blaze/mainboard.c M src/mainboard/google/peach_pit/mainboard.c M src/mainboard/google/storm/mainboard.c M src/mainboard/google/urara/mainboard.c M src/mainboard/google/veyron/mainboard.c M src/mainboard/google/veyron_mickey/mainboard.c M src/mainboard/google/veyron_rialto/mainboard.c 13 files changed, 16 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/32956/1 diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h index 0873dcc..277b746 100644 --- a/src/commonlib/include/commonlib/coreboot_tables.h +++ b/src/commonlib/include/commonlib/coreboot_tables.h @@ -291,9 +291,9 @@ }; #define LB_TAG_VBNV 0x0019 -#define LB_TAB_VBOOT_HANDOFF 0x0020 -#define LB_TAB_VBOOT_WORKBUF 0x0034 -#define LB_TAB_DMA 0x0022 +#define LB_TAG_VBOOT_HANDOFF 0x0020 +#define LB_TAG_VBOOT_WORKBUF 0x0034 +#define LB_TAG_DMA 0x0022 #define LB_TAG_RAM_OOPS 0x0023 #define LB_TAG_MTC 0x002b struct lb_range { diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index 14cd030..df75698 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -219,7 +219,7 @@ return; vbho = (struct lb_range *)lb_new_record(header); - vbho->tag = LB_TAB_VBOOT_HANDOFF; + vbho->tag = LB_TAG_VBOOT_HANDOFF; vbho->size = sizeof(*vbho); vbho->range_start = (intptr_t)addr; vbho->range_size = size; @@ -231,7 +231,7 @@ struct vboot_working_data *wd = vboot_get_working_data(); vbwb = (struct lb_range *)lb_new_record(header); - vbwb->tag = LB_TAB_VBOOT_WORKBUF; + vbwb->tag = LB_TAG_VBOOT_WORKBUF; vbwb->size = sizeof(*vbwb); vbwb->range_start = (uintptr_t)wd + wd->buffer_offset; vbwb->range_size = wd->buffer_size; diff --git a/src/mainboard/google/daisy/mainboard.c b/src/mainboard/google/daisy/mainboard.c index e812189..46939b7 100644 --- a/src/mainboard/google/daisy/mainboard.c +++ b/src/mainboard/google/daisy/mainboard.c @@ -350,7 +350,7 @@ struct lb_range *dma; dma = (struct lb_range *)lb_new_record(header); - dma->tag = LB_TAB_DMA; + dma->tag = LB_TAG_DMA; dma->size = sizeof(*dma); dma->range_start = (uintptr_t)_dma_coherent; dma->range_size = REGION_SIZE(dma_coherent); diff --git a/src/mainboard/google/gale/mainboard.c b/src/mainboard/google/gale/mainboard.c index c8ab88a..8025374 100644 --- a/src/mainboard/google/gale/mainboard.c +++ b/src/mainboard/google/gale/mainboard.c @@ -74,7 +74,7 @@ struct lb_range *dma; dma = (struct lb_range *)lb_new_record(header); - dma->tag = LB_TAB_DMA; + dma->tag = LB_TAG_DMA; dma->size = sizeof(*dma); dma->range_start = (uintptr_t)_dma_coherent; dma->range_size = REGION_SIZE(dma_coherent); diff --git a/src/mainboard/google/nyan/mainboard.c b/src/mainboard/google/nyan/mainboard.c index b1cf19e..807cec3 100644 --- a/src/mainboard/google/nyan/mainboard.c +++ b/src/mainboard/google/nyan/mainboard.c @@ -259,7 +259,7 @@ struct lb_range *dma; dma = (struct lb_range *)lb_new_record(header); - dma->tag = LB_TAB_DMA; + dma->tag = LB_TAG_DMA; dma->size = sizeof(*dma); dma->range_start = (uintptr_t)_dma_coherent; dma->range_size = REGION_SIZE(dma_coherent); diff --git a/src/mainboard/google/nyan_big/mainboard.c b/src/mainboard/google/nyan_big/mainboard.c index c0769f1..c8bb813 100644 --- a/src/mainboard/google/nyan_big/mainboard.c +++ b/src/mainboard/google/nyan_big/mainboard.c @@ -257,7 +257,7 @@ struct lb_range *dma; dma = (struct lb_range *)lb_new_record(header); - dma->tag = LB_TAB_DMA; + dma->tag = LB_TAG_DMA; dma->size = sizeof(*dma); dma->range_start = (uintptr_t)_dma_coherent; dma->range_size = REGION_SIZE(dma_coherent); diff --git a/src/mainboard/google/nyan_blaze/mainboard.c b/src/mainboard/google/nyan_blaze/mainboard.c index a296092..97d0576 100644 --- a/src/mainboard/google/nyan_blaze/mainboard.c +++ b/src/mainboard/google/nyan_blaze/mainboard.c @@ -257,7 +257,7 @@ struct lb_range *dma; dma = (struct lb_range *)lb_new_record(header); - dma->tag = LB_TAB_DMA; + dma->tag = LB_TAG_DMA; dma->size = sizeof(*dma); dma->range_start = (uintptr_t)_dma_coherent; dma->range_size = REGION_SIZE(dma_coherent); diff --git a/src/mainboard/google/peach_pit/mainboard.c b/src/mainboard/google/peach_pit/mainboard.c index 0441e52..ecd2260 100644 --- a/src/mainboard/google/peach_pit/mainboard.c +++ b/src/mainboard/google/peach_pit/mainboard.c @@ -485,7 +485,7 @@ struct lb_range *dma; dma = (struct lb_range *)lb_new_record(header); - dma->tag = LB_TAB_DMA; + dma->tag = LB_TAG_DMA; dma->size = sizeof(*dma); dma->range_start = (uintptr_t)_dma_coherent; dma->range_size = REGION_SIZE(dma_coherent); diff --git a/src/mainboard/google/storm/mainboard.c b/src/mainboard/google/storm/mainboard.c index fdff5ab..783e6ad 100644 --- a/src/mainboard/google/storm/mainboard.c +++ b/src/mainboard/google/storm/mainboard.c @@ -119,7 +119,7 @@ struct lb_range *dma; dma = (struct lb_range *)lb_new_record(header); - dma->tag = LB_TAB_DMA; + dma->tag = LB_TAG_DMA; dma->size = sizeof(*dma); dma->range_start = (uintptr_t)_dma_coherent; dma->range_size = REGION_SIZE(dma_coherent); diff --git a/src/mainboard/google/urara/mainboard.c b/src/mainboard/google/urara/mainboard.c index 3eaad34..7bf8b90 100644 --- a/src/mainboard/google/urara/mainboard.c +++ b/src/mainboard/google/urara/mainboard.c @@ -43,7 +43,7 @@ struct lb_range *dma; dma = (struct lb_range *)lb_new_record(header); - dma->tag = LB_TAB_DMA; + dma->tag = LB_TAG_DMA; dma->size = sizeof(*dma); dma->range_start = (uintptr_t)_dma_coherent; dma->range_size = REGION_SIZE(dma_coherent); diff --git a/src/mainboard/google/veyron/mainboard.c b/src/mainboard/google/veyron/mainboard.c index d8ac310..5243dc9 100644 --- a/src/mainboard/google/veyron/mainboard.c +++ b/src/mainboard/google/veyron/mainboard.c @@ -123,7 +123,7 @@ struct lb_range *dma; dma = (struct lb_range *)lb_new_record(header); - dma->tag = LB_TAB_DMA; + dma->tag = LB_TAG_DMA; dma->size = sizeof(*dma); dma->range_start = (uintptr_t)_dma_coherent; dma->range_size = REGION_SIZE(dma_coherent); diff --git a/src/mainboard/google/veyron_mickey/mainboard.c b/src/mainboard/google/veyron_mickey/mainboard.c index bb23973..9024b6c 100644 --- a/src/mainboard/google/veyron_mickey/mainboard.c +++ b/src/mainboard/google/veyron_mickey/mainboard.c @@ -101,7 +101,7 @@ struct lb_range *dma; dma = (struct lb_range *)lb_new_record(header); - dma->tag = LB_TAB_DMA; + dma->tag = LB_TAG_DMA; dma->size = sizeof(*dma); dma->range_start = (uintptr_t)_dma_coherent; dma->range_size = REGION_SIZE(dma_coherent); diff --git a/src/mainboard/google/veyron_rialto/mainboard.c b/src/mainboard/google/veyron_rialto/mainboard.c index 074e6a4..6259955 100644 --- a/src/mainboard/google/veyron_rialto/mainboard.c +++ b/src/mainboard/google/veyron_rialto/mainboard.c @@ -107,7 +107,7 @@ struct lb_range *dma; dma = (struct lb_range *)lb_new_record(header); - dma->tag = LB_TAB_DMA; + dma->tag = LB_TAG_DMA; dma->size = sizeof(*dma); dma->range_start = (uintptr_t)_dma_coherent; dma->range_size = REGION_SIZE(dma_coherent); -- To view, visit https://review.coreboot.org/c/coreboot/+/32956 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibf924a283d438de49a93ce661b0d9ca1a81cd6d1 Gerrit-Change-Number: 32956 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: commonlib: renumber CB_TAG_TCPA_LOG
by Patrick Georgi (Code Review) 29 May '19

29 May '19

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32955 Change subject: commonlib: renumber CB_TAG_TCPA_LOG ...................................................................... commonlib: renumber CB_TAG_TCPA_LOG It conflicts with VBOOT_WORKBUF but unlike VBOOT_WORKBUF no user can be identified in the coreboot tree for TCPA_LOG, so renumber this. Change-Id: Ib8a850c0ccbcacdf7d288316b54eb82fce874a82 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M src/commonlib/include/commonlib/coreboot_tables.h 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/32955/1 diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h index bbc8608..0873dcc 100644 --- a/src/commonlib/include/commonlib/coreboot_tables.h +++ b/src/commonlib/include/commonlib/coreboot_tables.h @@ -310,7 +310,7 @@ #define LB_TAG_CBMEM_CONSOLE 0x0017 #define LB_TAG_MRC_CACHE 0x0018 #define LB_TAG_ACPI_GNVS 0x0024 -#define LB_TAG_TCPA_LOG 0x0034 +#define LB_TAG_TCPA_LOG 0x0036 #define LB_TAG_WIFI_CALIBRATION 0x0027 #define LB_TAG_VPD 0x002c struct lb_cbmem_ref { -- To view, visit https://review.coreboot.org/c/coreboot/+/32955 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib8a850c0ccbcacdf7d288316b54eb82fce874a82 Gerrit-Change-Number: 32955 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: cpu/x86/mtrr: Assert that MSR arrays are fully initialized
by Jacob Garber (Code Review) 29 May '19

29 May '19

Jacob Garber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33048 Change subject: cpu/x86/mtrr: Assert that MSR arrays are fully initialized ...................................................................... cpu/x86/mtrr: Assert that MSR arrays are fully initialized The initialization logic for the fixed_msrs and msr_index arrays depends on the contents of the fixed MTRR descriptor. However, Coverity is unable to check these values and believes (incorrectly) that the arrays may not be entirely initialized. An assert was added in commit b28025a434 to ensure that one of the loops is entered, but it is simplest to just check that msr_num has iterated over the entire array after the loops are over. This also acts as a sanity check that the values in the MTRR descriptor were hardcoded correctly. Change-Id: Ia573792f74aa6ea5e659c1e2253f112184fbb0a5 Signed-off-by: Jacob Garber <jgarber1(a)ualberta.ca> Found-by: Coverity CID 1370582 --- M src/cpu/x86/mtrr/mtrr.c 1 file changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/33048/1 diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index d87c3d4..60eee31 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -331,7 +331,6 @@ desc = &fixed_mtrr_desc[i]; num_ranges = (desc->end - desc->begin) / desc->step; - ASSERT(num_ranges > 0); for (j = 0; j < num_ranges; j += RANGES_PER_FIXED_MTRR) { msr_index[msr_num] = desc->msr_index_base + (j / RANGES_PER_FIXED_MTRR); @@ -355,6 +354,9 @@ } } + /* Ensure that both arrays were fully initialized */ + ASSERT(msr_num == NUM_FIXED_MTRRS) + for (i = 0; i < ARRAY_SIZE(fixed_msrs); i++) printk(BIOS_DEBUG, "MTRR: Fixed MSR 0x%lx 0x%08x%08x\n", msr_index[i], fixed_msrs[i].hi, fixed_msrs[i].lo); -- To view, visit https://review.coreboot.org/c/coreboot/+/33048 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia573792f74aa6ea5e659c1e2253f112184fbb0a5 Gerrit-Change-Number: 33048 Gerrit-PatchSet: 1 Gerrit-Owner: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: drivers/generic/max98357a: Add extra error handling
by Jacob Garber (Code Review) 29 May '19

29 May '19

Jacob Garber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33028 Change subject: drivers/generic/max98357a: Add extra error handling ...................................................................... drivers/generic/max98357a: Add extra error handling It is possible that acpi_device_scope() and acpi_device_name() can return NULL to indicate an error, so add error handling to check their return values. Change-Id: I4c7ab0c592845d9d5f142e078fc2b505a99ecd12 Signed-off-by: Jacob Garber <jgarber1(a)ualberta.ca> Found-by: Coverity CID 1362592 --- M src/drivers/generic/max98357a/max98357a.c 1 file changed, 7 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/33028/1 diff --git a/src/drivers/generic/max98357a/max98357a.c b/src/drivers/generic/max98357a/max98357a.c index 1408dac..838491d 100644 --- a/src/drivers/generic/max98357a/max98357a.c +++ b/src/drivers/generic/max98357a/max98357a.c @@ -36,9 +36,14 @@ if (!dev->enabled || !config) return; + const char *scope = acpi_device_scope(dev); + const char *name = acpi_device_name(dev); + if (!scope || !name) + return; + /* Device */ - acpigen_write_scope(acpi_device_scope(dev)); - acpigen_write_device(acpi_device_name(dev)); + acpigen_write_scope(scope); + acpigen_write_device(name); acpigen_write_name_string("_HID", MAX98357A_ACPI_HID); acpigen_write_name_integer("_UID", 0); acpigen_write_name_string("_DDN", dev->chip_ops->name); -- To view, visit https://review.coreboot.org/c/coreboot/+/33028 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4c7ab0c592845d9d5f142e078fc2b505a99ecd12 Gerrit-Change-Number: 33028 Gerrit-PatchSet: 1 Gerrit-Owner: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: google/clapper: fix up devicetree
by Matt DeVillier (Code Review) 29 May '19

29 May '19

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33025 Change subject: google/clapper: fix up devicetree ...................................................................... google/clapper: fix up devicetree When clapper was upstreamed, the devicetree was pulled from the wrong firmware branch, leading to some incorrect settings and touchpad, touchscreen, and audio not working. Correct devicetree settings using Chromium branch firmware-clapper-5216.199.B Test: build/boot google/clapper, verify touchpad/touchscreen/audio functional under Linux (GalliumOS 3.0/kernel 4.16.18). Change-Id: Iacfce575a054b1f484149f36d0aa83d20d034d8a Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/rambi/variants/clapper/devicetree.cb 1 file changed, 14 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/33025/1 diff --git a/src/mainboard/google/rambi/variants/clapper/devicetree.cb b/src/mainboard/google/rambi/variants/clapper/devicetree.cb index 1e50e53..c010af1 100644 --- a/src/mainboard/google/rambi/variants/clapper/devicetree.cb +++ b/src/mainboard/google/rambi/variants/clapper/devicetree.cb @@ -32,16 +32,25 @@ register "sdcard_cap_high" = "0x0" # Enable devices in ACPI mode + register "lpe_acpi_mode" = "1" + register "lpss_acpi_mode" = "1" register "scc_acpi_mode" = "1" # Enable PIPEA as DP_C register "gpu_pipea_port_select" = "2" # DP_C - register "gpu_pipea_power_cycle_delay" = "5" # 400ms - register "gpu_pipea_power_on_delay" = "2000" # 200ms - register "gpu_pipea_light_on_delay" = "10" # 1ms + register "gpu_pipea_power_cycle_delay" = "6" # 600ms + register "gpu_pipea_power_on_delay" = "5000" # 500ms + register "gpu_pipea_light_on_delay" = "70" # 7ms register "gpu_pipea_power_off_delay" = "500" # 50ms register "gpu_pipea_light_off_delay" = "2000" # 200ms + # VR PS2 control + register "vnn_ps2_enable" = "1" + register "vcc_ps2_enable" = "1" + + # Disable SLP_X stretching after SUS power well fail. + register "disable_slp_x_stretch_sus_fail" = "1" + device cpu_cluster 0 on device lapic 0 on end end @@ -59,11 +68,11 @@ device pci 18.2 on end # I2C2 device pci 18.3 off end # I2C3 device pci 18.4 off end # I2C4 - device pci 18.5 off end # I2C5 + device pci 18.5 on end # I2C5 device pci 18.6 on end # I2C6 device pci 18.7 off end # I2C7 device pci 1a.0 off end # TXE - device pci 1b.0 off end # HDA + device pci 1b.0 on end # HDA device pci 1c.0 on end # PCIE_PORT1 device pci 1c.1 on end # PCIE_PORT2 device pci 1c.2 off end # PCIE_PORT3 -- To view, visit https://review.coreboot.org/c/coreboot/+/33025 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iacfce575a054b1f484149f36d0aa83d20d034d8a Gerrit-Change-Number: 33025 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/{misc}: set default SMBIOS manufacturer
by Matt DeVillier (Code Review) 29 May '19

29 May '19

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33027 Change subject: mb/google/{misc}: set default SMBIOS manufacturer ...................................................................... mb/google/{misc}: set default SMBIOS manufacturer Legacy Google mainboards (pre-Skylake) shipped with the SMBIOS manufacturer set to GOOGLE, which many Linux drivers rely on for application of DMI quirks. Set it as the default to avoid having to do so for each board's config Change-Id: I61b0217f3535852d7d6e24a1ac78075c20c0825a Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/auron/Kconfig M src/mainboard/google/beltino/Kconfig M src/mainboard/google/butterfly/Kconfig M src/mainboard/google/cyan/Kconfig M src/mainboard/google/jecht/Kconfig M src/mainboard/google/link/Kconfig M src/mainboard/google/parrot/Kconfig M src/mainboard/google/rambi/Kconfig M src/mainboard/google/slippy/Kconfig M src/mainboard/google/stout/Kconfig 10 files changed, 40 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/33027/1 diff --git a/src/mainboard/google/auron/Kconfig b/src/mainboard/google/auron/Kconfig index 3f350e8..69b086f 100644 --- a/src/mainboard/google/auron/Kconfig +++ b/src/mainboard/google/auron/Kconfig @@ -72,4 +72,8 @@ string default "pci8086,0406.rom" +config MAINBOARD_SMBIOS_MANUFACTURER + string + default "GOOGLE" + endif diff --git a/src/mainboard/google/beltino/Kconfig b/src/mainboard/google/beltino/Kconfig index 872d49d..df5da9d 100644 --- a/src/mainboard/google/beltino/Kconfig +++ b/src/mainboard/google/beltino/Kconfig @@ -59,4 +59,8 @@ string default "pci8086,0406.rom" +config MAINBOARD_SMBIOS_MANUFACTURER + string + default "GOOGLE" + endif # BOARD_GOOGLE_BASEBOARD_BELTINO diff --git a/src/mainboard/google/butterfly/Kconfig b/src/mainboard/google/butterfly/Kconfig index 24797be..76bcc3d 100644 --- a/src/mainboard/google/butterfly/Kconfig +++ b/src/mainboard/google/butterfly/Kconfig @@ -44,4 +44,8 @@ string default "Hewlett-Packard" +config MAINBOARD_SMBIOS_MANUFACTURER + string + default "GOOGLE" + endif # BOARD_GOOGLE_BUTTERFLY diff --git a/src/mainboard/google/cyan/Kconfig b/src/mainboard/google/cyan/Kconfig index aac14c0..bf0cd09 100644 --- a/src/mainboard/google/cyan/Kconfig +++ b/src/mainboard/google/cyan/Kconfig @@ -112,4 +112,8 @@ hex default 0x200000 +config MAINBOARD_SMBIOS_MANUFACTURER + string + default "GOOGLE" + endif # BOARD_GOOGLE_BASEBOARD_CYAN diff --git a/src/mainboard/google/jecht/Kconfig b/src/mainboard/google/jecht/Kconfig index 15ed05b..5ffc1bc 100644 --- a/src/mainboard/google/jecht/Kconfig +++ b/src/mainboard/google/jecht/Kconfig @@ -53,4 +53,8 @@ string default "pci8086,0406.rom" +config MAINBOARD_SMBIOS_MANUFACTURER + string + default "GOOGLE" + endif diff --git a/src/mainboard/google/link/Kconfig b/src/mainboard/google/link/Kconfig index 612a1b5..3628f1d 100644 --- a/src/mainboard/google/link/Kconfig +++ b/src/mainboard/google/link/Kconfig @@ -45,4 +45,9 @@ string depends on CHROMEOS default "X86 LINK TEST 6638" + +config MAINBOARD_SMBIOS_MANUFACTURER + string + default "GOOGLE" + endif # BOARD_GOOGLE_LINK diff --git a/src/mainboard/google/parrot/Kconfig b/src/mainboard/google/parrot/Kconfig index 4403d79..daf605d 100644 --- a/src/mainboard/google/parrot/Kconfig +++ b/src/mainboard/google/parrot/Kconfig @@ -41,4 +41,8 @@ string default "pci8086,0106.rom" +config MAINBOARD_SMBIOS_MANUFACTURER + string + default "GOOGLE" + endif # BOARD_GOOGLE_PARROT diff --git a/src/mainboard/google/rambi/Kconfig b/src/mainboard/google/rambi/Kconfig index 6d0c0df..c47b3d7 100644 --- a/src/mainboard/google/rambi/Kconfig +++ b/src/mainboard/google/rambi/Kconfig @@ -94,4 +94,8 @@ string default "pci8086,0f31.rom" +config MAINBOARD_SMBIOS_MANUFACTURER + string + default "GOOGLE" + endif # BOARD_GOOGLE_BASEBOARD_RAMBI diff --git a/src/mainboard/google/slippy/Kconfig b/src/mainboard/google/slippy/Kconfig index ecc8aff..242876d 100644 --- a/src/mainboard/google/slippy/Kconfig +++ b/src/mainboard/google/slippy/Kconfig @@ -71,5 +71,8 @@ config INTEL_GMA_VBT_FILE default "src/mainboard/$(MAINBOARDDIR)/data.vbt" +config MAINBOARD_SMBIOS_MANUFACTURER + string + default "GOOGLE" endif # BOARD_GOOGLE_BASEBOARD_SLIPPY diff --git a/src/mainboard/google/stout/Kconfig b/src/mainboard/google/stout/Kconfig index 7096d93..dfe687b 100644 --- a/src/mainboard/google/stout/Kconfig +++ b/src/mainboard/google/stout/Kconfig @@ -43,4 +43,8 @@ string default "8086,0156" +config MAINBOARD_SMBIOS_MANUFACTURER + string + default "GOOGLE" + endif # BOARD_GOOGLE_STOUT -- To view, visit https://review.coreboot.org/c/coreboot/+/33027 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I61b0217f3535852d7d6e24a1ac78075c20c0825a Gerrit-Change-Number: 33027 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

3 3

Change in ...coreboot[master]: Makefile.inc: Extend version string for timeless builds
by Nico Huber (Code Review) 29 May '19

29 May '19

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32986 Change subject: Makefile.inc: Extend version string for timeless builds ...................................................................... Makefile.inc: Extend version string for timeless builds With the version string "TIMELESS", binaries are slightly smaller than for a regular build. This may lead to false positive build tests if the space is limited (e.g. bootblock). So let's make the string a little longer. Change-Id: I3bbf6f71d5bcd74728a3fe39734312690901d0ec Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M Makefile.inc 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/32986/1 diff --git a/Makefile.inc b/Makefile.inc index 9860da1..d4f7597 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -31,7 +31,7 @@ # misleadingly named, this is the coreboot version ifeq ($(KERNELVERSION),) ifeq ($(BUILD_TIMELESS),1) -KERNELVERSION := TIMELESS +KERNELVERSION := -TIMELESS--LESSTIME- else KERNELVERSION := $(strip $(if $(GIT),\ $(shell git describe --dirty --always || git describe),\ -- To view, visit https://review.coreboot.org/c/coreboot/+/32986 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3bbf6f71d5bcd74728a3fe39734312690901d0ec Gerrit-Change-Number: 32986 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

4 4

Change in ...coreboot[master]: soc/intel/apollolake: Fix issue found by Coverity
by John Zhao (Code Review) 29 May '19

29 May '19

John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32903 Change subject: soc/intel/apollolake: Fix issue found by Coverity ...................................................................... soc/intel/apollolake: Fix issue found by Coverity Function soc_init: Value stored to 'gnvs' is never read. ACPI NVS in CBMEM allocation has been implemented in commom/acpi. Remove the redundant cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnve)). BRANCH=None TEST=Built image successfully. Signed-off-by: John Zhao <john.zhao(a)intel.com> Change-Id: Ie9421af4a556d1d88183aa938ee2a124a10ab727 --- M src/soc/intel/apollolake/chip.c 1 file changed, 0 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/32903/1 diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index f6880a7..ffe3ed1 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -44,7 +44,6 @@ #include <soc/intel/common/vbt.h> #include <soc/iomap.h> #include <soc/itss.h> -#include <soc/nvs.h> #include <soc/pci_devs.h> #include <soc/pm.h> #include <soc/systemagent.h> @@ -389,8 +388,6 @@ static void soc_init(void *data) { - struct global_nvs_t *gnvs; - /* Snapshot the current GPIO IRQ polarities. FSP is setting a * default policy that doesn't honor boards' requirements. */ itss_snapshot_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END); @@ -417,9 +414,6 @@ */ p2sb_unhide(); - /* Allocate ACPI NVS in CBMEM */ - gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); - /* Set RAPL MSR for Package power limits*/ set_power_limits(); -- To view, visit https://review.coreboot.org/c/coreboot/+/32903 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie9421af4a556d1d88183aa938ee2a124a10ab727 Gerrit-Change-Number: 32903 Gerrit-PatchSet: 1 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-MessageType: newchange

9 32

Change in ...coreboot[master]: sb/intel/*: Delete early_spi
by Patrick Rudolph (Code Review) 29 May '19

29 May '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32688 Change subject: sb/intel/*: Delete early_spi ...................................................................... sb/intel/*: Delete early_spi The file and all of it's functions are unused. Drop the dead code. Change-Id: Iaddd7a688d431d40f38293939e084d19b286aed4 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/intel/baytrail/include/soc/romstage.h M src/soc/intel/baytrail/romstage/Makefile.inc D src/soc/intel/baytrail/romstage/early_spi.c M src/soc/intel/braswell/include/soc/romstage.h M src/soc/intel/braswell/romstage/Makefile.inc D src/soc/intel/braswell/romstage/early_spi.c M src/soc/intel/broadwell/include/soc/romstage.h D src/soc/intel/broadwell/romstage/spi.c M src/southbridge/intel/bd82x6x/Makefile.inc D src/southbridge/intel/bd82x6x/early_spi.c M src/southbridge/intel/bd82x6x/pch.h M src/southbridge/intel/fsp_rangeley/Makefile.inc D src/southbridge/intel/fsp_rangeley/early_spi.c M src/southbridge/intel/fsp_rangeley/soc.h M src/southbridge/intel/ibexpeak/Makefile.inc M src/southbridge/intel/ibexpeak/pch.h M src/southbridge/intel/lynxpoint/Makefile.inc D src/southbridge/intel/lynxpoint/early_spi.c M src/southbridge/intel/lynxpoint/pch.h 19 files changed, 2 insertions(+), 606 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/32688/1 diff --git a/src/soc/intel/baytrail/include/soc/romstage.h b/src/soc/intel/baytrail/include/soc/romstage.h index 3e8b6a2..fffce7e 100644 --- a/src/soc/intel/baytrail/include/soc/romstage.h +++ b/src/soc/intel/baytrail/include/soc/romstage.h @@ -37,7 +37,6 @@ void tco_disable(void); void punit_init(void); void set_max_freq(void); -int early_spi_read_wpsr(u8 *sr); #if CONFIG(ENABLE_BUILTIN_COM1) void byt_config_com1_and_enable(void); diff --git a/src/soc/intel/baytrail/romstage/Makefile.inc b/src/soc/intel/baytrail/romstage/Makefile.inc index f1a3463..d43a6fb 100644 --- a/src/soc/intel/baytrail/romstage/Makefile.inc +++ b/src/soc/intel/baytrail/romstage/Makefile.inc @@ -5,4 +5,3 @@ romstage-$(CONFIG_ENABLE_BUILTIN_COM1) += uart.c romstage-y += gfx.c romstage-y += pmc.c -romstage-y += early_spi.c diff --git a/src/soc/intel/baytrail/romstage/early_spi.c b/src/soc/intel/baytrail/romstage/early_spi.c deleted file mode 100644 index 72e9b2c..0000000 --- a/src/soc/intel/baytrail/romstage/early_spi.c +++ /dev/null @@ -1,60 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. All rights reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <delay.h> -#include <console/console.h> - -#include <soc/iomap.h> -#include <soc/romstage.h> -#include <soc/spi.h> - -#define SPI_CYCLE_DELAY 10 /* 10us */ -#define SPI_CYCLE_TIMEOUT 400000 / SPI_CYCLE_DELAY /* 400ms */ - -#define SPI8(x) *((volatile u8 *)(SPI_BASE_ADDRESS + x)) -#define SPI16(x) *((volatile u16 *)(SPI_BASE_ADDRESS + x)) -#define SPI32(x) *((volatile u32 *)(SPI_BASE_ADDRESS + x)) - -/* Minimal set of commands to read wpsr from SPI. Don't use this code outside - * romstage -- it trashes the opmenu table. - * Returns 0 on success, < 0 on failure. */ -int early_spi_read_wpsr(u8 *sr) -{ - int timeout = SPI_CYCLE_TIMEOUT; - - /* No address associated with rdsr */ - SPI8(OPTYPE) = 0x0; - /* Setup opcode[0] = read wpsr */ - SPI8(OPMENU0) = 0x5; - - /* Start transaction */ - SPI16(SSFC) = DATA_CYCLE | SPI_CYCLE_GO; - - /* Wait for error / complete status */ - while (timeout--) { - u16 status = SPI16(SSFS); - if (status & FLASH_CYCLE_ERROR) { - printk(BIOS_ERR, "SPI rdsr failed\n"); - return -1; - } else if (status & CYCLE_DONE_STATUS) - break; - - udelay(SPI_CYCLE_DELAY); - } - - *sr = SPI32(FDATA0) & 0xff; - return 0; -} diff --git a/src/soc/intel/braswell/include/soc/romstage.h b/src/soc/intel/braswell/include/soc/romstage.h index 633233e..4ecbd2c 100644 --- a/src/soc/intel/braswell/include/soc/romstage.h +++ b/src/soc/intel/braswell/include/soc/romstage.h @@ -25,7 +25,6 @@ void gfx_init(void); void tco_disable(void); void punit_init(void); -int early_spi_read_wpsr(u8 *sr); void set_max_freq(void); /* romstage_common.c functions */ diff --git a/src/soc/intel/braswell/romstage/Makefile.inc b/src/soc/intel/braswell/romstage/Makefile.inc index c3ed415..15de822 100644 --- a/src/soc/intel/braswell/romstage/Makefile.inc +++ b/src/soc/intel/braswell/romstage/Makefile.inc @@ -1,3 +1,2 @@ -romstage-y += early_spi.c romstage-y += pmc.c romstage-y += romstage.c diff --git a/src/soc/intel/braswell/romstage/early_spi.c b/src/soc/intel/braswell/romstage/early_spi.c deleted file mode 100644 index 0ca5ef5..0000000 --- a/src/soc/intel/braswell/romstage/early_spi.c +++ /dev/null @@ -1,63 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. All rights reserved. - * Copyright (C) 2015 Intel Corp. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <delay.h> -#include <console/console.h> - -#include <soc/iomap.h> -#include <soc/romstage.h> -#include <soc/spi.h> - -#define SPI_CYCLE_DELAY 10 /* 10us */ -#define SPI_CYCLE_TIMEOUT (400000 / SPI_CYCLE_DELAY) /* 400ms */ - -#define SPI8(x) (*((volatile u8 *)(SPI_BASE_ADDRESS + (x)))) -#define SPI16(x) (*((volatile u16 *)(SPI_BASE_ADDRESS + (x)))) -#define SPI32(x) (*((volatile u32 *)(SPI_BASE_ADDRESS + (x)))) - -/* - * Minimal set of commands to read wpsr from SPI. Don't use this code outside - * romstage -- it trashes the opmenu table. - * Returns 0 on success, < 0 on failure. - */ -int early_spi_read_wpsr(u8 *sr) -{ - int timeout = SPI_CYCLE_TIMEOUT; - - /* No address associated with rdsr */ - SPI8(OPTYPE) = 0x0; - /* Setup opcode[0] = read wpsr */ - SPI8(OPMENU0) = 0x5; - - /* Start transaction */ - SPI16(SSFC) = DATA_CYCLE | SPI_CYCLE_GO; - - /* Wait for error / complete status */ - while (timeout--) { - u16 status = SPI16(SSFS); - if (status & FLASH_CYCLE_ERROR) { - printk(BIOS_ERR, "SPI rdsr failed\n"); - return -1; - } else if (status & CYCLE_DONE_STATUS) - break; - - udelay(SPI_CYCLE_DELAY); - } - - *sr = SPI32(FDATA0) & 0xff; - return 0; -} diff --git a/src/soc/intel/broadwell/include/soc/romstage.h b/src/soc/intel/broadwell/include/soc/romstage.h index 31184f9..a5a2ecb 100644 --- a/src/soc/intel/broadwell/include/soc/romstage.h +++ b/src/soc/intel/broadwell/include/soc/romstage.h @@ -47,8 +47,5 @@ void enable_smbus(void); int smbus_read_byte(unsigned int device, unsigned int address); -int early_spi_read(u32 offset, u32 size, u8 *buffer); -int early_spi_read_wpsr(u8 *sr); - void mainboard_pre_console_init(void); #endif diff --git a/src/soc/intel/broadwell/romstage/spi.c b/src/soc/intel/broadwell/romstage/spi.c deleted file mode 100644 index cb0509d..0000000 --- a/src/soc/intel/broadwell/romstage/spi.c +++ /dev/null @@ -1,143 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <device/pci_def.h> -#include <delay.h> -#include <soc/spi.h> -#include <soc/rcba.h> -#include <soc/romstage.h> - -#define SPI_DELAY 10 /* 10us */ -#define SPI_RETRY 200000 /* 2s */ - -static int early_spi_read_block(u32 offset, u8 size, u8 *buffer) -{ - u32 *ptr32 = (u32 *)buffer; - u32 i; - - /* Clear status bits */ - SPIBAR16(SPIBAR_HSFS) |= SPIBAR_HSFS_AEL | SPIBAR_HSFS_FCERR | - SPIBAR_HSFS_FDONE; - - if (SPIBAR16(SPIBAR_HSFS) & SPIBAR_HSFS_SCIP) { - printk(BIOS_ERR, "SPI ERROR: transaction in progress\n"); - return -1; - } - - /* Set flash address */ - SPIBAR32(SPIBAR_FADDR) = offset; - - /* Setup read transaction */ - SPIBAR16(SPIBAR_HSFC) = SPIBAR_HSFC_BYTE_COUNT(size) | - SPIBAR_HSFC_CYCLE_READ; - - /* Start transaction */ - SPIBAR16(SPIBAR_HSFC) |= SPIBAR_HSFC_GO; - - /* Wait for completion */ - for (i = 0; i < SPI_RETRY; i++) { - if (SPIBAR16(SPIBAR_HSFS) & SPIBAR_HSFS_SCIP) { - /* Cycle in progress, wait 1ms */ - udelay(SPI_DELAY); - continue; - } - - if (SPIBAR16(SPIBAR_HSFS) & SPIBAR_HSFS_AEL) { - printk(BIOS_ERR, "SPI ERROR: Access Error\n"); - return -1; - - } - - if (SPIBAR16(SPIBAR_HSFS) & SPIBAR_HSFS_FCERR) { - printk(BIOS_ERR, "SPI ERROR: Flash Cycle Error\n"); - return -1; - } - break; - } - - if (i >= SPI_RETRY) { - printk(BIOS_ERR, "SPI ERROR: Timeout\n"); - return -1; - } - - /* Read the data */ - for (i = 0; i < size; i += sizeof(u32)) { - if (size-i >= 4) { - /* reading >= dword */ - *ptr32++ = SPIBAR32(SPIBAR_FDATA(i/sizeof(u32))); - } else { - /* reading < dword */ - u8 j, *ptr8 = (u8 *)ptr32; - u32 temp = SPIBAR32(SPIBAR_FDATA(i/sizeof(u32))); - for (j = 0; j < (size-i); j++) { - *ptr8++ = temp & 0xff; - temp >>= 8; - } - } - } - - return size; -} - -int early_spi_read(u32 offset, u32 size, u8 *buffer) -{ - u32 current = 0; - - while (size > 0) { - u8 count = (size < 64) ? size : 64; - if (early_spi_read_block(offset + current, count, - buffer + current) < 0) - return -1; - size -= count; - current += count; - } - - return 0; -} - -/* - * Minimal set of commands to read WPSR from SPI. - * Don't use this code outside romstage -- it trashes the opmenu table. - * Returns 0 on success, < 0 on failure. - */ -int early_spi_read_wpsr(u8 *sr) -{ - int retry; - - /* No address associated with rdsr */ - SPIBAR8(SPIBAR_OPTYPE) = 0x0; - /* Setup opcode[0] = read wpsr */ - SPIBAR8(SPIBAR_OPMENU_LOWER) = 0x5; - - /* Start transaction */ - SPIBAR16(SPIBAR_SSFC) = SPIBAR_SSFC_DATA | SPIBAR_SSFC_GO; - - /* Wait for error / complete status */ - for (retry = SPI_RETRY; retry; retry--) { - u16 status = SPIBAR16(SPIBAR_SSFS); - if (status & SPIBAR_SSFS_ERROR) { - printk(BIOS_ERR, "SPI rdsr failed\n"); - return -1; - } else if (status & SPIBAR_SSFS_DONE) { - break; - } - - udelay(SPI_DELAY); - } - - *sr = SPIBAR32(SPIBAR_FDATA(0)) & 0xff; - return 0; -} diff --git a/src/southbridge/intel/bd82x6x/Makefile.inc b/src/southbridge/intel/bd82x6x/Makefile.inc index 023f5d3..b6023b0 100644 --- a/src/southbridge/intel/bd82x6x/Makefile.inc +++ b/src/southbridge/intel/bd82x6x/Makefile.inc @@ -37,7 +37,6 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c me.c me_8.x.c pch.c romstage-y += early_smbus.c me_status.c -romstage-y += early_spi.c romstage-y += early_rcba.c romstage-y += early_pch.c diff --git a/src/southbridge/intel/bd82x6x/early_spi.c b/src/southbridge/intel/bd82x6x/early_spi.c deleted file mode 100644 index 3034930..0000000 --- a/src/southbridge/intel/bd82x6x/early_spi.c +++ /dev/null @@ -1,108 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Google Inc. All rights reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <device/pci_def.h> -#include <delay.h> -#include "pch.h" - -#define SPI_DELAY 10 /* 10us */ -#define SPI_RETRY 200000 /* 2s */ - -static int early_spi_read_block(u32 offset, u8 size, u8 *buffer) -{ - u32 *ptr32 = (u32*)buffer; - u32 i; - - /* Clear status bits */ - RCBA16(SPIBAR_HSFS) |= SPIBAR_HSFS_AEL | SPIBAR_HSFS_FCERR | - SPIBAR_HSFS_FDONE; - - if (RCBA16(SPIBAR_HSFS) & SPIBAR_HSFS_SCIP) { - printk(BIOS_ERR, "SPI ERROR: transaction in progress\n"); - return -1; - } - - /* Set flash address */ - RCBA32(SPIBAR_FADDR) = offset; - - /* Setup read transaction */ - RCBA16(SPIBAR_HSFC) = SPIBAR_HSFC_BYTE_COUNT(size) | - SPIBAR_HSFC_CYCLE_READ; - - /* Start transactinon */ - RCBA16(SPIBAR_HSFC) |= SPIBAR_HSFC_GO; - - /* Wait for completion */ - for (i = 0; i < SPI_RETRY; i++) { - if (RCBA16(SPIBAR_HSFS) & SPIBAR_HSFS_SCIP) { - /* Cycle in progress, wait 1ms */ - udelay(SPI_DELAY); - continue; - } - - if (RCBA16(SPIBAR_HSFS) & SPIBAR_HSFS_AEL) { - printk(BIOS_ERR, "SPI ERROR: Access Error\n"); - return -1; - - } - - if (RCBA16(SPIBAR_HSFS) & SPIBAR_HSFS_FCERR) { - printk(BIOS_ERR, "SPI ERROR: Flash Cycle Error\n"); - return -1; - } - break; - } - - if (i >= SPI_RETRY) { - printk(BIOS_ERR, "SPI ERROR: Timeout\n"); - return -1; - } - - /* Read the data */ - for (i = 0; i < size; i+=sizeof(u32)) { - if (size-i >= 4) { - /* reading >= dword */ - *ptr32++ = RCBA32(SPIBAR_FDATA(i/sizeof(u32))); - } else { - /* reading < dword */ - u8 j, *ptr8 = (u8*)ptr32; - u32 temp = RCBA32(SPIBAR_FDATA(i/sizeof(u32))); - for (j = 0; j < (size-i); j++) { - *ptr8++ = temp & 0xff; - temp >>= 8; - } - } - } - - return size; -} - -int early_spi_read(u32 offset, u32 size, u8 *buffer) -{ - u32 current = 0; - - while (size > 0) { - u8 count = (size < 64) ? size : 64; - if (early_spi_read_block(offset + current, count, - buffer + current) < 0) - return -1; - size -= count; - current += count; - } - - return 0; -} diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 21b6031..57b1271 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -70,7 +70,6 @@ void enable_smbus(void); void enable_usb_bar(void); int smbus_read_byte(unsigned device, unsigned address); -int early_spi_read(u32 offset, u32 size, u8 *buffer); void early_thermal_init(void); void southbridge_configure_default_intmap(void); void southbridge_rcba_config(void); diff --git a/src/southbridge/intel/fsp_rangeley/Makefile.inc b/src/southbridge/intel/fsp_rangeley/Makefile.inc index 7fc8601..67a51af 100644 --- a/src/southbridge/intel/fsp_rangeley/Makefile.inc +++ b/src/southbridge/intel/fsp_rangeley/Makefile.inc @@ -23,7 +23,7 @@ ramstage-y += smbus.c ramstage-y += acpi.c -romstage-y += early_usb.c early_smbus.c gpio.c early_spi.c early_init.c +romstage-y += early_usb.c early_smbus.c gpio.c early_init.c romstage-y += romstage.c bootblock-$(CONFIG_USBDEBUG) += usb_debug.c diff --git a/src/southbridge/intel/fsp_rangeley/early_spi.c b/src/southbridge/intel/fsp_rangeley/early_spi.c deleted file mode 100644 index 7b20cdb..0000000 --- a/src/southbridge/intel/fsp_rangeley/early_spi.c +++ /dev/null @@ -1,108 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Google Inc. All rights reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <device/pci_def.h> -#include <delay.h> -#include "soc.h" - -#define SPI_DELAY 10 /* 10us */ -#define SPI_RETRY 200000 /* 2s */ - -static int early_spi_read_block(u32 offset, u8 size, u8 *buffer) -{ - u32 *ptr32 = (u32*)buffer; - u32 i; - - /* Clear status bits */ - RCBA16(SPIBAR_HSFS) |= SPIBAR_HSFS_AEL | SPIBAR_HSFS_FCERR | - SPIBAR_HSFS_FDONE; - - if (RCBA16(SPIBAR_HSFS) & SPIBAR_HSFS_SCIP) { - printk(BIOS_ERR, "SPI ERROR: transaction in progress\n"); - return -1; - } - - /* Set flash address */ - RCBA32(SPIBAR_FADDR) = offset; - - /* Setup read transaction */ - RCBA16(SPIBAR_HSFC) = SPIBAR_HSFC_BYTE_COUNT(size) | - SPIBAR_HSFC_CYCLE_READ; - - /* Start transaction */ - RCBA16(SPIBAR_HSFC) |= SPIBAR_HSFC_GO; - - /* Wait for completion */ - for (i = 0; i < SPI_RETRY; i++) { - if (RCBA16(SPIBAR_HSFS) & SPIBAR_HSFS_SCIP) { - /* Cycle in progress, wait 1ms */ - udelay(SPI_DELAY); - continue; - } - - if (RCBA16(SPIBAR_HSFS) & SPIBAR_HSFS_AEL) { - printk(BIOS_ERR, "SPI ERROR: Access Error\n"); - return -1; - - } - - if (RCBA16(SPIBAR_HSFS) & SPIBAR_HSFS_FCERR) { - printk(BIOS_ERR, "SPI ERROR: Flash Cycle Error\n"); - return -1; - } - break; - } - - if (i >= SPI_RETRY) { - printk(BIOS_ERR, "SPI ERROR: Timeout\n"); - return -1; - } - - /* Read the data */ - for (i = 0; i < size; i+=sizeof(u32)) { - if (size-i >= 4) { - /* reading >= dword */ - *ptr32++ = RCBA32(SPIBAR_FDATA(i/sizeof(u32))); - } else { - /* reading < dword */ - u8 j, *ptr8 = (u8*)ptr32; - u32 temp = RCBA32(SPIBAR_FDATA(i/sizeof(u32))); - for (j = 0; j < (size-i); j++) { - *ptr8++ = temp & 0xff; - temp >>= 8; - } - } - } - - return size; -} - -int early_spi_read(u32 offset, u32 size, u8 *buffer) -{ - u32 current = 0; - - while (size > 0) { - u8 count = (size < 64) ? size : 64; - if (early_spi_read_block(offset + current, count, - buffer + current) < 0) - return -1; - size -= count; - current += count; - } - - return 0; -} diff --git a/src/southbridge/intel/fsp_rangeley/soc.h b/src/southbridge/intel/fsp_rangeley/soc.h index 4c5e835..aceb425 100644 --- a/src/southbridge/intel/fsp_rangeley/soc.h +++ b/src/southbridge/intel/fsp_rangeley/soc.h @@ -68,7 +68,6 @@ void enable_smbus(void); void enable_usb_bar(void); int smbus_read_byte(unsigned device, unsigned address); -int early_spi_read(u32 offset, u32 size, u8 *buffer); void rangeley_sb_early_initialization(void); #endif #endif diff --git a/src/southbridge/intel/ibexpeak/Makefile.inc b/src/southbridge/intel/ibexpeak/Makefile.inc index 2fb3718..6bd4a22 100644 --- a/src/southbridge/intel/ibexpeak/Makefile.inc +++ b/src/southbridge/intel/ibexpeak/Makefile.inc @@ -40,7 +40,5 @@ romstage-y += ../bd82x6x/early_usb.c early_smbus.c ../bd82x6x/early_me.c ../bd82x6x/me_status.c ../common/gpio.c early_thermal.c romstage-y += ../bd82x6x/early_rcba.c -romstage-$(CONFIG_SOUTHBRIDGE_INTEL_BD82X6X) += ../bd82x6x/early_spi.c -romstage-$(CONFIG_SOUTHBRIDGE_INTEL_C216) += ../bd82x6x/early_spi.c endif diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h index 9b2dd8a..7f40e2e 100644 --- a/src/southbridge/intel/ibexpeak/pch.h +++ b/src/southbridge/intel/ibexpeak/pch.h @@ -72,7 +72,6 @@ int smbus_write_byte(unsigned device, unsigned address, u8 data); int smbus_block_read(unsigned device, unsigned cmd, u8 bytes, u8 *buf); int smbus_block_write(unsigned device, unsigned cmd, u8 bytes, const u8 *buf); -int early_spi_read(u32 offset, u32 size, u8 *buffer); void early_thermal_init(void); void southbridge_configure_default_intmap(void); #endif diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc index f0bfa5b..3e3ef35 100644 --- a/src/southbridge/intel/lynxpoint/Makefile.inc +++ b/src/southbridge/intel/lynxpoint/Makefile.inc @@ -47,7 +47,7 @@ bootblock-y += early_pch.c romstage-y += early_usb.c early_smbus.c early_me.c me_status.c early_pch.c -romstage-y += early_spi.c rcba.c pmutil.c +romstage-y += rcba.c pmutil.c ifeq ($(CONFIG_INTEL_LYNXPOINT_LP),y) romstage-y += lp_gpio.c diff --git a/src/southbridge/intel/lynxpoint/early_spi.c b/src/southbridge/intel/lynxpoint/early_spi.c deleted file mode 100644 index 3034930..0000000 --- a/src/southbridge/intel/lynxpoint/early_spi.c +++ /dev/null @@ -1,108 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Google Inc. All rights reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <device/pci_def.h> -#include <delay.h> -#include "pch.h" - -#define SPI_DELAY 10 /* 10us */ -#define SPI_RETRY 200000 /* 2s */ - -static int early_spi_read_block(u32 offset, u8 size, u8 *buffer) -{ - u32 *ptr32 = (u32*)buffer; - u32 i; - - /* Clear status bits */ - RCBA16(SPIBAR_HSFS) |= SPIBAR_HSFS_AEL | SPIBAR_HSFS_FCERR | - SPIBAR_HSFS_FDONE; - - if (RCBA16(SPIBAR_HSFS) & SPIBAR_HSFS_SCIP) { - printk(BIOS_ERR, "SPI ERROR: transaction in progress\n"); - return -1; - } - - /* Set flash address */ - RCBA32(SPIBAR_FADDR) = offset; - - /* Setup read transaction */ - RCBA16(SPIBAR_HSFC) = SPIBAR_HSFC_BYTE_COUNT(size) | - SPIBAR_HSFC_CYCLE_READ; - - /* Start transactinon */ - RCBA16(SPIBAR_HSFC) |= SPIBAR_HSFC_GO; - - /* Wait for completion */ - for (i = 0; i < SPI_RETRY; i++) { - if (RCBA16(SPIBAR_HSFS) & SPIBAR_HSFS_SCIP) { - /* Cycle in progress, wait 1ms */ - udelay(SPI_DELAY); - continue; - } - - if (RCBA16(SPIBAR_HSFS) & SPIBAR_HSFS_AEL) { - printk(BIOS_ERR, "SPI ERROR: Access Error\n"); - return -1; - - } - - if (RCBA16(SPIBAR_HSFS) & SPIBAR_HSFS_FCERR) { - printk(BIOS_ERR, "SPI ERROR: Flash Cycle Error\n"); - return -1; - } - break; - } - - if (i >= SPI_RETRY) { - printk(BIOS_ERR, "SPI ERROR: Timeout\n"); - return -1; - } - - /* Read the data */ - for (i = 0; i < size; i+=sizeof(u32)) { - if (size-i >= 4) { - /* reading >= dword */ - *ptr32++ = RCBA32(SPIBAR_FDATA(i/sizeof(u32))); - } else { - /* reading < dword */ - u8 j, *ptr8 = (u8*)ptr32; - u32 temp = RCBA32(SPIBAR_FDATA(i/sizeof(u32))); - for (j = 0; j < (size-i); j++) { - *ptr8++ = temp & 0xff; - temp >>= 8; - } - } - } - - return size; -} - -int early_spi_read(u32 offset, u32 size, u8 *buffer) -{ - u32 current = 0; - - while (size > 0) { - u8 count = (size < 64) ? size : 64; - if (early_spi_read_block(offset + current, count, - buffer + current) < 0) - return -1; - size -= count; - current += count; - } - - return 0; -} diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 97d0aa3..93c2bc5 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -195,7 +195,6 @@ void enable_smbus(void); void enable_usb_bar(void); int smbus_read_byte(unsigned device, unsigned address); -int early_spi_read(u32 offset, u32 size, u8 *buffer); int early_pch_init(const void *gpio_map, const struct rcba_config_instruction *rcba_config); void pch_enable_lpc(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/32688 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaddd7a688d431d40f38293939e084d19b286aed4 Gerrit-Change-Number: 32688 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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coreboot-gerrit May 2019