coreboot-gerrit May 2019

coreboot-gerrit@coreboot.org

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1485 discussions

Change in ...coreboot[master]: Kconfig: Enable CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM based on CONFI...
by Subrata Banik (Code Review) 31 May '19

31 May '19

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33145 Change subject: Kconfig: Enable CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM based on CONFIG_STAGE_RAMSTAGE ...................................................................... Kconfig: Enable CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM based on CONFIG_STAGE_RAMSTAGE Change-Id: I49768fe480fa35ccbcaee14b3e614ed7b905f66b Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/Kconfig 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/33145/1 diff --git a/src/Kconfig b/src/Kconfig index 770a80b..6b6d2bc 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -1210,6 +1210,10 @@ config COMPRESS_RAMSTAGE default y if !UNCOMPRESSED_RAMSTAGE +config CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM + depends on ARCH_X86 + default n if !STAGE_RAMSTAGE + config COMPRESS_PRERAM_STAGES depends on !ARCH_X86 default y -- To view, visit https://review.coreboot.org/c/coreboot/+/33145 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I49768fe480fa35ccbcaee14b3e614ed7b905f66b Gerrit-Change-Number: 33145 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/common/block/gpio: Fix the mask for gpio_pm_configure
by Furquan Shaikh (Code Review) 31 May '19

31 May '19

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33099 Change subject: soc/intel/common/block/gpio: Fix the mask for gpio_pm_configure ...................................................................... soc/intel/common/block/gpio: Fix the mask for gpio_pm_configure gpio_pm_configure clears out all the bits related to PM configuration in MISCCFG register and sets only the bits requested by mainboard. The mask as it is set currently results in preserving all PM bits instead of clearing them. This change updates the mask to ensure that the PM bits are cleared before setting the ones requested by mainboard. Change-Id: I5b8c04952775dc1e94fa229328be2f3c1102a468 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/soc/intel/common/block/gpio/gpio.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/33099/1 diff --git a/src/soc/intel/common/block/gpio/gpio.c b/src/soc/intel/common/block/gpio/gpio.c index d37601c..7ebf05a 100644 --- a/src/soc/intel/common/block/gpio/gpio.c +++ b/src/soc/intel/common/block/gpio/gpio.c @@ -615,7 +615,7 @@ { int i; size_t gpio_communities; - uint8_t misccfg_pm_mask = MISCCFG_ENABLE_GPIO_PM_CONFIG; + const uint8_t misccfg_pm_mask = ~MISCCFG_ENABLE_GPIO_PM_CONFIG; const struct pad_community *comm; comm = soc_gpio_get_community(&gpio_communities); -- To view, visit https://review.coreboot.org/c/coreboot/+/33099 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b8c04952775dc1e94fa229328be2f3c1102a468 Gerrit-Change-Number: 33099 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: qualcomm/common/qclib: Use CONFIG()
by Patrick Rudolph (Code Review) 30 May '19

30 May '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32836 Change subject: qualcomm/common/qclib: Use CONFIG() ...................................................................... qualcomm/common/qclib: Use CONFIG() Use CONFIG() instead of IS_ENABLED(). Change-Id: I9bd78726fcdcc9f477d7c230fc2cd2c3c3f80f6f Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/soc/qualcomm/common/qclib.c 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/32836/1 diff --git a/src/soc/qualcomm/common/qclib.c b/src/soc/qualcomm/common/qclib.c index 1fd79b5..73c5250 100644 --- a/src/soc/qualcomm/common/qclib.c +++ b/src/soc/qualcomm/common/qclib.c @@ -129,7 +129,7 @@ memset(ddr_region, 0, sizeof(struct region)); /* output area, QCLib copies console log buffer out */ - if (IS_ENABLED(CONFIG_CONSOLE_CBMEM)) + if (CONFIG(CONSOLE_CBMEM)) qclib_add_if_table_entry(QCLIB_TE_QCLIB_LOG_BUFFER, _qclib_serial_log, REGION_SIZE(qclib_serial_log), 0); @@ -152,11 +152,11 @@ } /* Enable QCLib serial output, based on Kconfig */ - if (IS_ENABLED(CONFIG_CONSOLE_SERIAL)) + if (CONFIG(CONSOLE_SERIAL)) qclib_cb_if_table.global_attributes = QCLIB_GA_ENABLE_UART_LOGGING; - if (IS_ENABLED(CONFIG_QC_SDI_ENABLE)) { + if (CONFIG(QC_SDI_ENABLE)) { struct prog qcsdi = PROG_INIT(PROG_REFCODE, CONFIG_CBFS_PREFIX "/qcsdi"); -- To view, visit https://review.coreboot.org/c/coreboot/+/32836 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9bd78726fcdcc9f477d7c230fc2cd2c3c3f80f6f Gerrit-Change-Number: 32836 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: google/grunt: Update Samsung K4AAG165WB-MCTD SPD Module Part Number
by Kevin Chiu (Code Review) 30 May '19

30 May '19

Hello Kevin Chiu, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/33018 to review the following change. Change subject: google/grunt: Update Samsung K4AAG165WB-MCTD SPD Module Part Number ...................................................................... google/grunt: Update Samsung K4AAG165WB-MCTD SPD Module Part Number Correct SPD Module Part Number to "K4AAG165WB-MCTD" from "M471A1K43BB1-CTD". BUG=b:133478308 BRANCH=master TEST=emerge-grunt coreboot chromeos-bootimage mosys memory spd print all 0 | DDR4 | SO-DIMM 0 | 1-78: Samsung | 00000000 | K4AAG165WB-MCTD 0 | 8192 | 1 | 64 0 | DDR4-1333, DDR4-1600, DDR4-2400 Signed-off-by: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Change-Id: I5037ddfa99d8509c8a84a575348f8ae8d61f38a1 --- M src/mainboard/google/kahlee/variants/baseboard/spd/samsung-K4AAG165WB-MCTD.spd.hex 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/33018/1 diff --git a/src/mainboard/google/kahlee/variants/baseboard/spd/samsung-K4AAG165WB-MCTD.spd.hex b/src/mainboard/google/kahlee/variants/baseboard/spd/samsung-K4AAG165WB-MCTD.spd.hex index ede001a..c50df63 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/spd/samsung-K4AAG165WB-MCTD.spd.hex +++ b/src/mainboard/google/kahlee/variants/baseboard/spd/samsung-K4AAG165WB-MCTD.spd.hex @@ -19,8 +19,8 @@ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -80 CE 00 00 00 00 00 00 00 4D 34 37 31 41 31 4B -34 33 42 42 31 2D 43 54 44 20 20 20 20 00 80 CE +80 CE 00 00 00 00 00 00 00 4B 34 41 41 47 31 36 +35 57 42 2D 4D 43 54 44 20 20 20 20 20 00 80 CE 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -- To view, visit https://review.coreboot.org/c/coreboot/+/33018 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5037ddfa99d8509c8a84a575348f8ae8d61f38a1 Gerrit-Change-Number: 33018 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-Reviewer: Kevin Chiu <kevin.chiu(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: src/vendorcode/amd/pi: Fix CONFIG() check issue in rules.h
by Subrata Banik (Code Review) 30 May '19

30 May '19

Hello ron minnich, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/33105 to review the following change. Change subject: src/vendorcode/amd/pi: Fix CONFIG() check issue in rules.h ...................................................................... src/vendorcode/amd/pi: Fix CONFIG() check issue in rules.h This patch fixes problem of adding CONFIG() check inside rules.h. Change-Id: Ifb6842d0efef3521642c5c399fdf2876f71b167a Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- M src/vendorcode/amd/pi/00670F00/Makefile.inc M src/vendorcode/amd/pi/Makefile.inc 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/33105/1 diff --git a/src/vendorcode/amd/pi/00670F00/Makefile.inc b/src/vendorcode/amd/pi/00670F00/Makefile.inc index 0e6f2af..790955a 100644 --- a/src/vendorcode/amd/pi/00670F00/Makefile.inc +++ b/src/vendorcode/amd/pi/00670F00/Makefile.inc @@ -77,8 +77,8 @@ @printf " CC $$(subst $(obj)/,,$$(@))\n" $(CC_libagesa) -c -MMD $(CFLAGS_libagesa) $(AGESA_CFLAGS) \ $(AGESA_INC) \ - -include $(src)/include/rules.h \ -include $(src)/include/kconfig.h \ + -include $(src)/include/rules.h \ -include $(src)/commonlib/include/commonlib/compiler.h \ -o $$@ \ $(agesa_src_path)/$(notdir $1) diff --git a/src/vendorcode/amd/pi/Makefile.inc b/src/vendorcode/amd/pi/Makefile.inc index 4c8db6a..4e8787b 100644 --- a/src/vendorcode/amd/pi/Makefile.inc +++ b/src/vendorcode/amd/pi/Makefile.inc @@ -100,8 +100,8 @@ @printf " CC $$(subst $(obj)/,,$$(@))\n" $(CC_libagesa) -c -MMD $(CFLAGS_libagesa) $(AGESA_CFLAGS) \ $(AGESA_INC) \ - -include $(src)/include/rules.h \ -include $(src)/include/kconfig.h \ + -include $(src)/include/rules.h \ -include $(src)/commonlib/include/commonlib/compiler.h \ -o $$@ \ $(agesa_src_path)/$(notdir $1) -- To view, visit https://review.coreboot.org/c/coreboot/+/33105 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifb6842d0efef3521642c5c399fdf2876f71b167a Gerrit-Change-Number: 33105 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/lenovo/*20*: Remove default FMAP
by Nico Huber (Code Review) 30 May '19

30 May '19

Hello Arthur Heymans, Patrick Rudolph, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/33110 to review the following change. Change subject: mb/lenovo/*20*: Remove default FMAP ...................................................................... mb/lenovo/*20*: Remove default FMAP These boards don't need a default FMAP. Moreover, having a default FMAP disables automatic integration of optional regions like `CONSOLE`. Also, these files contain an error: `COREBOOT` isn't placed at the top of the image. Resulting in default builds without a reset vector ;) Change-Id: If6331e19955034c02828e88902a5934c34d3e784 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/mainboard/lenovo/t420/Kconfig D src/mainboard/lenovo/t420/board.fmd M src/mainboard/lenovo/t420s/Kconfig D src/mainboard/lenovo/t420s/board.fmd M src/mainboard/lenovo/t520/Kconfig D src/mainboard/lenovo/t520/board.fmd M src/mainboard/lenovo/x220/Kconfig D src/mainboard/lenovo/x220/board.fmd 8 files changed, 0 insertions(+), 68 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/33110/1 diff --git a/src/mainboard/lenovo/t420/Kconfig b/src/mainboard/lenovo/t420/Kconfig index 3d3b56a..02bcc4f 100644 --- a/src/mainboard/lenovo/t420/Kconfig +++ b/src/mainboard/lenovo/t420/Kconfig @@ -46,7 +46,6 @@ config FMDFILE string default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/vboot-rwa.fmd" if VBOOT - default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/board.fmd" config MAINBOARD_DIR string diff --git a/src/mainboard/lenovo/t420/board.fmd b/src/mainboard/lenovo/t420/board.fmd deleted file mode 100644 index 04cf827..0000000 --- a/src/mainboard/lenovo/t420/board.fmd +++ /dev/null @@ -1,16 +0,0 @@ -FLASH@0xff800000 0x800000 { - SI_ALL@0x0 0x500000 { - SI_DESC@0x0 0x1000 - SI_GBE@0x1000 0x2000 - SI_ME@0x3000 0x4ed000 - } - SI_BIOS@0x500000 0x300000 { - RW_MRC_CACHE@0 0x10000 - SMMSTORE(PRESERVE)@0x10000 0x40000 - - WP_RO@0x50000 0x2a0000 { - FMAP@0x0 0x800 - COREBOOT(CBFS)@0x1000 0x29f000 - } - } -} diff --git a/src/mainboard/lenovo/t420s/Kconfig b/src/mainboard/lenovo/t420s/Kconfig index 1383d41..60735b0 100644 --- a/src/mainboard/lenovo/t420s/Kconfig +++ b/src/mainboard/lenovo/t420s/Kconfig @@ -45,7 +45,6 @@ config FMDFILE string default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/vboot-rwa.fmd" if VBOOT - default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/board.fmd" config MAINBOARD_DIR string diff --git a/src/mainboard/lenovo/t420s/board.fmd b/src/mainboard/lenovo/t420s/board.fmd deleted file mode 100644 index 04cf827..0000000 --- a/src/mainboard/lenovo/t420s/board.fmd +++ /dev/null @@ -1,16 +0,0 @@ -FLASH@0xff800000 0x800000 { - SI_ALL@0x0 0x500000 { - SI_DESC@0x0 0x1000 - SI_GBE@0x1000 0x2000 - SI_ME@0x3000 0x4ed000 - } - SI_BIOS@0x500000 0x300000 { - RW_MRC_CACHE@0 0x10000 - SMMSTORE(PRESERVE)@0x10000 0x40000 - - WP_RO@0x50000 0x2a0000 { - FMAP@0x0 0x800 - COREBOOT(CBFS)@0x1000 0x29f000 - } - } -} diff --git a/src/mainboard/lenovo/t520/Kconfig b/src/mainboard/lenovo/t520/Kconfig index ba17e80..e847f8e 100644 --- a/src/mainboard/lenovo/t520/Kconfig +++ b/src/mainboard/lenovo/t520/Kconfig @@ -58,7 +58,6 @@ config FMDFILE string default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/vboot-rwa.fmd" if VBOOT - default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/board.fmd" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/lenovo/t520/board.fmd b/src/mainboard/lenovo/t520/board.fmd deleted file mode 100644 index 04cf827..0000000 --- a/src/mainboard/lenovo/t520/board.fmd +++ /dev/null @@ -1,16 +0,0 @@ -FLASH@0xff800000 0x800000 { - SI_ALL@0x0 0x500000 { - SI_DESC@0x0 0x1000 - SI_GBE@0x1000 0x2000 - SI_ME@0x3000 0x4ed000 - } - SI_BIOS@0x500000 0x300000 { - RW_MRC_CACHE@0 0x10000 - SMMSTORE(PRESERVE)@0x10000 0x40000 - - WP_RO@0x50000 0x2a0000 { - FMAP@0x0 0x800 - COREBOOT(CBFS)@0x1000 0x29f000 - } - } -} diff --git a/src/mainboard/lenovo/x220/Kconfig b/src/mainboard/lenovo/x220/Kconfig index 358cf8e..c80c2520 100644 --- a/src/mainboard/lenovo/x220/Kconfig +++ b/src/mainboard/lenovo/x220/Kconfig @@ -53,7 +53,6 @@ config FMDFILE string default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/vboot-rwa.fmd" if VBOOT - default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/board.fmd" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/lenovo/x220/board.fmd b/src/mainboard/lenovo/x220/board.fmd deleted file mode 100644 index 04cf827..0000000 --- a/src/mainboard/lenovo/x220/board.fmd +++ /dev/null @@ -1,16 +0,0 @@ -FLASH@0xff800000 0x800000 { - SI_ALL@0x0 0x500000 { - SI_DESC@0x0 0x1000 - SI_GBE@0x1000 0x2000 - SI_ME@0x3000 0x4ed000 - } - SI_BIOS@0x500000 0x300000 { - RW_MRC_CACHE@0 0x10000 - SMMSTORE(PRESERVE)@0x10000 0x40000 - - WP_RO@0x50000 0x2a0000 { - FMAP@0x0 0x800 - COREBOOT(CBFS)@0x1000 0x29f000 - } - } -} -- To view, visit https://review.coreboot.org/c/coreboot/+/33110 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If6331e19955034c02828e88902a5934c34d3e784 Gerrit-Change-Number: 33110 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: [WIP] mb/roda/rk9: Document flash header
by Nico Huber (Code Review) 30 May '19

30 May '19

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32025 Change subject: [WIP] mb/roda/rk9: Document flash header ...................................................................... [WIP] mb/roda/rk9: Document flash header Change-Id: I5bd131635340ffa0c6b8979fc8e263fc5f09fdc5 --- A Documentation/mainboard/roda/rk9/flash_header.md 1 file changed, 23 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/32025/1 diff --git a/Documentation/mainboard/roda/rk9/flash_header.md b/Documentation/mainboard/roda/rk9/flash_header.md new file mode 100644 index 0000000..26efcb4 --- /dev/null +++ b/Documentation/mainboard/roda/rk9/flash_header.md @@ -0,0 +1,23 @@ +Flash Header +============ + +There is a 5x2 pin, 1.27mm pitch header "J1" south of the BIOS flash. It +follows the pinout of the Dediprog adaptor board: + + +------+ + | 1 2 | 1: HOLD 2 2: CS 2 + | 3 4 | 3: CS 1 4: VCC + | 5 6 | 5: MISO 6: HOLD 1 + | 7 8 | 7: 8: CLK + | 9 10 | 9: GND 10: MOSI + +------+ + +Pins 3 to 10 directly map to the regular SPI flash pinout. + +There is also a JP17 around. Ideally, it should be closed during +programming (isolates the SPI bus from the southbridge): + + +---+ + | 1 | 1: SF100-I/O3 + | 2 | 2: GND + +---+ -- To view, visit https://review.coreboot.org/c/coreboot/+/32025 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5bd131635340ffa0c6b8979fc8e263fc5f09fdc5 Gerrit-Change-Number: 32025 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: nb/intel/sandybridge: Remove the C native graphic init
by Nico Huber (Code Review) 30 May '19

30 May '19

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/27532 ) Change subject: nb/intel/sandybridge: Remove the C native graphic init ...................................................................... Patch Set 11: > I think this patch orphaned code in src/mainboard/google/link/i915.c, and (presumably) broke Link when selecting DO_NATIVE_VGA_INIT in menuconfig. If the intention was to get rid of that option entirely, can you please remove HAS_NATIVE_VGA_INIT and any associated code from affected boards? Somebody must have missed your message ^^ I looked into it and also fixed two more odd occurences of DO_NATIVE_VGA_INIT. -- To view, visit https://review.coreboot.org/c/coreboot/+/27532 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic6678d3455f1116e7e67a67b465a79df020b2399 Gerrit-Change-Number: 27532 Gerrit-PatchSet: 11 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Thu, 30 May 2019 13:33:53 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/lenovo/t520: Add support for VBOOT
by Patrick Rudolph (Code Review) 30 May '19

30 May '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32585 Change subject: mb/lenovo/t520: Add support for VBOOT ...................................................................... mb/lenovo/t520: Add support for VBOOT Enable VBOOT support using a single RW_MAIN_A partition, allowing the use of tianocore payload in both RW_MAIN_A and WP_RO. Tested on Lenovo T520. Change-Id: Icb7b263ed86551cc53e1db7babccaca6b3ae2fe6 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/mainboard/lenovo/t520/Kconfig A src/mainboard/lenovo/t520/board.fmd M src/mainboard/lenovo/t520/cmos.layout A src/mainboard/lenovo/t520/vboot-rwa.fmd 4 files changed, 69 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/32585/1 diff --git a/src/mainboard/lenovo/t520/Kconfig b/src/mainboard/lenovo/t520/Kconfig index 06f296b..567ebc0 100644 --- a/src/mainboard/lenovo/t520/Kconfig +++ b/src/mainboard/lenovo/t520/Kconfig @@ -27,6 +27,22 @@ if BOARD_LENOVO_BASEBOARD_T520 +config VBOOT + select VBOOT_VBNV_CMOS + select VBOOT_NO_BOARD_SUPPORT + select GBB_FLAG_DISABLE_LID_SHUTDOWN + select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_FWMP + select HAS_RECOVERY_MRC_CACHE + +config VBOOT_SLOTS_RW_A + default y + +config VBOOT_VBNV_OFFSET + hex + default 0x2a + config VARIANT_DIR string default "t520" if BOARD_LENOVO_T520 @@ -40,6 +56,11 @@ string default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" +config FMDFILE + string + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/vboot-rwa.fmd" if VBOOT + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/board.fmd" + config MAINBOARD_PART_NUMBER string default "ThinkPad T520" if BOARD_LENOVO_T520 diff --git a/src/mainboard/lenovo/t520/board.fmd b/src/mainboard/lenovo/t520/board.fmd new file mode 100644 index 0000000..04cf827 --- /dev/null +++ b/src/mainboard/lenovo/t520/board.fmd @@ -0,0 +1,16 @@ +FLASH@0xff800000 0x800000 { + SI_ALL@0x0 0x500000 { + SI_DESC@0x0 0x1000 + SI_GBE@0x1000 0x2000 + SI_ME@0x3000 0x4ed000 + } + SI_BIOS@0x500000 0x300000 { + RW_MRC_CACHE@0 0x10000 + SMMSTORE(PRESERVE)@0x10000 0x40000 + + WP_RO@0x50000 0x2a0000 { + FMAP@0x0 0x800 + COREBOOT(CBFS)@0x1000 0x29f000 + } + } +} diff --git a/src/mainboard/lenovo/t520/cmos.layout b/src/mainboard/lenovo/t520/cmos.layout index 1a7943e..ec6ce85 100644 --- a/src/mainboard/lenovo/t520/cmos.layout +++ b/src/mainboard/lenovo/t520/cmos.layout @@ -81,6 +81,9 @@ #437 3 r 0 unused 440 8 h 0 volume +# VBOOT +448 128 r 0 vbnv + # SandyBridge MRC Scrambler Seed values 896 32 r 0 mrc_scrambler_seed 928 32 r 0 mrc_scrambler_seed_s3 diff --git a/src/mainboard/lenovo/t520/vboot-rwa.fmd b/src/mainboard/lenovo/t520/vboot-rwa.fmd new file mode 100644 index 0000000..8a4cd3b --- /dev/null +++ b/src/mainboard/lenovo/t520/vboot-rwa.fmd @@ -0,0 +1,29 @@ +FLASH@0xff800000 0x800000 { + SI_ALL@0x0 0x500000 { + SI_DESC@0x0 0x1000 + SI_GBE@0x1000 0x2000 + SI_ME@0x3000 0x4ed000 + } + SI_BIOS@0x500000 0x300000 { + RW_SECTION_A@0x00000 0x180000 { + VBLOCK_A@0x0 0x10000 + FW_MAIN_A(CBFS)@0x10000 0x16ffc0 + RW_FWID_A@0x17ffc0 0x40 + } + UNIFIED_MRC_CACHE@0x180000 0x20000 { + RECOVERY_MRC_CACHE@0x0 0x10000 + RW_MRC_CACHE@0x10000 0x10000 + } + RW_VPD(PRESERVE)@0x1a0000 0x1000 + SMMSTORE(PRESERVE)@0x1a1000 0x40000 + + WP_RO@0x1e1000 0x11f000 { + FMAP@0x0 0x800 + RO_FRID@0x800 0x40 + RO_PADDING@0x840 0x7c0 + RO_VPD(PRESERVE)@0x1000 0x1000 + GBB@0x2000 0x1e000 + COREBOOT(CBFS)@0x20000 0xff000 + } + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/32585 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icb7b263ed86551cc53e1db7babccaca6b3ae2fe6 Gerrit-Change-Number: 32585 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mediatek/mt8183: Add soc ARM Trusted Firmware support
by jitao shi (Code Review) 30 May '19

30 May '19

jitao shi has uploaded a new patch set (#10) to the change originally created by Tristan Hsieh. ( https://review.coreboot.org/c/coreboot/+/29186 ) Change subject: mediatek/mt8183: Add soc ARM Trusted Firmware support ...................................................................... mediatek/mt8183: Add soc ARM Trusted Firmware support Set BL31 platform to mt8183 to link with ARM Trusted Firmware. BUG=b:80501386 BRANCH=none Test=Boots correctly on Kukui with more patches in ATF. Change-Id: Ia988d2b4ed646027c04c7c6ff0e50ed7a0b14da3 Signed-off-by: kenny liang <kenny.liang(a)mediatek.com> --- M src/soc/mediatek/mt8183/Makefile.inc 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/29186/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/29186 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia988d2b4ed646027c04c7c6ff0e50ed7a0b14da3 Gerrit-Change-Number: 29186 Gerrit-PatchSet: 10 Gerrit-Owner: Tristan Hsieh <tristan.shieh(a)mediatek.com> Gerrit-Reviewer: Erin Lo <erin.lo(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Joel Kitching <kitching(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Tristan Hsieh <tristan.shieh(a)mediatek.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: jitao shi <jitao.shi(a)mediatek.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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coreboot-gerrit May 2019