Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31249
Change subject: soc/intel/denverton_ns: Don't use CONFIG_CBFS_SIZE
......................................................................
soc/intel/denverton_ns: Don't use CONFIG_CBFS_SIZE
CONFIG_CBFS_SIZE is only meaningful to generate the default fmap
layout and ought not to be used in the code directly.
Change-Id: Iae72a9fb02d62d7548d34689f5eb371f34cd3d81
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/soc/intel/denverton_ns/bootblock/bootblock.c
1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/31249/1
diff --git a/src/soc/intel/denverton_ns/bootblock/bootblock.c b/src/soc/intel/denverton_ns/bootblock/bootblock.c
index 110d67d..58144bd 100644
--- a/src/soc/intel/denverton_ns/bootblock/bootblock.c
+++ b/src/soc/intel/denverton_ns/bootblock/bootblock.c
@@ -37,8 +37,8 @@
.MicrocodeRegionLength =
(UINT32)CONFIG_CPU_MICROCODE_CBFS_LEN,
.CodeRegionBase =
- (UINT32)(0x100000000ULL - CONFIG_CBFS_SIZE),
- .CodeRegionLength = (UINT32)CONFIG_CBFS_SIZE,
+ (UINT32)(0x100000000ULL - CONFIG_ROM_SIZE),
+ .CodeRegionLength = (UINT32)CONFIG_ROM_SIZE,
.Reserved1 = {0},
},
.FsptConfig = {
--
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Gerrit-Change-Id: Iae72a9fb02d62d7548d34689f5eb371f34cd3d81
Gerrit-Change-Number: 31249
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-MessageType: newchange
Christian Walter has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33014
Change subject: payloads/external/Linuxboot: Fix Makefile when not using bash
......................................................................
payloads/external/Linuxboot: Fix Makefile when not using bash
Adding "SHELL := /bin/bash" to the Makefile makes sure, that we use the
bash shell which is needed here.
Tested with oh-my-zsh.
Change-Id: I71495e15b8f1a495af7d8ab21cc5235feb595e01
Signed-off-by: Christian Walter <christian.walter(a)9elements.com>
---
M payloads/external/LinuxBoot/targets/linux.mk
1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/33014/1
diff --git a/payloads/external/LinuxBoot/targets/linux.mk b/payloads/external/LinuxBoot/targets/linux.mk
index 5632a0b..e32ad1e 100644
--- a/payloads/external/LinuxBoot/targets/linux.mk
+++ b/payloads/external/LinuxBoot/targets/linux.mk
@@ -12,6 +12,7 @@
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
+SHELL := /bin/bash
ARCH-$(CONFIG_LINUXBOOT_X86_64)=x86_64
ARCH-$(CONFIG_LINUXBOOT_X86)=x86
--
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Gerrit-Change-Id: I71495e15b8f1a495af7d8ab21cc5235feb595e01
Gerrit-Change-Number: 33014
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Gerrit-Owner: Christian Walter <christian.walter(a)9elements.com>
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Christian Walter has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32965
Change subject: src/soc/intel/skylake/chip.h: Add smbios.h for Type9 Entries
......................................................................
src/soc/intel/skylake/chip.h: Add smbios.h for Type9 Entries
In order to add the smbios_slot_desc for the SMBIOS Type9 entries into
the devicetree, and not use numbers but strings like
"SlotTypePciExpressGen3X4", smbios.h needs to be included in the
static.c.
Change-Id: Iace547868b4ce8eb7d3624baf1abd1187c1e5f51
Signed-off-by: Christian Walter <christian.walter(a)9elements.com>
---
M src/soc/intel/skylake/chip.h
1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/32965/1
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h
index 57d51e7..a537165 100644
--- a/src/soc/intel/skylake/chip.h
+++ b/src/soc/intel/skylake/chip.h
@@ -34,6 +34,7 @@
#include <soc/serialio.h>
#include <soc/usb.h>
#include <soc/vr_config.h>
+#include <smbios.h>
#define MAX_PEG_PORTS 3
--
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Gerrit-Change-Id: Iace547868b4ce8eb7d3624baf1abd1187c1e5f51
Gerrit-Change-Number: 32965
Gerrit-PatchSet: 1
Gerrit-Owner: Christian Walter <christian.walter(a)9elements.com>
Gerrit-MessageType: newchange
Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/20782 )
Change subject: payloads/external/iPXE: Add more Kconfig options
......................................................................
payloads/external/iPXE: Add more Kconfig options
Add two new options:
* Disable the prompt "Press Ctrl+B for the iPXE command line..."
Add a boolean that disables the initial 2 second timeout.
* Include a script that is executed instead of showing a shell.
Allows to add a script that will be included into the iPXE ROM.
Tested on Lenovo T500 and PC Engines apu2.
Change-Id: Ie1083d8571d9d1f1c7c71659fb6ff0de2eecad0e
Signed-off-by: Patrick Rudolph <siro(a)das-labor.org>
Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/20782
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi(a)google.com>
---
M payloads/external/Makefile.inc
M payloads/external/iPXE/Kconfig
M payloads/external/iPXE/Makefile
3 files changed, 53 insertions(+), 3 deletions(-)
Approvals:
build bot (Jenkins): Verified
Patrick Georgi: Looks good to me, approved
Michał Żygowski: Looks good to me, approved
diff --git a/payloads/external/Makefile.inc b/payloads/external/Makefile.inc
index 5edbb81..9c34efa 100644
--- a/payloads/external/Makefile.inc
+++ b/payloads/external/Makefile.inc
@@ -229,7 +229,9 @@
ifeq ($(CONFIG_BUILD_IPXE),y)
PXE_ROM_FILE:=payloads/external/iPXE/ipxe/ipxe.rom
endif
-
+ifeq ($(CONFIG_PXE_ADD_SCRIPT),y)
+PXE_CONFIG_SCRIPT:=$(abspath $(patsubst "%",%,$(CONFIG_PXE_SCRIPT)))
+endif
ifeq ($(CONFIG_CONSOLE_SERIAL)$(CONFIG_DRIVERS_UART_8250IO),yy)
IPXE_UART=COM$(call int-add,$(CONFIG_UART_FOR_CONSOLE) 1)
endif
@@ -244,7 +246,7 @@
pci$(CONFIG_PXE_ROM_ID).rom-file := $(PXE_ROM_FILE)
pci$(CONFIG_PXE_ROM_ID).rom-type := raw
-payloads/external/iPXE/ipxe/ipxe.rom ipxe: $(DOTCONFIG)
+payloads/external/iPXE/ipxe/ipxe.rom ipxe: $(DOTCONFIG) $(PXE_CONFIG_SCRIPT)
$(MAKE) -C payloads/external/iPXE all \
CROSS_COMPILE="$(CROSS_COMPILE_$(ARCH-ramstage-y))" \
PXE_ROM_PCI_ID=$(PXE_ROM_PCI_ID) \
@@ -253,6 +255,9 @@
CONSOLE_SERIAL=$(IPXE_SERIAL_CONSOLE) \
IPXE_UART=$(IPXE_UART) \
CONFIG_TTYS0_BAUD=$(CONFIG_TTYS0_BAUD) \
+ CONFIG_SCRIPT=$(PXE_CONFIG_SCRIPT) \
+ CONFIG_HAS_SCRIPT=$(CONFIG_PXE_ADD_SCRIPT) \
+ CONFIG_PXE_NO_PROMT=$(CONFIG_PXE_NO_PROMT) \
MFLAGS= MAKEFLAGS=
# LinuxBoot
diff --git a/payloads/external/iPXE/Kconfig b/payloads/external/iPXE/Kconfig
index f99182c..7cb0d1e 100644
--- a/payloads/external/iPXE/Kconfig
+++ b/payloads/external/iPXE/Kconfig
@@ -87,5 +87,31 @@
Unselect to let only SeaBIOS handle printing output.
+config PXE_NO_PROMT
+ bool "Do not show prompt to boot from PXE"
+ default n
+ depends on BUILD_IPXE
+ help
+ Don't wait for the user to press Ctrl-B.
+ The PXE still can be run as it shows up in SeaBIOS's payload list.
+
+config PXE_ADD_SCRIPT
+ bool "Embed an iPXE script for automated provisioning"
+ depends on BUILD_IPXE
+ default n
+ help
+ Enable to embed a script that is run instead of an iPXE shell.
+
+config PXE_SCRIPT
+ string "Embedded iPXE script path and filename"
+ depends on PXE_ADD_SCRIPT
+ default ""
+ help
+ Path to a script that is embedded into the iPXE binary.
+ Example: startup.ipxe
+
+ Uses the ipxe script instead showing the prompt:
+ "Press Ctrl-B to start iPXE..."
+
endmenu
endif
diff --git a/payloads/external/iPXE/Makefile b/payloads/external/iPXE/Makefile
index 3a0585f..0c071fa 100644
--- a/payloads/external/iPXE/Makefile
+++ b/payloads/external/iPXE/Makefile
@@ -54,15 +54,34 @@
sed 's|#define\s*COMCONSOLE.*|#define COMCONSOLE $(IPXE_UART)|' "$(project_dir)/src/config/serial.h" > "$(project_dir)/src/config/serial.h.tmp"
sed 's|#define\s*COMSPEED.*|#define COMSPEED $(CONFIG_TTYS0_BAUD)|' "$(project_dir)/src/config/serial.h.tmp" > "$(project_dir)/src/config/serial.h"
endif
+ifneq ($(filter y,$(CONFIG_HAS_SCRIPT) $(CONFIG_PXE_NO_PROMT)),)
+ cp "$(project_dir)/src/config/general.h" "$(project_dir)/src/config/general.h.cb"
+endif
+ifeq ($(CONFIG_HAS_SCRIPT),y)
+ sed 's|//#define\s*IMAGE_SCRIPT.*|#define IMAGE_SCRIPT|' "$(project_dir)/src/config/general.h" > "$(project_dir)/src/config/general.h.tmp"
+ mv "$(project_dir)/src/config/general.h.tmp" "$(project_dir)/src/config/general.h"
+endif
+ifeq ($(CONFIG_PXE_NO_PROMT),y)
+ sed 's|#define\s*BANNER_TIMEOUT.*|#define BANNER_TIMEOUT 0|' "$(project_dir)/src/config/general.h" > "$(project_dir)/src/config/general.h.tmp"
+ mv "$(project_dir)/src/config/general.h.tmp" "$(project_dir)/src/config/general.h"
+endif
-build: config
+build: config $(CONFIG_SCRIPT)
+ifeq ($(CONFIG_HAS_SCRIPT),y)
+ echo " MAKE $(project_name) $(TAG-y) EMBED=$(CONFIG_SCRIPT)"
+ $(MAKE) -C $(project_dir)/src bin/$(PXE_ROM_PCI_ID).rom EMBED=$(CONFIG_SCRIPT)
+else
echo " MAKE $(project_name) $(TAG-y)"
$(MAKE) -C $(project_dir)/src bin/$(PXE_ROM_PCI_ID).rom
+endif
cp $(project_dir)/src/bin/$(PXE_ROM_PCI_ID).rom $(project_dir)/ipxe.rom
ifeq ($(CONSOLE_SERIAL),yy)
cp "$(project_dir)/src/config/console.h.cb" "$(project_dir)/src/config/console.h"
cp "$(project_dir)/src/config/serial.h.cb" "$(project_dir)/src/config/serial.h"
endif
+ifneq ($(filter y,$(CONFIG_HAS_SCRIPT) $(CONFIG_PXE_NO_PROMT)),)
+ cp "$(project_dir)/src/config/general.h.cb" "$(project_dir)/src/config/general.h"
+endif
clean:
test -d $(project_dir) && $(MAKE) -C $(project_dir)/src veryclean || exit 0
--
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Gerrit-Change-Id: Ie1083d8571d9d1f1c7c71659fb6ff0de2eecad0e
Gerrit-Change-Number: 20782
Gerrit-PatchSet: 5
Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com>
Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net>
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Gerrit-MessageType: merged
Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/20782 )
Change subject: payloads/external/iPXE: Add more Kconfig options
......................................................................
Patch Set 4: Code-Review+2
--
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Gerrit-Change-Id: Ie1083d8571d9d1f1c7c71659fb6ff0de2eecad0e
Gerrit-Change-Number: 20782
Gerrit-PatchSet: 4
Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com>
Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
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Gerrit-Comment-Date: Wed, 29 May 2019 20:21:37 +0000
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Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32962
Change subject: soc/intel/skylake: Use common cpu/intel/car romstage code
......................................................................
soc/intel/skylake: Use common cpu/intel/car romstage code
Setting up the console and entering postcar can be done in a common
place.
Change-Id: I8a8db0fcb4f0fbbb121a8195a8a8b6644c28db07
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/drivers/intel/fsp1_1/car.c
M src/drivers/intel/fsp1_1/include/fsp/car.h
M src/soc/intel/skylake/romstage/Makefile.inc
D src/soc/intel/skylake/romstage/car_stage.S
4 files changed, 4 insertions(+), 50 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/32962/1
diff --git a/src/drivers/intel/fsp1_1/car.c b/src/drivers/intel/fsp1_1/car.c
index 34b2518..2202121 100644
--- a/src/drivers/intel/fsp1_1/car.c
+++ b/src/drivers/intel/fsp1_1/car.c
@@ -15,6 +15,7 @@
#include <arch/early_variables.h>
#include <console/console.h>
+#include <cpu/intel/romstage.h>
#include <cpu/x86/mtrr.h>
#include <fsp/car.h>
#include <fsp/util.h>
@@ -27,7 +28,7 @@
/* platform_enter_postcar() determines the stack to use after
* cache-as-ram is torn down as well as the MTRR settings to use,
* and continues execution in postcar stage. */
-static void platform_enter_postcar(void)
+void platform_enter_postcar(void)
{
struct postcar_frame pcf;
size_t alignment;
@@ -155,15 +156,13 @@
/* This is the romstage C entry for platforms with
CONFIG_C_ENVIRONMENT_BOOTBLOCK */
-asmlinkage void romstage_c_entry(void)
+void mainboard_romstage_entry(unsigned long bist)
{
/* Need to locate the current FSP_INFO_HEADER. The cache-as-ram
* is still enabled. We can directly access work buffer here. */
FSP_INFO_HEADER *fih;
struct prog fsp = PROG_INIT(PROG_REFCODE, "fsp.bin");
- console_init();
-
if (prog_locate(&fsp)) {
fih = NULL;
printk(BIOS_ERR, "Unable to locate %s\n", prog_name(&fsp));
@@ -174,9 +173,6 @@
}
cache_as_ram_stage_main(fih);
-
- /* we don't return here */
- platform_enter_postcar();
}
void __weak car_mainboard_pre_console_init(void)
diff --git a/src/drivers/intel/fsp1_1/include/fsp/car.h b/src/drivers/intel/fsp1_1/include/fsp/car.h
index 0ae687a..c051392 100644
--- a/src/drivers/intel/fsp1_1/include/fsp/car.h
+++ b/src/drivers/intel/fsp1_1/include/fsp/car.h
@@ -31,7 +31,6 @@
/* Entry points from the cache-as-ram assembly code. */
asmlinkage void cache_as_ram_main(struct cache_as_ram_params *car_params);
-asmlinkage void romstage_c_entry(void);
/* Per stage calls from the above two functions. The void * return from
* cache_as_ram_stage_main() is the stack pointer to use in RAM after
* exiting cache-as-ram mode. */
diff --git a/src/soc/intel/skylake/romstage/Makefile.inc b/src/soc/intel/skylake/romstage/Makefile.inc
index 8bfbfea..e929eba 100644
--- a/src/soc/intel/skylake/romstage/Makefile.inc
+++ b/src/soc/intel/skylake/romstage/Makefile.inc
@@ -1,4 +1,4 @@
-romstage-$(CONFIG_PLATFORM_USES_FSP1_1) += car_stage.S
+romstage-$(CONFIG_PLATFORM_USES_FSP1_1) += ../../../../cpu/intel/car/romstage.c
romstage-$(CONFIG_PLATFORM_USES_FSP1_1) += romstage.c
romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += romstage_fsp20.c
romstage-y += systemagent.c
diff --git a/src/soc/intel/skylake/romstage/car_stage.S b/src/soc/intel/skylake/romstage/car_stage.S
deleted file mode 100644
index d8b45cb..0000000
--- a/src/soc/intel/skylake/romstage/car_stage.S
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <cpu/x86/post_code.h>
-
-/* I/O delay between post codes on failure */
-#define LHLT_DELAY 0x50000
-
-.text
-.global car_stage_entry
-car_stage_entry:
- call romstage_c_entry
-
- /* we don't return here */
- movb $0x69, %ah
- jmp .Lhlt
-
-.Lhlt:
- xchg %al, %ah
-#if CONFIG(POST_IO)
- outb %al, $CONFIG_POST_IO_PORT
-#else
- post_code(POST_DEAD_CODE)
-#endif
- movl $LHLT_DELAY, %ecx
-.Lhlt_Delay:
- outb %al, $0xED
- loop .Lhlt_Delay
- jmp .Lhlt
--
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Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz>
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