coreboot-gerrit May 2019

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Change in ...coreboot[master]: soc/intel/common: Add negative sign check for variable bios_size
by John Zhao (Code Review) 29 May '19

29 May '19

John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32924 Change subject: soc/intel/common: Add negative sign check for variable bios_size ...................................................................... soc/intel/common: Add negative sign check for variable bios_size Clang Static Analyzer found that the rounding operation of alignment=1UL<<(log2_ceil(bios_size)) is garbage or undefined if varialbe bios_size is negative. Add sanity check for bios_size to prevent rounding error. Signed-off-by: John Zhao <john.zhao(a)intel.com> Change-Id: Ifc3f3da52d129ef5d6063a46b045603a236be759 --- M src/soc/intel/common/block/fast_spi/fast_spi.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/32924/1 diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c index 455b13c..560c75c 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi.c +++ b/src/soc/intel/common/block/fast_spi/fast_spi.c @@ -236,7 +236,7 @@ /* Only the IFD BIOS region is memory mapped (at top of 4G) */ fast_spi_get_bios_region(&bios_size); - if (!bios_size) + if (!bios_size || (bios_size < 0)) return; /* LOCAL APIC default address is 0xFEE0000, bios_size over 16MB will -- To view, visit https://review.coreboot.org/c/coreboot/+/32924 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifc3f3da52d129ef5d6063a46b045603a236be759 Gerrit-Change-Number: 32924 Gerrit-PatchSet: 1 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/common: Set GSPI clock value to prevent division by zero
by John Zhao (Code Review) 29 May '19

29 May '19

John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32974 Change subject: soc/intel/common: Set GSPI clock value to prevent division by zero ...................................................................... soc/intel/common: Set GSPI clock value to prevent division by zero Clang Static Analyzer version 8.0.0 detects the division by zero if gspi_clk_mhz is initialized to 0. gspi_clk_mhz is referred to speed_mhz in devicetree. Set gspi_clk_mhz to 1 if it is detected as 0 in order to prevent the division by zero in DIV_ROUND_UP operation. Then the value of (ref_clk_mhz - 1) will be fed into GSPI's Serial Clock Rate value. TEST=Built and boot up to kernel. Change-Id: I6a09474bff114c57d7a9c4c232bb636ff287e4d5 Signed-off-by: John Zhao <john.zhao(a)intel.com> --- M src/soc/intel/common/block/gspi/gspi.c 1 file changed, 4 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/32974/1 diff --git a/src/soc/intel/common/block/gspi/gspi.c b/src/soc/intel/common/block/gspi/gspi.c index 81eb7ee..fb3bf7a 100644 --- a/src/soc/intel/common/block/gspi/gspi.c +++ b/src/soc/intel/common/block/gspi/gspi.c @@ -437,9 +437,11 @@ { const uint32_t ref_clk_mhz = CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ; - const uint32_t gspi_clk_mhz = gspi_get_bus_clk_mhz(gspi_bus); + uint32_t gspi_clk_mhz = gspi_get_bus_clk_mhz(gspi_bus); - assert(gspi_clk_mhz != 0); + if (!gspi_clk_mhz) + gspi_clk_mhz = 1; + assert(ref_clk_mhz != 0); return (DIV_ROUND_UP(ref_clk_mhz, gspi_clk_mhz) - 1) & SSCR0_SCR_MASK; } -- To view, visit https://review.coreboot.org/c/coreboot/+/32974 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6a09474bff114c57d7a9c4c232bb636ff287e4d5 Gerrit-Change-Number: 32974 Gerrit-PatchSet: 1 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: util/autoport: Add info about rank_mirror to readme.md
by Evgeny Zinoviev (Code Review) 29 May '19

29 May '19

Evgeny Zinoviev has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32683 Change subject: util/autoport: Add info about rank_mirror to readme.md ...................................................................... util/autoport: Add info about rank_mirror to readme.md inteltool can't detect whether address mapping is normal or mirrored, which in turn may be cause RAM initialization to fail when using spd.bin generated by inteltool. Mention this in readme as it may help someone. Change-Id: I8d24e4d9332bdcf484987581dd6941e2bf9c4f87 Signed-off-by: Evgeny Zinoviev <me(a)ch1p.io> --- M util/autoport/readme.md 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/32683/1 diff --git a/util/autoport/readme.md b/util/autoport/readme.md index 4683d8d..6e0a7ef 100644 --- a/util/autoport/readme.md +++ b/util/autoport/readme.md @@ -267,6 +267,10 @@ not forget to copy the data on all the array elements that need it. * If they use different data, use several files. +If memory initialization is not working, try enbling rank_mirror, which can't +be detected by inteltool. To do that, set the lowest bit at the offset `0x3f` +in `spd.bin` to 1. + ### `board_info.txt` `board_info.txt` is a text file used in the board status page to list all -- To view, visit https://review.coreboot.org/c/coreboot/+/32683 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d24e4d9332bdcf484987581dd6941e2bf9c4f87 Gerrit-Change-Number: 32683 Gerrit-PatchSet: 1 Gerrit-Owner: Evgeny Zinoviev <me(a)ch1p.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: drivers/intel/fsp2_0: Dont' use CAR_GLOBAL
by Arthur Heymans (Code Review) 29 May '19

29 May '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33003 Change subject: drivers/intel/fsp2_0: Dont' use CAR_GLOBAL ...................................................................... drivers/intel/fsp2_0: Dont' use CAR_GLOBAL All platforms using this code have NO_CAR_GLOBAL_MIGRATION. Change-Id: Ic50b16916261abb8c63b8fe571819af5c830ff8d Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/drivers/intel/fsp2_0/hand_off_block.c 1 file changed, 3 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/33003/1 diff --git a/src/drivers/intel/fsp2_0/hand_off_block.c b/src/drivers/intel/fsp2_0/hand_off_block.c index c5c78ca..95b80200 100644 --- a/src/drivers/intel/fsp2_0/hand_off_block.c +++ b/src/drivers/intel/fsp2_0/hand_off_block.c @@ -10,7 +10,6 @@ * (at your option) any later version. */ -#include <arch/early_variables.h> #include <device/mmio.h> #include <cbmem.h> #include <commonlib/helpers.h> @@ -100,7 +99,7 @@ * Utilities for locating and identifying HOBs */ -static void *fsp_hob_list_ptr CAR_GLOBAL; +static void *fsp_hob_list_ptr; static void save_hob_list(int is_recovery) { @@ -122,14 +121,14 @@ uint32_t *list_loc; if (ENV_ROMSTAGE) - return (void *)car_get_var(fsp_hob_list_ptr); + return fsp_hob_list_ptr; list_loc = cbmem_find(CBMEM_ID_FSP_RUNTIME); return (list_loc) ? (void *)(uintptr_t)(*list_loc) : NULL; } void *fsp_get_hob_list_ptr(void) { - return car_get_var_ptr(&fsp_hob_list_ptr); + return &fsp_hob_list_ptr; } static const -- To view, visit https://review.coreboot.org/c/coreboot/+/33003 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic50b16916261abb8c63b8fe571819af5c830ff8d Gerrit-Change-Number: 33003 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/common/pmc: Don't use CAR_GLOBAL
by Arthur Heymans (Code Review) 29 May '19

29 May '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33002 Change subject: soc/intel/common/pmc: Don't use CAR_GLOBAL ...................................................................... soc/intel/common/pmc: Don't use CAR_GLOBAL All platforms using this code use NO_CAR_GLOBAL_MIGRATION. Change-Id: I426dee60521045db4711cd253432c65223a64b93 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/common/block/pmc/pmclib.c 1 file changed, 3 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/33002/1 diff --git a/src/soc/intel/common/block/pmc/pmclib.c b/src/soc/intel/common/block/pmc/pmclib.c index f58d362..564aacb 100644 --- a/src/soc/intel/common/block/pmc/pmclib.c +++ b/src/soc/intel/common/block/pmc/pmclib.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <arch/early_variables.h> #include <arch/io.h> #include <device/mmio.h> #include <cbmem.h> @@ -27,7 +26,7 @@ #include <timer.h> #include <security/vboot/vboot_common.h> -static struct chipset_power_state power_state CAR_GLOBAL; +static struct chipset_power_state power_state; struct chipset_power_state *pmc_get_power_state(void) { @@ -38,7 +37,7 @@ /* cbmem is online but ptr is not populated yet */ if (ptr == NULL && !(ENV_RAMSTAGE || ENV_POSTCAR)) - return car_get_var_ptr(&power_state); + return &power_state; return ptr; } @@ -46,16 +45,14 @@ static void migrate_power_state(int is_recovery) { struct chipset_power_state *ps_cbmem; - struct chipset_power_state *ps_car; - ps_car = car_get_var_ptr(&power_state); ps_cbmem = cbmem_add(CBMEM_ID_POWER_STATE, sizeof(*ps_cbmem)); if (ps_cbmem == NULL) { printk(BIOS_DEBUG, "Not adding power state to cbmem!\n"); return; } - memcpy(ps_cbmem, ps_car, sizeof(*ps_cbmem)); + memcpy(ps_cbmem, &power_state, sizeof(*ps_cbmem)); } ROMSTAGE_CBMEM_INIT_HOOK(migrate_power_state) -- To view, visit https://review.coreboot.org/c/coreboot/+/33002 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I426dee60521045db4711cd253432c65223a64b93 Gerrit-Change-Number: 33002 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/common/cse: Don't use CAR_GLOBAL
by Arthur Heymans (Code Review) 29 May '19

29 May '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33001 Change subject: soc/intel/common/cse: Don't use CAR_GLOBAL ...................................................................... soc/intel/common/cse: Don't use CAR_GLOBAL All platforms using this code have NO_CAR_GLOBAL_MIGRATION. Change-Id: If952ad8129e1fa6e45858cb77ec99c9fec55c4a6 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/common/block/cse/cse.c 1 file changed, 9 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/33001/1 diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index 302e6de..6164580 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <arch/early_variables.h> #include <assert.h> #include <commonlib/helpers.h> #include <console/console.h> @@ -71,7 +70,7 @@ struct cse_device { uintptr_t sec_bar; -} g_cse CAR_GLOBAL; +} g_cse; /* * Initialize the device with provided temporary BAR. If BAR is 0 use a @@ -80,7 +79,6 @@ */ void heci_init(uintptr_t tempbar) { - struct cse_device *cse = car_get_var_ptr(&g_cse); #if defined(__SIMPLE_DEVICE__) pci_devfn_t dev = PCH_DEV_CSE; #else @@ -89,7 +87,7 @@ u8 pcireg; /* Assume it is already initialized, nothing else to do */ - if (cse->sec_bar) + if (g_cse.sec_bar) return; /* Use default pre-ram bar */ @@ -111,7 +109,7 @@ pcireg |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; pci_write_config8(dev, PCI_COMMAND, pcireg); - cse->sec_bar = tempbar; + g_cse.sec_bar = tempbar; } /* Get HECI BAR 0 from PCI configuration space */ @@ -130,20 +128,18 @@ static uint32_t read_bar(uint32_t offset) { - struct cse_device *cse = car_get_var_ptr(&g_cse); /* Reach PCI config space to get BAR in case CAR global not available */ - if (!cse->sec_bar) - cse->sec_bar = get_cse_bar(); - return read32((void *)(cse->sec_bar + offset)); + if (!g_cse.sec_bar) + g_cse.sec_bar = get_cse_bar(); + return read32((void *)(g_cse.sec_bar + offset)); } static void write_bar(uint32_t offset, uint32_t val) { - struct cse_device *cse = car_get_var_ptr(&g_cse); /* Reach PCI config space to get BAR in case CAR global not available */ - if (!cse->sec_bar) - cse->sec_bar = get_cse_bar(); - return write32((void *)(cse->sec_bar + offset), val); + if (!g_cse.sec_bar) + g_cse.sec_bar = get_cse_bar(); + return write32((void *)(g_cse.sec_bar + offset), val); } static uint32_t read_cse_csr(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/33001 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If952ad8129e1fa6e45858cb77ec99c9fec55c4a6 Gerrit-Change-Number: 33001 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/common/cse: Declare g_cse statically
by Arthur Heymans (Code Review) 29 May '19

29 May '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33023 Change subject: soc/intel/common/cse: Declare g_cse statically ...................................................................... soc/intel/common/cse: Declare g_cse statically Change-Id: I91b6ce3b52d987e2fc0f79e550fda2891502bfe8 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/common/block/cse/cse.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/33023/1 diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index 302e6de..e4fc6e4 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -69,7 +69,7 @@ #define MEI_HDR_CSE_ADDR (((1 << 8) - 1) << MEI_HDR_CSE_ADDR_START) -struct cse_device { +static struct cse_device { uintptr_t sec_bar; } g_cse CAR_GLOBAL; -- To view, visit https://review.coreboot.org/c/coreboot/+/33023 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I91b6ce3b52d987e2fc0f79e550fda2891502bfe8 Gerrit-Change-Number: 33023 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: drivers/emulation/qemu_debugcon: Don't use CAR_GLOBAL
by Arthur Heymans (Code Review) 29 May '19

29 May '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33000 Change subject: drivers/emulation/qemu_debugcon: Don't use CAR_GLOBAL ...................................................................... drivers/emulation/qemu_debugcon: Don't use CAR_GLOBAL This platform uses NO_CAR_GLOBAL_MIGRATION. Change-Id: Idc9434e5a1a8bc5ed76a9f80c9a7cfba2fd474c0 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/drivers/emulation/qemu/qemu_debugcon.c 1 file changed, 2 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/33000/1 diff --git a/src/drivers/emulation/qemu/qemu_debugcon.c b/src/drivers/emulation/qemu/qemu_debugcon.c index 3807524..a4715d1 100644 --- a/src/drivers/emulation/qemu/qemu_debugcon.c +++ b/src/drivers/emulation/qemu/qemu_debugcon.c @@ -17,14 +17,13 @@ #include <console/console.h> #include <console/qemu_debugcon.h> #include <arch/io.h> -#include <arch/early_variables.h> -static int qemu_debugcon_detected CAR_GLOBAL; +static int qemu_debugcon_detected; void qemu_debugcon_init(void) { int detected = (inb(CONFIG_CONSOLE_QEMU_DEBUGCON_PORT) == 0xe9); - car_set_var(qemu_debugcon_detected, detected); + qemu_debugcon_detected = detected; printk(BIOS_INFO, "QEMU debugcon %s [port 0x%x]\n", detected ? "detected" : "not found", CONFIG_CONSOLE_QEMU_DEBUGCON_PORT); -- To view, visit https://review.coreboot.org/c/coreboot/+/33000 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idc9434e5a1a8bc5ed76a9f80c9a7cfba2fd474c0 Gerrit-Change-Number: 33000 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/common/gpsi: Don't use CAR_GLOBAL
by Arthur Heymans (Code Review) 29 May '19

29 May '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32999 Change subject: soc/intel/common/gpsi: Don't use CAR_GLOBAL ...................................................................... soc/intel/common/gpsi: Don't use CAR_GLOBAL All platforms using this code have NO_CAR_GLOBAL_MIGRATION. Change-Id: I5dfbc718fd82f0511b0049383e4e93c6f15ee932 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/common/block/gspi/gspi.c 1 file changed, 4 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/32999/1 diff --git a/src/soc/intel/common/block/gspi/gspi.c b/src/soc/intel/common/block/gspi/gspi.c index 81eb7ee..7fd7d0f 100644 --- a/src/soc/intel/common/block/gspi/gspi.c +++ b/src/soc/intel/common/block/gspi/gspi.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ -#include <arch/early_variables.h> #include <device/mmio.h> #include <assert.h> #include <console/console.h> @@ -262,15 +261,13 @@ return cfg[gspi_bus].speed_mhz; } -static uintptr_t gspi_base[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX] CAR_GLOBAL; +static uintptr_t gspi_base[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]; static uintptr_t gspi_get_bus_base_addr(unsigned int gspi_bus) { - uintptr_t *base = car_get_var_ptr(gspi_base); + if (!gspi_base[gspi_bus]) + gspi_base[gspi_bus] = gspi_calc_base_addr(gspi_bus); - if (!base[gspi_bus]) - base[gspi_bus] = gspi_calc_base_addr(gspi_bus); - - return base[gspi_bus]; + return gspi_base[gspi_bus]; } /* Parameters for GSPI controller operation. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/32999 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5dfbc718fd82f0511b0049383e4e93c6f15ee932 Gerrit-Change-Number: 32999 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/quark: Don't use CAR_GLOBAL
by Arthur Heymans (Code Review) 29 May '19

29 May '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32998 Change subject: soc/intel/quark: Don't use CAR_GLOBAL ...................................................................... soc/intel/quark: Don't use CAR_GLOBAL This soc has NO_CAR_GLOBAL_MIGRATION and does not require CAR_GLOBAL and car_get/set_x. Change-Id: I4e2c1c5766e3bcdd4763b42fb925074f7ccd7002 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/quark/romstage/fsp2_0.c M src/soc/intel/quark/romstage/romstage.c M src/soc/intel/quark/storage_test.c 3 files changed, 13 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/32998/1 diff --git a/src/soc/intel/quark/romstage/fsp2_0.c b/src/soc/intel/quark/romstage/fsp2_0.c index e4abcc0..d8daaf9 100644 --- a/src/soc/intel/quark/romstage/fsp2_0.c +++ b/src/soc/intel/quark/romstage/fsp2_0.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <arch/early_variables.h> #include <console/console.h> #include <cbmem.h> #include "../chip.h" @@ -85,20 +84,19 @@ run_postcar_phase(&pcf); } -static struct chipset_power_state power_state CAR_GLOBAL; +static struct chipset_power_state power_state; struct chipset_power_state *get_power_state(void) { - return (struct chipset_power_state *)car_get_var_ptr(&power_state); + return &power_state; } int fill_power_state(void) { - struct chipset_power_state *ps = get_power_state(); - - ps->prev_sleep_state = 0; - printk(BIOS_SPEW, "prev_sleep_state %d\n", ps->prev_sleep_state); - return ps->prev_sleep_state; + power_state.prev_sleep_state = 0; + printk(BIOS_SPEW, "prev_sleep_state %d\n", + power_state.prev_sleep_state); + return power_state.prev_sleep_state; } void platform_fsp_memory_init_params_cb(FSPM_UPD *fspm_upd, uint32_t version) diff --git a/src/soc/intel/quark/romstage/romstage.c b/src/soc/intel/quark/romstage/romstage.c index f2a280e..4ac580e 100644 --- a/src/soc/intel/quark/romstage/romstage.c +++ b/src/soc/intel/quark/romstage/romstage.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ -#include <arch/early_variables.h> #include <cbfs.h> #include <console/console.h> #include <fsp/util.h> diff --git a/src/soc/intel/quark/storage_test.c b/src/soc/intel/quark/storage_test.c index bdf86b1..d79ae7b 100644 --- a/src/soc/intel/quark/storage_test.c +++ b/src/soc/intel/quark/storage_test.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <arch/early_variables.h> #include <device/pci_ops.h> #include <assert.h> #include <cbmem.h> @@ -29,13 +28,13 @@ #include <string.h> #if CONFIG(STORAGE_LOG) -struct log_entry log[LOG_ENTRIES] CAR_GLOBAL; -uint8_t log_index CAR_GLOBAL; -int log_full CAR_GLOBAL; -long log_start_time CAR_GLOBAL; +struct log_entry log[LOG_ENTRIES]; +uint8_t log_index; +int log_full; +long log_start_time; #endif -static uint8_t drivers_storage[256] CAR_GLOBAL; +static uint8_t drivers_storage[256]; #define STORAGE_DEBUG BIOS_DEBUG #define LOG_DEBUG (CONFIG(STORAGE_LOG) ? STORAGE_DEBUG : BIOS_NEVER) @@ -175,7 +174,7 @@ /* Get the structure addresses */ media = NULL; if (ENV_ROMSTAGE) - media = car_get_var_ptr(drivers_storage); + media = drivers_storage; else media = cbmem_find(CBMEM_ID_STORAGE_DATA); sdhci_ctrlr = (void *)(((uintptr_t)(media + 1) + 0x7) & ~7); @@ -255,7 +254,7 @@ sdhci_ctrlr = (void *)(((uintptr_t)(media + 1) + 0x7) & ~7); /* Migrate the data into CBMEM */ - memcpy(media, car_get_var_ptr(drivers_storage), size); + memcpy(media, drivers_storage, size); media->ctrlr = &sdhci_ctrlr->sd_mmc_ctrlr; } -- To view, visit https://review.coreboot.org/c/coreboot/+/32998 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4e2c1c5766e3bcdd4763b42fb925074f7ccd7002 Gerrit-Change-Number: 32998 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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coreboot-gerrit May 2019