coreboot-gerrit May 2019

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Change in ...coreboot[master]: mb/google/poppy/variants/nami: Disable FPMCU for non-fingerprint vari...
by Ivy Jian (Code Review) 29 May '19

29 May '19

Ivy Jian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33017 Change subject: mb/google/poppy/variants/nami: Disable FPMCU for non-fingerprint variants ...................................................................... mb/google/poppy/variants/nami: Disable FPMCU for non-fingerprint variants Even fingerprint device probe failed on non-fingerpint boards,the CRFP driver still register the device that cause the GPE#1 as wake source every time. Override devicetree for non-fingerpirnt variants to avoid unexpected wake event(GPE#1). BUG=b:129650040 BRANCH=firmware-nami-10775.B TEST=Boots to OS and check no GPE#1 wake event from eventlog when S0ix exit. Signed-off-by: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Change-Id: I6fa96e04a34e296889414b96a8c604fc61b8a236 --- M src/mainboard/google/poppy/variants/nami/mainboard.c 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/33017/1 diff --git a/src/mainboard/google/poppy/variants/nami/mainboard.c b/src/mainboard/google/poppy/variants/nami/mainboard.c index dff62c2..cc87136 100644 --- a/src/mainboard/google/poppy/variants/nami/mainboard.c +++ b/src/mainboard/google/poppy/variants/nami/mainboard.c @@ -238,6 +238,7 @@ struct device *root = SA_DEV_ROOT; config_t *cfg = root->chip_info; uint8_t pl2_id = PL2_ID_DEFAULT; + struct device *spi_fpmcu = PCH_DEV_GSPI1; switch (sku_id) { case SKU_0_SONA: @@ -260,6 +261,7 @@ case SKU_3_PANTHEON: case SKU_4_PANTHEON: cfg->usb2_ports[5].enable = 0; + spi_fpmcu->enabled = 0; break; case SKU_0_BARD: case SKU_1_BARD: -- To view, visit https://review.coreboot.org/c/coreboot/+/33017 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6fa96e04a34e296889414b96a8c604fc61b8a236 Gerrit-Change-Number: 33017 Gerrit-PatchSet: 1 Gerrit-Owner: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: nb/intel/nehalem: Call smm_region_start() function
by Arthur Heymans (Code Review) 29 May '19

29 May '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33046 Change subject: nb/intel/nehalem: Call smm_region_start() function ...................................................................... nb/intel/nehalem: Call smm_region_start() function TEST: X201 Boots again. Change-Id: Ia637bd01cd7dc1aecd1a87a739d5243c70419553 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/nehalem/ram_calc.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/33046/1 diff --git a/src/northbridge/intel/nehalem/ram_calc.c b/src/northbridge/intel/nehalem/ram_calc.c index ca821da..f0b848d 100644 --- a/src/northbridge/intel/nehalem/ram_calc.c +++ b/src/northbridge/intel/nehalem/ram_calc.c @@ -35,7 +35,7 @@ u32 northbridge_get_tseg_base(void) { - return (u32)smm_region_start & ~1; + return (u32)smm_region_start() & ~1; } void *cbmem_top(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/33046 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia637bd01cd7dc1aecd1a87a739d5243c70419553 Gerrit-Change-Number: 33046 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: drivers/intel/fsp1_1/raminit.c: Always check FSP HOBs
by Frans Hendriks (Code Review) 29 May '19

29 May '19

Hello Patrick Rudolph, Piotr Król, Huang Jin, York Yang, Lee Leahy, build bot (Jenkins), Michał Żygowski, Patrick Georgi, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29371 to look at the new patch set (#9). Change subject: drivers/intel/fsp1_1/raminit.c: Always check FSP HOBs ...................................................................... drivers/intel/fsp1_1/raminit.c: Always check FSP HOBs Check for FSP HOBs is depending on CONFIG_DISPLAY_HOBS. Use the CONFIG_DISPLAY_HOBS for display HOB info only and always check HOBs. Use BIOS_ERR of printk() for FSP errors. BUG=N/A TEST=Check console output on Facebook FBG1701. Change-Id: I3776fa37866c7ef3aea090842387660c22bbdd4d Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/drivers/intel/fsp1_1/raminit.c M src/drivers/intel/fsp1_1/ramstage.c 2 files changed, 25 insertions(+), 57 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/29371/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/29371 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3776fa37866c7ef3aea090842387660c22bbdd4d Gerrit-Change-Number: 29371 Gerrit-PatchSet: 9 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: York Yang <yyang024(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: drivers/intel/fsp2_0: Fix typo mistake
by Subrata Banik (Code Review) 29 May '19

29 May '19

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33056 Change subject: drivers/intel/fsp2_0: Fix typo mistake ...................................................................... drivers/intel/fsp2_0: Fix typo mistake Change-Id: I90f595d7d789429c8717261c6edb6c756f6c0e1f Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/drivers/intel/fsp2_0/silicon_init.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/33056/1 diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c index e9c29db..302bc0f 100644 --- a/src/drivers/intel/fsp2_0/silicon_init.c +++ b/src/drivers/intel/fsp2_0/silicon_init.c @@ -72,7 +72,7 @@ } printk(BIOS_SPEW, "FspSiliconInit returned 0x%08x\n", status); die_with_post_code(postcode, - "FspSiliconINit returned an error!\n"); + "FspSiliconInit returned an error!\n"); } } -- To view, visit https://review.coreboot.org/c/coreboot/+/33056 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I90f595d7d789429c8717261c6edb6c756f6c0e1f Gerrit-Change-Number: 33056 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: nb/amd/amdfam10/northbridge.c: Remove variable set but not used
by HAOUAS Elyes (Code Review) 29 May '19

29 May '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33054 Change subject: nb/amd/amdfam10/northbridge.c: Remove variable set but not used ...................................................................... nb/amd/amdfam10/northbridge.c: Remove variable set but not used Change-Id: I3ae05338669a6d71e322d5fc0ee4ca2028048ac4 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/amd/amdfam10/northbridge.c 1 file changed, 1 insertion(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/33054/1 diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index db40267..2316c61 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -1690,10 +1690,9 @@ uint8_t fam15h = 0; uint8_t rev_gte_d = 0; - uint32_t family; uint32_t model; - family = model = cpuid_eax(0x80000001); + model = cpuid_eax(0x80000001); model = ((model & 0xf0000) >> 12) | ((model & 0xf0) >> 4); if (is_fam15h()) { -- To view, visit https://review.coreboot.org/c/coreboot/+/33054 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3ae05338669a6d71e322d5fc0ee4ca2028048ac4 Gerrit-Change-Number: 33054 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: src/drivers/intel/fsp1_0: Move PLATFORM_USES_FSP1_0
by Arthur Heymans (Code Review) 29 May '19

29 May '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30791 Change subject: src/drivers/intel/fsp1_0: Move PLATFORM_USES_FSP1_0 ...................................................................... src/drivers/intel/fsp1_0: Move PLATFORM_USES_FSP1_0 This is a better location. Change-Id: Ic1c86c26a66c33760484bb6a86e9763c148a7c96 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/x86/Kconfig M src/drivers/intel/fsp1_0/Kconfig 2 files changed, 9 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/30791/1 diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index 232fe63..608afd7 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -151,13 +151,6 @@ This option informs the MTRR code to use the RdMem and WrMem fields in the fixed MTRR MSRs. -config PLATFORM_USES_FSP1_0 - bool - default n - help - Selected for Intel processors/platform combinations that use the - Intel Firmware Support Package (FSP) 1.0 for initialization. - config MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING def_bool n help diff --git a/src/drivers/intel/fsp1_0/Kconfig b/src/drivers/intel/fsp1_0/Kconfig index c7f6c18..4d1c4df 100644 --- a/src/drivers/intel/fsp1_0/Kconfig +++ b/src/drivers/intel/fsp1_0/Kconfig @@ -13,6 +13,15 @@ ## GNU General Public License for more details. ## +config PLATFORM_USES_FSP1_0 + bool + default n + select CACHE_MRC_SETTINGS + help + Selected for Intel processors/platform combinations that use the + Intel Firmware Support Package (FSP) 1.0 for initialization. + + if PLATFORM_USES_FSP1_0 comment "Intel FSP" -- To view, visit https://review.coreboot.org/c/coreboot/+/30791 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic1c86c26a66c33760484bb6a86e9763c148a7c96 Gerrit-Change-Number: 30791 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: util/xcompile/xcompile: apply -march to clang as well as gcc
by Patrick Georgi (Code Review) 28 May '19

28 May '19

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/32923 ) Change subject: util/xcompile/xcompile: apply -march to clang as well as gcc ...................................................................... util/xcompile/xcompile: apply -march to clang as well as gcc For x64 and x86_32 configurations, apply the -march flag to both GCC and Clang flags. This solves the problem of Clang-compiled coreboot failing due to Clang emitting SSE instructions for code that is executed while SSE is not enabled. This patch takes functionality targeted for GCC configurations and moves it down a few lines, modifying CFLAGS instead of GCC_CFLAGS in order that it applies to both GCC and Clang. This is an alternate patch to CB:32887. Signed-off-by: Alan Green <avg(a)google.com> Change-Id: I6a6a6136b01a64d46f730ed19ebbeaadaf2183df Reviewed-on: https://review.coreboot.org/c/coreboot/+/32923 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M util/xcompile/xcompile 1 file changed, 28 insertions(+), 27 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved Kyösti Mälkki: Looks good to me, but someone else must approve Paul Menzel: Looks good to me, but someone else must approve diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile index 4a29cdd..40356d9 100755 --- a/util/xcompile/xcompile +++ b/util/xcompile/xcompile @@ -227,33 +227,6 @@ GCC_CFLAGS_${TARCH}:=${CFLAGS_GCC} GCC_COMPILER_RT_${TARCH}:=${CC_RT_GCC} GCC_COMPILER_RT_FLAGS_${TARCH}:=${CC_RT_EXTRA_GCC} -EOF - -# Generally the x86 should build for i686 -- no sse/mmx -# instructions since SMM modules are compiled using these -# flags. Note that this doesn't prevent a project using -# xcompile to explicitly specify -mmsse, etc flags. -# The Quark processor doesn't support the instructions -# introduced with the Pentium 6 architecture, so allow it -# to use i586 instead. -if [ "${TARCH}" = "x86_64" ]; then -cat <<EOF - GCC_CFLAGS_${TARCH} += -march=nocona -malign-data=abi -EOF -fi - -if [ "${TARCH}" = "x86_32" ]; then -cat <<EOF - -ifneq (\$(CONFIG_USE_MARCH_586)\$(CONFIG_LP_USE_MARCH_586),) - GCC_CFLAGS_${TARCH} += -march=i586 -else - GCC_CFLAGS_${TARCH} += -march=i686 -endif -EOF -fi - -cat <<EOF # Clang CLANG_CC_${TARCH}:=${CLANG} @@ -265,6 +238,7 @@ CLANG_COMPILER_RT_${TARCH}:=${CC_RT_CLANG} CLANG_COMPILER_RT_FLAGS_${TARCH}:=${CC_RT_EXTRA_CLANG} +# GCC/Clang Common ifeq (\$(CONFIG_COMPILER_GCC)\$(CONFIG_LP_COMPILER_GCC),y) CC_${TARCH}:=\$(GCC_CC_${TARCH}) CFLAGS_${TARCH}:=\$(GCC_CFLAGS_${TARCH}) @@ -276,6 +250,33 @@ COMPILER_RT_${TARCH}:=\$(CLANG_COMPILER_RT_${TARCH}) COMPILER_RT_FLAGS_${TARCH}:=\$(CLANG_COMPILER_RT_FLAGS_${TARCH}) endif +EOF + +# Generally the x86 should build for i686 -- no sse/mmx +# instructions since SMM modules are compiled using these +# flags. Note that this doesn't prevent a project using +# xcompile to explicitly specify -mmsse, etc flags. +# The Quark processor doesn't support the instructions +# introduced with the Pentium 6 architecture, so allow it +# to use i586 instead. +if [ "${TARCH}" = "x86_64" ]; then +cat <<EOF + CFLAGS_${TARCH} += -march=nocona -malign-data=abi +EOF +fi + +if [ "${TARCH}" = "x86_32" ]; then +cat <<EOF + +ifneq (\$(CONFIG_USE_MARCH_586)\$(CONFIG_LP_USE_MARCH_586),) + CFLAGS_${TARCH} += -march=i586 +else + CFLAGS_${TARCH} += -march=i686 +endif +EOF +fi + +cat <<EOF CPP_${TARCH}:=${GCCPREFIX}cpp AS_${TARCH}:=${GCCPREFIX}as ${ASFLAGS} -- To view, visit https://review.coreboot.org/c/coreboot/+/32923 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6a6a6136b01a64d46f730ed19ebbeaadaf2183df Gerrit-Change-Number: 32923 Gerrit-PatchSet: 4 Gerrit-Owner: Alan Green <avg(a)google.com> Gerrit-Reviewer: Alan Green <avg(a)google.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: mb/google/sarien: Modify SSD power sequence
by EricR Lai (Code Review) 28 May '19

28 May '19

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33029 Change subject: mb/google/sarien: Modify SSD power sequence ...................................................................... mb/google/sarien: Modify SSD power sequence Due to we turn off SSD power in S5. CB:32952 Based on M2 spec we have to turn on SSD power before RST assert. BUG=b:133389422 TEST=verify warm boot and cold boot are boot successfully. Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: I5b78bab4be675bbb8795361bcfa5af52cb54bb1e --- M src/mainboard/google/sarien/variants/arcada/gpio.c M src/mainboard/google/sarien/variants/sarien/gpio.c 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/33029/1 diff --git a/src/mainboard/google/sarien/variants/arcada/gpio.c b/src/mainboard/google/sarien/variants/arcada/gpio.c index ea0601b..ff0240c 100644 --- a/src/mainboard/google/sarien/variants/arcada/gpio.c +++ b/src/mainboard/google/sarien/variants/arcada/gpio.c @@ -211,7 +211,6 @@ /* I2C4_SCL */ PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), /* I2C_SCL_H1 */ /* I2C5_SDA */ PAD_NC(GPP_H10, NONE), /* ISH_I2C2_SDA */ /* I2C5_SCL */ PAD_NC(GPP_H11, NONE), /* ISH_I2C2_SCL */ -/* M2_SKT2_CFG1 */ PAD_CFG_GPO(GPP_H13, 1, DEEP), /* M.2 SSD D3 cold */ /* M2_SKT2_CFG2 */ PAD_NC(GPP_H14, NONE), /* M2_SKT2_CFG3 */ PAD_CFG_GPO(GPP_H15, 1, DEEP), /* BT_RADIO_DIS# */ /* DDPF_CTRLCLK */ PAD_NC(GPP_H16, NONE), @@ -239,6 +238,7 @@ /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { +/* M2_SKT2_CFG1 */ PAD_CFG_GPO(GPP_H13, 1, DEEP), /* M.2 SSD D3 cold */ /* SSD RESET pin will stay low first */ /* M2_SKT2_CFG0 */ PAD_CFG_GPO(GPP_H12, 0, DEEP), /* D3 cold RST */ /* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVOTX_UART */ diff --git a/src/mainboard/google/sarien/variants/sarien/gpio.c b/src/mainboard/google/sarien/variants/sarien/gpio.c index ec3b44d..78db12e 100644 --- a/src/mainboard/google/sarien/variants/sarien/gpio.c +++ b/src/mainboard/google/sarien/variants/sarien/gpio.c @@ -197,7 +197,6 @@ /* I2C4_SCL */ PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), /* I2C_SCL_H1 */ /* I2C5_SDA */ PAD_NC(GPP_H10, NONE), /* I2C5_SCL */ PAD_NC(GPP_H11, NONE), -/* M2_SKT2_CFG1 */ PAD_CFG_GPO(GPP_H13, 1, DEEP), /* M.2 SSD D3 cold */ /* M2_SKT2_CFG2 */ PAD_NC(GPP_H14, NONE), /* M2_SKT2_CFG3 */ PAD_CFG_GPO(GPP_H15, 1, DEEP), /* BT_RADIO_DIS# */ /* DDPF_CTRLCLK */ PAD_NC(GPP_H16, NONE), @@ -224,6 +223,7 @@ /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { +/* M2_SKT2_CFG1 */ PAD_CFG_GPO(GPP_H13, 1, DEEP), /* M.2 SSD D3 cold */ /* SUSWARN# */ PAD_CFG_GPO(GPP_A13, 0, DEEP), /* Card reader D3 cold */ /* SUSACK# */ PAD_CFG_GPO(GPP_A15, 0, DEEP), /* Card reader D3 cold */ /* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVOTX_UART */ -- To view, visit https://review.coreboot.org/c/coreboot/+/33029 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b78bab4be675bbb8795361bcfa5af52cb54bb1e Gerrit-Change-Number: 33029 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/sarien: Fix SSD power leakage in S5
by EricR Lai (Code Review) 28 May '19

28 May '19

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32952 Change subject: mb/google/sarien: Fix SSD power leakage in S5 ...................................................................... mb/google/sarien: Fix SSD power leakage in S5 Turn off SSD power in S5. BUG=b:133389422 TEST=measure H13 is low in S5 Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: I40b5381cac33b0eac962a7730ee5c57e60e6d375 --- M src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl M src/mainboard/google/sarien/variants/sarien/include/variant/acpi/mainboard.asl 2 files changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/32952/1 diff --git a/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl b/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl index 41121d2..52e96af 100644 --- a/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl @@ -15,6 +15,7 @@ #define CAM_EN GPP_B11 /* Active low */ #define TS_PD GPP_E7 +#define SSD_EN GPP_H13 /* Method called from LPIT prior to enter s0ix state */ Method (MS0X, 1) @@ -35,6 +36,9 @@ /* Clear touch screen pd pin to avoid leakage */ \_SB.PCI0.CTXS (TS_PD) + + /* Clear SSD EN pin to avoid leakage */ + \_SB.PCI0.CTXS (SSD_EN) } /* Method called from _WAK prior to wakeup */ diff --git a/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/mainboard.asl b/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/mainboard.asl index 41121d2..52e96af 100644 --- a/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/mainboard.asl @@ -15,6 +15,7 @@ #define CAM_EN GPP_B11 /* Active low */ #define TS_PD GPP_E7 +#define SSD_EN GPP_H13 /* Method called from LPIT prior to enter s0ix state */ Method (MS0X, 1) @@ -35,6 +36,9 @@ /* Clear touch screen pd pin to avoid leakage */ \_SB.PCI0.CTXS (TS_PD) + + /* Clear SSD EN pin to avoid leakage */ + \_SB.PCI0.CTXS (SSD_EN) } /* Method called from _WAK prior to wakeup */ -- To view, visit https://review.coreboot.org/c/coreboot/+/32952 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I40b5381cac33b0eac962a7730ee5c57e60e6d375 Gerrit-Change-Number: 32952 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: cpu/intel/sandybridge: Add `hyper_threading` option
by Nico Huber (Code Review) 28 May '19

28 May '19

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29669 ) Change subject: cpu/intel/sandybridge: Add `hyper_threading` option ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/#/c/29669/4/src/cpu/intel/model_206ax/bootblock… File src/cpu/intel/model_206ax/bootblock.c: https://review.coreboot.org/#/c/29669/4/src/cpu/intel/model_206ax/bootblock… PS4, Line 106: read_option(hyper_threading, 1); > Why not get_option(&ht_requested, "hyper_threading")? Still a romcc bootblock, afaik. -- To view, visit https://review.coreboot.org/c/coreboot/+/29669 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2b73e32ff5af8ea64a47e8aa706e27648aaf0993 Gerrit-Change-Number: 29669 Gerrit-PatchSet: 4 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-CC: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Comment-Date: Tue, 28 May 2019 18:57:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Evgeny Zinoviev <me(a)ch1p.com> Gerrit-MessageType: comment

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coreboot-gerrit May 2019