HAOUAS Elyes has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/29704 )
Change subject: device/dram/ddr2: Add TCK_1066MHZ to 'normalize_tck' function
......................................................................
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HAOUAS Elyes has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/29705 )
Change subject: include/spd_ddr2: Remove common SPD byte 2
......................................................................
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Nitheesh Sekar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29967 )
Change subject: qclib: Add qclib support with interface tables
......................................................................
Patch Set 26:
Hi Julius,
I have rebased the gerrits to add few new changes.
Will address the comments and make a new upstream post.
Thanks,
Nitheesh Sekar
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build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29981 )
Change subject: TEMP: NOT FOR REVIEW: qcs405: Add bl31 stage and elf
......................................................................
Patch Set 25:
(1 comment)
https://review.coreboot.org/#/c/29981/25/src/soc/qualcomm/qcs405/soc.c
File src/soc/qualcomm/qcs405/soc.c:
https://review.coreboot.org/#/c/29981/25/src/soc/qualcomm/qcs405/soc.c@26
PS25, Line 26: bootmem_add_range((uintptr_t)_dram_reserved, _dram_reserved_size, BM_MEM_BL31);
line over 80 characters
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Gerrit-Owner: Nitheesh Sekar <nsekar(a)codeaurora.org>
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Gerrit-Comment-Date: Tue, 28 May 2019 10:44:39 +0000
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Hello Julius Werner, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/29981
to look at the new patch set (#25).
Change subject: TEMP: NOT FOR REVIEW: qcs405: Add bl31 stage and elf
......................................................................
TEMP: NOT FOR REVIEW: qcs405: Add bl31 stage and elf
Change-Id: I967c0b78a3561574609bf8332a22838c85e43429
Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org>
Signed-off-by: Sricharan R <sricharan(a)codeaurora.org>
---
M src/soc/qualcomm/qcs405/Kconfig
M src/soc/qualcomm/qcs405/Makefile.inc
A src/soc/qualcomm/qcs405/bl31_plat_params.c
A src/soc/qualcomm/qcs405/include/soc/bl31_plat_params.h
M src/soc/qualcomm/qcs405/soc.c
5 files changed, 90 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/29981/25
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Gerrit-Change-Id: I967c0b78a3561574609bf8332a22838c85e43429
Gerrit-Change-Number: 29981
Gerrit-PatchSet: 25
Gerrit-Owner: Nitheesh Sekar <nsekar(a)codeaurora.org>
Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org>
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Hello build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/29958
to look at the new patch set (#25).
Change subject: TEMP: NOT FOR REVIEW: qcs405: Combine BB with QC-Sec for ROM boot
......................................................................
TEMP: NOT FOR REVIEW: qcs405: Combine BB with QC-Sec for ROM boot
TEST=build & run
Change-Id: I2428fd067c0216d9cf6a63e218d1792788317db0
Signed-off-by: Sricharan R <sricharan(a)codeaurora.org>
Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org>
---
M src/soc/qualcomm/qcs405/Makefile.inc
1 file changed, 25 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/29958/25
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Gerrit-Owner: Nitheesh Sekar <nsekar(a)codeaurora.org>
Gerrit-Reviewer: Martin Roth <martinroth(a)google.com>
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Hello Julius Werner, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/29970
to look at the new patch set (#26).
Change subject: TEMP: NOT FOR REVIEW: QCS405: Added RPM support
......................................................................
TEMP: NOT FOR REVIEW: QCS405: Added RPM support
This patch adds support to read RPM image from
3rdparty/blobs and load it. It takes RPM out of reset.
Note that, clock_reset_rpm function to touch the
GCC registers actually should reside in clock.c,
but for now keeping it here till clock patches
are posted.
Change-Id: I17f491f0a4bd0dce7522b7e80e1bac97ec18b945
Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org>
Signed-off-by: Sricharan R <sricharan(a)codeaurora.org>
---
M src/soc/qualcomm/qcs405/Makefile.inc
M src/soc/qualcomm/qcs405/include/soc/memlayout.ld
A src/soc/qualcomm/qcs405/include/soc/rpm.h
M src/soc/qualcomm/qcs405/include/soc/symbols.h
M src/soc/qualcomm/qcs405/mmu.c
A src/soc/qualcomm/qcs405/rpm_load_reset.c
M src/soc/qualcomm/qcs405/soc.c
7 files changed, 106 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/29970/26
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Gerrit-Change-Number: 29970
Gerrit-PatchSet: 26
Gerrit-Owner: Nitheesh Sekar <nsekar(a)codeaurora.org>
Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org>
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Gerrit-MessageType: newpatchset
Hello Julius Werner, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/29967
to look at the new patch set (#26).
Change subject: qclib: Add qclib support with interface tables
......................................................................
qclib: Add qclib support with interface tables
Add to load and execute qclib blob to configure pmic,
clocks and ddr.This also loads the qcsdi, cdt blob.
Added support for interface tables to read ddr info
from qclib and do ddr one time training based on it.
Change-Id: I534af71163d034ea04420dda6a94ce31b08c8a07
Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org>
Signed-off-by: Sricharan R <sricharan(a)codeaurora.org>
---
M src/mainboard/google/mistral/Makefile.inc
M src/mainboard/google/mistral/romstage.c
M src/soc/qualcomm/common/qclib.c
M src/soc/qualcomm/qcs405/Makefile.inc
M src/soc/qualcomm/qcs405/include/soc/memlayout.ld
A src/soc/qualcomm/qcs405/include/soc/qclib.h
M src/soc/qualcomm/qcs405/include/soc/symbols.h
M src/soc/qualcomm/qcs405/mmu.c
A src/soc/qualcomm/qcs405/soc_blob_load.c
9 files changed, 149 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/29967/26
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Gerrit-Change-Number: 29967
Gerrit-PatchSet: 26
Gerrit-Owner: Nitheesh Sekar <nsekar(a)codeaurora.org>
Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org>
Gerrit-Reviewer: Martin Roth <martinroth(a)google.com>
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Gerrit-CC: mturney mturney <mturney(a)codeaurora.org>
Gerrit-MessageType: newpatchset
Hello build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/29968
to look at the new patch set (#25).
Change subject: qcs405: Enable SPI-NOR
......................................................................
qcs405: Enable SPI-NOR
Enable support for WINBOND spi-nor flash.
Change-Id: I340eb3bf77b25fe3502d4b29ef4bf7c06b282c02
Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org>
---
M src/mainboard/google/mistral/Kconfig
1 file changed, 2 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/29968/25
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