coreboot-gerrit May 2019

coreboot-gerrit@coreboot.org

1 participants
1485 discussions

Change in ...coreboot[master]: cpu/intel/sandybridge: Add `hyper_threading` option
by Evgeny Zinoviev (Code Review) 28 May '19

28 May '19

1 0

Change in ...coreboot[master]: cpu/intel/sandybridge: Add `hyper_threading` option
by Evgeny Zinoviev (Code Review) 28 May '19

28 May '19

Evgeny Zinoviev has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29669 ) Change subject: cpu/intel/sandybridge: Add `hyper_threading` option ...................................................................... Patch Set 4: The ACPI problems were caused by `get_cores_per_package()` function. It was using CPUID 0Bh function, that returns number of logical processes of requested level to EBX. According to Intel's manual, this value is not changed if HT was disabled. int totalcores = dev_count_cpu(); // this was 2 int cores_per_package = get_cores_per_package(); // this was 4, when it had to be 2 int numcpus = totalcores/cores_per_package; // so this was 0 I updated the `get_cores_per_package` function, now it uses MSR 0x35 instead of CPUID. I hope that doesn't break anything. Somebody please review. I will then fix build problems, which are caused by non-existent CMOS option for some boards or similar minor stuff. Latest PS is tested on X220. -- To view, visit https://review.coreboot.org/c/coreboot/+/29669 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2b73e32ff5af8ea64a47e8aa706e27648aaf0993 Gerrit-Change-Number: 29669 Gerrit-PatchSet: 4 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-CC: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Comment-Date: Tue, 28 May 2019 17:49:32 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: cpu/intel/sandybridge: Add `hyper_threading` option
by Evgeny Zinoviev (Code Review) 28 May '19

28 May '19

Evgeny Zinoviev has uploaded a new patch set (#4) to the change originally created by Nico Huber. ( https://review.coreboot.org/c/coreboot/+/29669 ) Change subject: cpu/intel/sandybridge: Add `hyper_threading` option ...................................................................... cpu/intel/sandybridge: Add `hyper_threading` option More and more people request an option to disable HT. To implement that we have to toggle a bit in a `soft reset` register in the PCH that can override certain default settings of the CPU when it comes out of reset. The `soft reset` register is already used for other settings. So we have to take care that all settings are gathered before we issue the reset. Note, the current code using `soft reset` for flex ratio selection seems incomplete. Change-Id: I2b73e32ff5af8ea64a47e8aa706e27648aaf0993 Signed-off-by: Nico Huber <nico.h(a)gmx.de> Signed-off-by: Evgeny Zinoviev <me(a)ch1p.io> --- M src/cpu/intel/model_206ax/acpi.c M src/cpu/intel/model_206ax/bootblock.c M src/mainboard/hp/2570p/cmos.layout M src/mainboard/hp/2760p/cmos.layout M src/mainboard/hp/8460p/cmos.layout M src/mainboard/hp/8470p/cmos.layout M src/mainboard/hp/8770w/cmos.layout M src/mainboard/hp/compaq_8200_elite_sff/cmos.layout M src/mainboard/hp/folio_9470m/cmos.layout M src/mainboard/hp/revolve_810_g1/cmos.layout M src/mainboard/lenovo/l520/cmos.layout M src/mainboard/lenovo/t420/cmos.layout M src/mainboard/lenovo/t420s/cmos.layout M src/mainboard/lenovo/t430/cmos.layout M src/mainboard/lenovo/t430s/cmos.layout M src/mainboard/lenovo/t520/cmos.layout M src/mainboard/lenovo/t530/cmos.layout M src/mainboard/lenovo/x131e/cmos.layout M src/mainboard/lenovo/x1_carbon_gen1/cmos.layout M src/mainboard/lenovo/x220/cmos.layout M src/mainboard/lenovo/x230/cmos.layout M src/southbridge/intel/bd82x6x/pch.h 22 files changed, 90 insertions(+), 47 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/29669/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/29669 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2b73e32ff5af8ea64a47e8aa706e27648aaf0993 Gerrit-Change-Number: 29669 Gerrit-PatchSet: 4 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-CC: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-MessageType: newpatchset

1 0

Change in ...coreboot[master]: mb/google/sarien: Send post code to the EC in ROM stage
by EricR Lai (Code Review) 28 May '19

28 May '19

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33030 Change subject: mb/google/sarien: Send post code to the EC in ROM stage ...................................................................... mb/google/sarien: Send post code to the EC in ROM stage Use the mainboard post code hook to inform the wilco EC driver of the ROM stage. BUG=b:124401932,b:133466714,b:133600566 BRANCH=sarien TEST=Remove DIMM module, confirm diagnostic LED pattern for memory failure (2 amber, 4 white). Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: Ic03827e148b8c05e6b97f73ad36964832942c09a --- M src/mainboard/google/sarien/ramstage.c M src/mainboard/google/sarien/romstage.c 2 files changed, 11 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/33030/1 diff --git a/src/mainboard/google/sarien/ramstage.c b/src/mainboard/google/sarien/ramstage.c index e246419..804d35a 100644 --- a/src/mainboard/google/sarien/ramstage.c +++ b/src/mainboard/google/sarien/ramstage.c @@ -70,10 +70,12 @@ cnl_configure_pads(gpio_table, num_gpios); } +#if ENV_RAMSTAGE void mainboard_post(uint8_t value) { wilco_ec_save_post_code(value); } +#endif static void mainboard_enable(struct device *dev) { diff --git a/src/mainboard/google/sarien/romstage.c b/src/mainboard/google/sarien/romstage.c index 20eee7f..0b0c32a 100644 --- a/src/mainboard/google/sarien/romstage.c +++ b/src/mainboard/google/sarien/romstage.c @@ -16,6 +16,8 @@ #include <ec/google/wilco/romstage.h> #include <soc/cnl_memcfg_init.h> #include <soc/romstage.h> +#include <ec/google/wilco/commands.h> +#include <console/console.h> static const struct cnl_mb_cfg memcfg = { /* Access memory info through SMBUS. */ @@ -55,6 +57,13 @@ .vref_ca_config = 2, }; +#if ENV_ROMSTAGE +void mainboard_post(uint8_t value) +{ + wilco_ec_save_post_code(value); +} +#endif + void mainboard_memory_init_params(FSPM_UPD *memupd) { wilco_ec_romstage_init(); -- To view, visit https://review.coreboot.org/c/coreboot/+/33030 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic03827e148b8c05e6b97f73ad36964832942c09a Gerrit-Change-Number: 33030 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

3 7

Change in ...coreboot[master]: cpu/intel/sandybridge: Add `hyper_threading` option
by Evgeny Zinoviev (Code Review) 28 May '19

28 May '19

Evgeny Zinoviev has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29669 ) Change subject: cpu/intel/sandybridge: Add `hyper_threading` option ...................................................................... Patch Set 3: [ 0.328910] ACPI Error: AE_NOT_FOUND, While resolving a named reference package element - \_PR_.CP00 (20190215/dspkginit-440) [ 0.329023] ACPI Error: AE_NOT_FOUND, While resolving a named reference package element - \_PR_.CP01 (20190215/dspkginit-440) [ 0.329134] ACPI Error: AE_NOT_FOUND, While resolving a named reference package element - \_PR_.CP02 (20190215/dspkginit-440) [ 0.329247] ACPI Error: AE_NOT_FOUND, While resolving a named reference package element - \_PR_.CP03 (20190215/dspkginit-440) [ 0.928328] ACPI BIOS Error (bug): Could not resolve symbol [\_PR.CP00], AE_NOT_FOUND (20190215/psargs-330) [ 0.928441] ACPI Error: Aborting method \_PR.CNOT due to previous error (AE_NOT_FOUND) (20190215/psparse-531) [ 0.928561] ACPI Error: Aborting method \PNOT due to previous error (AE_NOT_FOUND) (20190215/psparse-531) [ 0.928671] ACPI Error: Aborting method \_SB.PCI0.LPCB.EC.AC._PSR due to previous error (AE_NOT_FOUND) (20190215/psparse-531) [ 0.928786] ACPI Error: AE_NOT_FOUND, Error reading AC Adapter state (20190215/ac-129) Need to fix this first. -- To view, visit https://review.coreboot.org/c/coreboot/+/29669 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2b73e32ff5af8ea64a47e8aa706e27648aaf0993 Gerrit-Change-Number: 29669 Gerrit-PatchSet: 3 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-CC: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Comment-Date: Tue, 28 May 2019 13:21:05 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: cpu/intel/sandybridge: Add `hyper_threading` option
by Evgeny Zinoviev (Code Review) 28 May '19

28 May '19

1 0

Change in ...coreboot[master]: cpu/intel/sandybridge: Add `hyper_threading` option
by Evgeny Zinoviev (Code Review) 28 May '19

28 May '19

1 0

Change in ...coreboot[master]: cpu/intel/sandybridge: Add `hyper_threading` option
by Evgeny Zinoviev (Code Review) 28 May '19

28 May '19

Evgeny Zinoviev has uploaded a new patch set (#3) to the change originally created by Nico Huber. ( https://review.coreboot.org/c/coreboot/+/29669 ) Change subject: cpu/intel/sandybridge: Add `hyper_threading` option ...................................................................... cpu/intel/sandybridge: Add `hyper_threading` option More and more people request an option to disable HT. To implement that we have to toggle a bit in a `soft reset` register in the PCH that can override certain default settings of the CPU when it comes out of reset. The `soft reset` register is already used for other settings. So we have to take care that all settings are gathered before we issue the reset. Note, the current code using `soft reset` for flex ratio selection seems incomplete. Change-Id: I2b73e32ff5af8ea64a47e8aa706e27648aaf0993 Signed-off-by: Nico Huber <nico.h(a)gmx.de> Signed-off-by: Evgeny Zinoviev <me(a)ch1p.io> --- M src/cpu/intel/model_206ax/bootblock.c M src/mainboard/hp/2570p/cmos.default M src/mainboard/hp/2570p/cmos.layout M src/mainboard/hp/2760p/cmos.default M src/mainboard/hp/2760p/cmos.layout M src/mainboard/hp/8460p/cmos.default M src/mainboard/hp/8460p/cmos.layout M src/mainboard/hp/8470p/cmos.default M src/mainboard/hp/8470p/cmos.layout M src/mainboard/hp/8770w/cmos.default M src/mainboard/hp/8770w/cmos.layout M src/mainboard/hp/compaq_8200_elite_sff/cmos.default M src/mainboard/hp/compaq_8200_elite_sff/cmos.layout M src/mainboard/hp/folio_9470m/cmos.default M src/mainboard/hp/folio_9470m/cmos.layout M src/mainboard/hp/revolve_810_g1/cmos.default M src/mainboard/hp/revolve_810_g1/cmos.layout M src/mainboard/lenovo/l520/cmos.default M src/mainboard/lenovo/l520/cmos.layout M src/mainboard/lenovo/t420/cmos.default M src/mainboard/lenovo/t420/cmos.layout M src/mainboard/lenovo/t420s/cmos.default M src/mainboard/lenovo/t420s/cmos.layout M src/mainboard/lenovo/t430/cmos.default M src/mainboard/lenovo/t430/cmos.layout M src/mainboard/lenovo/t430s/cmos.default M src/mainboard/lenovo/t430s/cmos.layout M src/mainboard/lenovo/t520/cmos.default M src/mainboard/lenovo/t520/cmos.layout M src/mainboard/lenovo/t530/cmos.layout M src/mainboard/lenovo/x131e/cmos.default M src/mainboard/lenovo/x131e/cmos.layout M src/mainboard/lenovo/x1_carbon_gen1/cmos.default M src/mainboard/lenovo/x1_carbon_gen1/cmos.layout M src/mainboard/lenovo/x220/cmos.default M src/mainboard/lenovo/x220/cmos.layout M src/mainboard/lenovo/x230/cmos.default M src/mainboard/lenovo/x230/cmos.layout M src/southbridge/intel/bd82x6x/pch.h 39 files changed, 103 insertions(+), 37 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/29669/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/29669 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2b73e32ff5af8ea64a47e8aa706e27648aaf0993 Gerrit-Change-Number: 29669 Gerrit-PatchSet: 3 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-CC: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-MessageType: newpatchset

1 0

Change in ...coreboot[master]: drivers/intel/fsp1_1/raminit.c: Make check FSP HOBs independent of CO...
by Frans Hendriks (Code Review) 28 May '19

28 May '19

Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29371 ) Change subject: drivers/intel/fsp1_1/raminit.c: Make check FSP HOBs independent of CONFIG_DISPLAY_HOBS ...................................................................... Patch Set 8: (3 comments) https://review.coreboot.org/#/c/29371/3/src/drivers/intel/fsp1_1/raminit.c File src/drivers/intel/fsp1_1/raminit.c: https://review.coreboot.org/#/c/29371/3/src/drivers/intel/fsp1_1/raminit.c@… PS3, Line 209: printk(BIOS_DEBUG, > These prints could be moved to the print_hob_type_structure function possibly? It is kind of display […] Done https://review.coreboot.org/#/c/29371/3/src/drivers/intel/fsp1_1/raminit.c@… PS3, Line 224: printk(BIOS_DEBUG, > Let's print only an error message in case of missing HOB. […] Done https://review.coreboot.org/#/c/29371/3/src/drivers/intel/fsp1_1/raminit.c@… PS3, Line 229: printk(BIOS_DEBUG, > These prints should be moved too. The check for missing HOB is done earlier. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/29371 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3776fa37866c7ef3aea090842387660c22bbdd4d Gerrit-Change-Number: 29371 Gerrit-PatchSet: 8 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: York Yang <yyang024(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 28 May 2019 12:48:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: src/arch/x86: Add automatic type41 entry creation
by Christian Walter (Code Review) 28 May '19

28 May '19

Christian Walter has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32910 Change subject: src/arch/x86: Add automatic type41 entry creation ...................................................................... src/arch/x86: Add automatic type41 entry creation SMBIOS Type41 Emtries will be automatically created. Change-Id: Idcb3532a5c05666d6613af4f303df85f4f1f6e97 Signed-off-by: Christian Walter <christian.walter(a)9elements.com> --- M src/arch/x86/smbios.c M src/include/device/pci_ids.h 2 files changed, 93 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/32910/1 diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index d389314..3d62614 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -30,6 +30,8 @@ #include <memory_info.h> #include <spd.h> #include <cbmem.h> +#include <device/pci_ids.h> +#include <device/pci_def.h> #if CONFIG(CHROMEOS) #include <vendorcode/google/chromeos/gnvs.h> #endif @@ -50,6 +52,67 @@ return -ret; } +static const char *smbios_get_name_from_type(u8 device_type) +{ + switch (device_type) { + case SMBIOS_DEVICE_TYPE_VIDEO: + return "Video Controller"; + case SMBIOS_DEVICE_TYPE_ETHERNET: + case SMBIOS_DEVICE_TYPE_TOKEN_RING: + return "Ethernet Controller"; + case SMBIOS_DEVICE_TYPE_SOUND: + return "Sound Controller"; + case SMBIOS_DEVICE_TYPE_PATA: + case SMBIOS_DEVICE_TYPE_SAS: + case SMBIOS_DEVICE_TYPE_SATA: + case SMBIOS_DEVICE_TYPE_SCSI: + return "Memory Controller"; + default: + return "Unknown"; + } + + return "Unknown"; +} + +/* Get the device type from the dev struct */ +static u8 smbios_get_device_type_from_dev(struct device *dev) +{ + u16 pci_basesubclass = (dev->class >> 8) & 0xFFFF; + + switch (pci_basesubclass) { + case PCI_CLASS_NOT_DEFINED: + return SMBIOS_DEVICE_TYPE_OTHER; + case PCI_CLASS_DISPLAY_VGA: + case PCI_CLASS_DISPLAY_XGA: + case PCI_CLASS_DISPLAY_3D: + case PCI_CLASS_DISPLAY_OTHER: + return SMBIOS_DEVICE_TYPE_VIDEO; + case PCI_CLASS_STORAGE_SCSI: + return SMBIOS_DEVICE_TYPE_SCSI; + case PCI_CLASS_NETWORK_ETHERNET: + return SMBIOS_DEVICE_TYPE_ETHERNET; + case PCI_CLASS_NETWORK_TOKEN_RING: + return SMBIOS_DEVICE_TYPE_TOKEN_RING; + case PCI_CLASS_MULTIMEDIA_VIDEO: + case PCI_CLASS_MULTIMEDIA_AUDIO: + case PCI_CLASS_MULTIMEDIA_PHONE: + case PCI_CLASS_MULTIMEDIA_OTHER: + return SMBIOS_DEVICE_TYPE_SOUND; + case PCI_CLASS_STORAGE_ATA: + return SMBIOS_DEVICE_TYPE_PATA; + case PCI_CLASS_STORAGE_SATA: + return SMBIOS_DEVICE_TYPE_SATA; + case PCI_CLASS_STORAGE_SAS: + return SMBIOS_DEVICE_TYPE_SAS; + default: + return SMBIOS_DEVICE_TYPE_UNKNOWN; + break; + } + + return SMBIOS_DEVICE_TYPE_UNKNOWN; // safety first + +} + int smbios_add_string(u8 *start, const char *str) { @@ -999,6 +1062,33 @@ return len; } +/* Generate Type41 entries from devicetree */ +static int smbios_walk_device_tree_type41(struct device *dev, int *handle, + unsigned long *current) +{ + static u8 type41_instance_cnt = 0; + + if (dev->path.type != DEVICE_PATH_PCI) + return 0; + + u8 device_type = smbios_get_device_type_from_dev(dev); + + if (device_type == SMBIOS_DEVICE_TYPE_OTHER || + device_type == SMBIOS_DEVICE_TYPE_UNKNOWN) + return 0; + + const char *name = smbios_get_name_from_type(device_type); + + return smbios_write_type41(current, handle, + name, // name + type41_instance_cnt++, // instance + 0, // segment + dev->bus->secondary, //bus + PCI_SLOT(dev->path.pci.devfn), //device + PCI_FUNC(dev->path.pci.devfn), //func + device_type); +} + /* Generate Type9 entries from devicetree */ static int smbios_walk_device_tree_type9(struct device *dev, int *handle, unsigned long *current) @@ -1062,6 +1152,7 @@ len += dev->ops->get_smbios_data(dev, handle, current); } len += smbios_walk_device_tree_type9(dev, handle, current); + len += smbios_walk_device_tree_type41(dev, handle, current); } return len; } diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 6453951..bd98e91 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -18,6 +18,7 @@ #define PCI_CLASS_STORAGE_FLOPPY 0x0102 #define PCI_CLASS_STORAGE_IPI 0x0103 #define PCI_CLASS_STORAGE_RAID 0x0104 +#define PCI_CLASS_STORAGE_ATA 0x0105 #define PCI_CLASS_STORAGE_SATA 0x0106 #define PCI_CLASS_STORAGE_OTHER 0x0180 @@ -3081,6 +3082,7 @@ #define PCI_DEVICE_ID_INTEL_KBL_ID_Y 0x590c #define PCI_DEVICE_ID_INTEL_KBL_ID_H 0x5910 #define PCI_DEVICE_ID_INTEL_KBL_U_R 0x5914 +#define PCI_DEVICE_ID_INTEL_KBL_ID_DT_2 0x5918 #define PCI_DEVICE_ID_INTEL_KBL_ID_DT 0x591f #define PCI_DEVICE_ID_INTEL_CNL_ID_U 0x5A04 #define PCI_DEVICE_ID_INTEL_CNL_ID_Y 0x5A02 -- To view, visit https://review.coreboot.org/c/coreboot/+/32910 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idcb3532a5c05666d6613af4f303df85f4f1f6e97 Gerrit-Change-Number: 32910 Gerrit-PatchSet: 1 Gerrit-Owner: Christian Walter <christian.walter(a)9elements.com> Gerrit-MessageType: newchange

4 19

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit May 2019