coreboot-gerrit May 2019

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Change in ...coreboot[master]: soc/rockchip/rk3288: Disable bootblock console
by Patrick Georgi (Code Review) 30 May '19

30 May '19

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33068 Change subject: soc/rockchip/rk3288: Disable bootblock console ...................................................................... soc/rockchip/rk3288: Disable bootblock console Bootblock space is tight on this SoC and recent changes increased it ever so slightly to make this a problem. Since the bootblock is well-tested, we can get by without console. Change-Id: I7496a3e313b2c6ee6fb3c4671eac64376d84e0dc Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M src/soc/rockchip/rk3288/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/33068/1 diff --git a/src/soc/rockchip/rk3288/Kconfig b/src/soc/rockchip/rk3288/Kconfig index 38d8752..f845f07 100644 --- a/src/soc/rockchip/rk3288/Kconfig +++ b/src/soc/rockchip/rk3288/Kconfig @@ -30,6 +30,7 @@ select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_FORCE_NATIVE_VGA_INIT select HAVE_LINEAR_FRAMEBUFFER + select NO_BOOTBLOCK_CONSOLE if SOC_ROCKCHIP_RK3288 -- To view, visit https://review.coreboot.org/c/coreboot/+/33068 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7496a3e313b2c6ee6fb3c4671eac64376d84e0dc Gerrit-Change-Number: 33068 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: xcompile: Remove --rtlib switch from clang CFLAGS
by Patrick Georgi (Code Review) 29 May '19

29 May '19

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/21354 ) Change subject: xcompile: Remove --rtlib switch from clang CFLAGS ...................................................................... Patch Set 3: That option was created by a patch to clang that we don't carry (and nobody else either) -- To view, visit https://review.coreboot.org/c/coreboot/+/21354 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ife7ef6b6b47a04598fc67b40751bc59eed93b4af Gerrit-Change-Number: 21354 Gerrit-PatchSet: 3 Gerrit-Owner: Damien Zammit Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 29 May 2019 20:33:55 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: xcompile: Remove --rtlib switch from clang CFLAGS
by Patrick Georgi (Code Review) 29 May '19

29 May '19

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/21354 ) Change subject: xcompile: Remove --rtlib switch from clang CFLAGS ...................................................................... xcompile: Remove --rtlib switch from clang CFLAGS Fix the following error from clang invoking gcc linker with wrong arg: i386-elf-gcc: error: unrecognized command line option '--rtlib=libgcc'; did you mean '-static-libgcc'? clang-4.0: error: linker (via gcc) command failed with exit code 1 Just remove --rtlib switch from CFLAGS relating to clang Change-Id: Ife7ef6b6b47a04598fc67b40751bc59eed93b4af Signed-off-by: Damien Zammit <damien(a)zamaudio.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/21354 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin Roth <martinroth(a)google.com> --- M util/xcompile/xcompile 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile index 40356d9..7ab1cb7 100755 --- a/util/xcompile/xcompile +++ b/util/xcompile/xcompile @@ -453,7 +453,7 @@ # but that's more of a clang limitation. Let's be optimistic # that this will change in the future. CLANG="${clang_prefix}clang" - CFLAGS_CLANG="-target ${clang_arch}-${TABI} --rtlib=${CLANG_RUNTIME} $CFLAGS_CLANG -ccc-gcc-name ${GCC}" + CFLAGS_CLANG="-target ${clang_arch}-${TABI} $CFLAGS_CLANG -ccc-gcc-name ${GCC}" fi } -- To view, visit https://review.coreboot.org/c/coreboot/+/21354 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ife7ef6b6b47a04598fc67b40751bc59eed93b4af Gerrit-Change-Number: 21354 Gerrit-PatchSet: 3 Gerrit-Owner: Damien Zammit Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: libpayload/drivers/i8402/kbd: Fix qemu
by Patrick Georgi (Code Review) 29 May '19

29 May '19

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/23584 ) Change subject: libpayload/drivers/i8402/kbd: Fix qemu ...................................................................... libpayload/drivers/i8402/kbd: Fix qemu Reset keyboard controller to fix qemu make scan codes. Change-Id: I5f8ad2d4be4b9e89d9af3a62726259e77f0403c1 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/23584 Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M payloads/libpayload/drivers/i8042/keyboard.c 1 file changed, 8 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved diff --git a/payloads/libpayload/drivers/i8042/keyboard.c b/payloads/libpayload/drivers/i8042/keyboard.c index fea9e71..12255fb 100644 --- a/payloads/libpayload/drivers/i8042/keyboard.c +++ b/payloads/libpayload/drivers/i8042/keyboard.c @@ -333,6 +333,14 @@ if (!ret && !CONFIG(LP_PC_KEYBOARD_IGNORE_INIT_FAILURE)) return; + /* + * Set default parameters. + * Fix for broken QEMU ps/2 make scancodes. + */ + ret = keyboard_cmd(0xf6); + if (!ret) + return; + /* Enable scanning */ ret = keyboard_cmd(I8042_KBCMD_EN); if (!ret && !CONFIG(LP_PC_KEYBOARD_IGNORE_INIT_FAILURE)) -- To view, visit https://review.coreboot.org/c/coreboot/+/23584 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f8ad2d4be4b9e89d9af3a62726259e77f0403c1 Gerrit-Change-Number: 23584 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: libpayload/drivers/i8402/kbd: Fix qemu
by Patrick Georgi (Code Review) 29 May '19

29 May '19

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/23584 ) Change subject: libpayload/drivers/i8402/kbd: Fix qemu ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/23584 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f8ad2d4be4b9e89d9af3a62726259e77f0403c1 Gerrit-Change-Number: 23584 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Comment-Date: Wed, 29 May 2019 20:32:36 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: src/mainboard: Add missing 'include <types.h>'
by HAOUAS Elyes (Code Review) 29 May '19

29 May '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32811 Change subject: src/mainboard: Add missing 'include <types.h>' ...................................................................... src/mainboard: Add missing 'include <types.h>' <types.h> is supposed to provide <stdint.h> and <stddef.h>. So when <types.h> is included, <stdint.h> and/or <stddef.h> is removed. Change-Id: I3b1a395cfe8b710fb6b468e68f4c92e063794568 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/asus/kcma-d8/romstage.c M src/mainboard/asus/kgpe-d16/romstage.c M src/mainboard/cubietech/cubieboard/romstage.c M src/mainboard/lenovo/t430s/variants/t430s/romstage.c M src/mainboard/siemens/mc_apl1/mainboard.c M src/mainboard/siemens/mc_apl1/variants/mc_apl1/mainboard.c M src/mainboard/siemens/mc_apl1/variants/mc_apl1/ptn3460.c M src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c M src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c M src/mainboard/siemens/mc_apl1/variants/mc_apl4/ptn3460.c M src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c M src/mainboard/siemens/mc_apl1/variants/mc_apl5/ptn3460.c M src/mainboard/siemens/mc_tcu3/ptn3460.c 13 files changed, 13 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/32811/1 diff --git a/src/mainboard/asus/kcma-d8/romstage.c b/src/mainboard/asus/kcma-d8/romstage.c index 5d43a54..6c40627 100644 --- a/src/mainboard/asus/kcma-d8/romstage.c +++ b/src/mainboard/asus/kcma-d8/romstage.c @@ -17,7 +17,6 @@ * GNU General Public License for more details. */ -#include <stdint.h> #include <device/pci_def.h> #include <arch/io.h> #include <device/pci_ops.h> @@ -44,6 +43,7 @@ #include <cpu/amd/family_10h-family_15h/init_cpus.h> #include <arch/early_variables.h> #include <cbmem.h> +#include <types.h> #include "cpu/amd/quadcore/quadcore.c" diff --git a/src/mainboard/asus/kgpe-d16/romstage.c b/src/mainboard/asus/kgpe-d16/romstage.c index f7d30bd..d017b06 100644 --- a/src/mainboard/asus/kgpe-d16/romstage.c +++ b/src/mainboard/asus/kgpe-d16/romstage.c @@ -17,7 +17,6 @@ * GNU General Public License for more details. */ -#include <stdint.h> #include <device/pci_def.h> #include <arch/io.h> #include <device/mmio.h> @@ -45,6 +44,7 @@ #include <cpu/amd/family_10h-family_15h/init_cpus.h> #include <arch/early_variables.h> #include <cbmem.h> +#include <types.h> #include "cpu/amd/quadcore/quadcore.c" diff --git a/src/mainboard/cubietech/cubieboard/romstage.c b/src/mainboard/cubietech/cubieboard/romstage.c index 21fa9b5..bfb5e02 100644 --- a/src/mainboard/cubietech/cubieboard/romstage.c +++ b/src/mainboard/cubietech/cubieboard/romstage.c @@ -31,7 +31,7 @@ #include <device/device.h> #include <drivers/xpowers/axp209/axp209.h> #include <drivers/xpowers/axp209/chip.h> - +#include <types.h> #define GPB_TWI0_FUNC 2 #define GPB_TWI0_PINS ((1 << 0) | (1 << 1)) diff --git a/src/mainboard/lenovo/t430s/variants/t430s/romstage.c b/src/mainboard/lenovo/t430s/variants/t430s/romstage.c index e461681..5bc7b80 100644 --- a/src/mainboard/lenovo/t430s/variants/t430s/romstage.c +++ b/src/mainboard/lenovo/t430s/variants/t430s/romstage.c @@ -22,6 +22,7 @@ #include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> #include <ec/lenovo/pmh7/pmh7.h> +#include <types.h> const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 0, 0 }, /* P0:, OC 0 */ diff --git a/src/mainboard/siemens/mc_apl1/mainboard.c b/src/mainboard/siemens/mc_apl1/mainboard.c index b39b681..c931e10 100644 --- a/src/mainboard/siemens/mc_apl1/mainboard.c +++ b/src/mainboard/siemens/mc_apl1/mainboard.c @@ -28,6 +28,7 @@ #include <string.h> #include <timer.h> #include <baseboard/variants.h> +#include <types.h> #define MAX_PATH_DEPTH 12 #define MAX_NUM_MAPPINGS 10 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/mainboard.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/mainboard.c index 6d22fd9..df6fc21 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/mainboard.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/mainboard.c @@ -25,6 +25,7 @@ #include <timer.h> #include <timestamp.h> #include <baseboard/variants.h> +#include <types.h> #include <variant/ptn3460.h> #define TX_DWORD3 0xa8c diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/ptn3460.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/ptn3460.c index 060a35c..c0770f3 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/ptn3460.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/ptn3460.c @@ -16,6 +16,7 @@ #include <console/console.h> #include <hwilib.h> #include <device/i2c_simple.h> +#include <types.h> #include <variant/ptn3460.h> /** diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c index f52091b..7890ee0 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c @@ -24,6 +24,7 @@ #include <timestamp.h> #include <baseboard/variants.h> #include <soc/pci_devs.h> +#include <types.h> #define SD_CAP_BYP 0x810 #define SD_CAP_BYP_EN 0x5A diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c index 3e2e7f0..6a883c6 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c @@ -28,6 +28,7 @@ #include <timer.h> #include <timestamp.h> #include <baseboard/variants.h> +#include <types.h> #define TX_DWORD3 0xa8c diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/ptn3460.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/ptn3460.c index 73d9019..47763ae 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/ptn3460.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/ptn3460.c @@ -16,6 +16,7 @@ #include <console/console.h> #include <hwilib.h> #include <device/i2c_simple.h> +#include <types.h> #include <variant/ptn3460.h> /* diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c index 9462497..e1b56bd 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c @@ -26,6 +26,7 @@ #include <timer.h> #include <timestamp.h> #include <baseboard/variants.h> +#include <types.h> #include <variant/ptn3460.h> #define TX_DWORD3 0xa8c diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/ptn3460.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/ptn3460.c index 060a35c..c0770f3 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/ptn3460.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/ptn3460.c @@ -16,6 +16,7 @@ #include <console/console.h> #include <hwilib.h> #include <device/i2c_simple.h> +#include <types.h> #include <variant/ptn3460.h> /** diff --git a/src/mainboard/siemens/mc_tcu3/ptn3460.c b/src/mainboard/siemens/mc_tcu3/ptn3460.c index 9acc60a..414baeb 100644 --- a/src/mainboard/siemens/mc_tcu3/ptn3460.c +++ b/src/mainboard/siemens/mc_tcu3/ptn3460.c @@ -17,6 +17,7 @@ #include <hwilib.h> #include <string.h> #include <delay.h> +#include <types.h> #include "soc/i2c.h" #include "ptn3460.h" -- To view, visit https://review.coreboot.org/c/coreboot/+/32811 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3b1a395cfe8b710fb6b468e68f4c92e063794568 Gerrit-Change-Number: 32811 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: src/soc: Add missing 'include <types.h>'
by HAOUAS Elyes (Code Review) 29 May '19

29 May '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32810 Change subject: src/soc: Add missing 'include <types.h>' ...................................................................... src/soc: Add missing 'include <types.h>' <types.h> is supposed to provide <stdint.h> and <stddef.h>. When <types.h> is included, <stdint.h> and/or <stddef.h> is removed. Change-Id: I2db0a647bc657a3626cb5e78f23e9198e290261a Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/amd/common/block/include/amdblocks/psp.h M src/soc/amd/stoneyridge/include/soc/northbridge.h M src/soc/amd/stoneyridge/southbridge.c M src/soc/intel/apollolake/graphics.c M src/soc/intel/baytrail/gfx.c M src/soc/intel/broadwell/igd.c M src/soc/intel/cannonlake/graphics.c M src/soc/intel/icelake/graphics.c M src/soc/intel/skylake/graphics.c M src/soc/mediatek/common/pll.c M src/soc/mediatek/mt8173/ddp.c M src/soc/mediatek/mt8173/pll.c M src/soc/mediatek/mt8173/rtc.c M src/soc/nvidia/tegra210/dsi.c M src/soc/nvidia/tegra210/include/soc/dma.h M src/soc/nvidia/tegra210/mipi-phy.c M src/soc/nvidia/tegra210/spi.c M src/soc/qualcomm/ipq806x/include/soc/clock.h M src/soc/rockchip/common/gpio.c M src/soc/rockchip/rk3399/include/soc/mipi.h M src/soc/rockchip/rk3399/mipi.c 21 files changed, 25 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/32810/1 diff --git a/src/soc/amd/common/block/include/amdblocks/psp.h b/src/soc/amd/common/block/include/amdblocks/psp.h index 25a564b..512b0b8 100644 --- a/src/soc/amd/common/block/include/amdblocks/psp.h +++ b/src/soc/amd/common/block/include/amdblocks/psp.h @@ -18,7 +18,7 @@ #include <amdblocks/agesawrapper.h> #include <soc/pci_devs.h> -#include <stdint.h> +#include <types.h> /* Extra, Special Purpose Registers in the PSP PCI Config Space */ diff --git a/src/soc/amd/stoneyridge/include/soc/northbridge.h b/src/soc/amd/stoneyridge/include/soc/northbridge.h index 563dae0..60a6ea2 100644 --- a/src/soc/amd/stoneyridge/include/soc/northbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/northbridge.h @@ -18,6 +18,7 @@ #define __PI_STONEYRIDGE_NORTHBRIDGE_H__ #include <device/device.h> +#include <types.h> /* D0F0 - Root Complex */ diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index b6c40b6..692f75d 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -14,7 +14,6 @@ */ #include <console/console.h> - #include <device/mmio.h> #include <bootstate.h> #include <cpu/x86/smm.h> @@ -35,6 +34,7 @@ #include <soc/pci_devs.h> #include <agesa_headers.h> #include <soc/nvs.h> +#include <types.h> /* * Table of devices that need their AOAC registers enabled and waited diff --git a/src/soc/intel/apollolake/graphics.c b/src/soc/intel/apollolake/graphics.c index 51661d0..f5136ec 100644 --- a/src/soc/intel/apollolake/graphics.c +++ b/src/soc/intel/apollolake/graphics.c @@ -26,6 +26,7 @@ #include <intelblocks/graphics.h> #include <drivers/intel/gma/opregion.h> #include <drivers/intel/gma/libgfxinit.h> +#include <types.h> uintptr_t fsp_soc_get_igd_bar(void) { diff --git a/src/soc/intel/baytrail/gfx.c b/src/soc/intel/baytrail/gfx.c index d2cb589..2048c13 100644 --- a/src/soc/intel/baytrail/gfx.c +++ b/src/soc/intel/baytrail/gfx.c @@ -28,6 +28,7 @@ #include <soc/pci_devs.h> #include <soc/ramstage.h> #include <cbmem.h> +#include <types.h> #include "chip.h" diff --git a/src/soc/intel/broadwell/igd.c b/src/soc/intel/broadwell/igd.c index b9b4281..9107b23 100644 --- a/src/soc/intel/broadwell/igd.c +++ b/src/soc/intel/broadwell/igd.c @@ -36,6 +36,7 @@ #include <soc/intel/broadwell/chip.h> #include <security/vboot/vbnv.h> #include <soc/igd.h> +#include <types.h> #define GT_RETRY 1000 enum { diff --git a/src/soc/intel/cannonlake/graphics.c b/src/soc/intel/cannonlake/graphics.c index a89dcb3..2acfecc 100644 --- a/src/soc/intel/cannonlake/graphics.c +++ b/src/soc/intel/cannonlake/graphics.c @@ -23,6 +23,7 @@ #include <drivers/intel/gma/i915_reg.h> #include <drivers/intel/gma/opregion.h> #include <intelblocks/graphics.h> +#include <types.h> uintptr_t fsp_soc_get_igd_bar(void) { diff --git a/src/soc/intel/icelake/graphics.c b/src/soc/intel/icelake/graphics.c index 35fe8b6..0fbddf0 100644 --- a/src/soc/intel/icelake/graphics.c +++ b/src/soc/intel/icelake/graphics.c @@ -23,6 +23,7 @@ #include <drivers/intel/gma/i915_reg.h> #include <drivers/intel/gma/opregion.h> #include <intelblocks/graphics.h> +#include <types.h> uintptr_t fsp_soc_get_igd_bar(void) { diff --git a/src/soc/intel/skylake/graphics.c b/src/soc/intel/skylake/graphics.c index 07ee67a..f563c11 100644 --- a/src/soc/intel/skylake/graphics.c +++ b/src/soc/intel/skylake/graphics.c @@ -25,6 +25,7 @@ #include <drivers/intel/gma/opregion.h> #include <soc/nvs.h> #include <soc/ramstage.h> +#include <types.h> uintptr_t fsp_soc_get_igd_bar(void) { diff --git a/src/soc/mediatek/common/pll.c b/src/soc/mediatek/common/pll.c index 0968d2f..a63fe89 100644 --- a/src/soc/mediatek/common/pll.c +++ b/src/soc/mediatek/common/pll.c @@ -16,6 +16,7 @@ #include <device/mmio.h> #include <assert.h> #include <soc/pll.h> +#include <types.h> #define GENMASK(h, l) (BIT(h + 1) - BIT(l)) diff --git a/src/soc/mediatek/mt8173/ddp.c b/src/soc/mediatek/mt8173/ddp.c index 0b78c3e..f8896d3 100644 --- a/src/soc/mediatek/mt8173/ddp.c +++ b/src/soc/mediatek/mt8173/ddp.c @@ -19,6 +19,7 @@ #include <stddef.h> #include <soc/addressmap.h> #include <soc/ddp.h> +#include <types.h> #define RDMA_FIFO_PSEUDO_SIZE(bytes) (((bytes) / 16) << 16) #define RDMA_OUTPUT_VALID_FIFO_THRESHOLD(bytes) ((bytes) / 16) diff --git a/src/soc/mediatek/mt8173/pll.c b/src/soc/mediatek/mt8173/pll.c index 7eb12b1..e1c1bff 100644 --- a/src/soc/mediatek/mt8173/pll.c +++ b/src/soc/mediatek/mt8173/pll.c @@ -16,11 +16,10 @@ #include <device/mmio.h> #include <assert.h> #include <delay.h> -#include <stddef.h> - #include <soc/addressmap.h> #include <soc/infracfg.h> #include <soc/pll.h> +#include <types.h> enum mux_id { TOP_AXI_SEL, diff --git a/src/soc/mediatek/mt8173/rtc.c b/src/soc/mediatek/mt8173/rtc.c index 79e5732..9ad4caa 100644 --- a/src/soc/mediatek/mt8173/rtc.c +++ b/src/soc/mediatek/mt8173/rtc.c @@ -18,6 +18,7 @@ #include <soc/rtc.h> #include <soc/mt6391.h> #include <soc/pmic_wrap.h> +#include <types.h> #define RTC_GPIO_USER_MASK ((1 << 13) - (1 << 8)) diff --git a/src/soc/nvidia/tegra210/dsi.c b/src/soc/nvidia/tegra210/dsi.c index 76054f0..52505138 100644 --- a/src/soc/nvidia/tegra210/dsi.c +++ b/src/soc/nvidia/tegra210/dsi.c @@ -12,10 +12,10 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ + +#include <commonlib/helpers.h> #include <console/console.h> #include <device/mmio.h> -#include <stdint.h> -#include <stdlib.h> #include <delay.h> #include <timer.h> #include <soc/addressmap.h> @@ -24,14 +24,15 @@ #include <edid.h> #include <soc/nvidia/tegra/types.h> #include <soc/nvidia/tegra/dc.h> -#include "chip.h" #include <soc/display.h> #include <soc/mipi_dsi.h> #include <soc/mipi_display.h> #include <soc/tegra_dsi.h> #include <soc/mipi-phy.h> +#include <types.h> + +#include "chip.h" #include "jdi_25x18_display/panel-jdi-lpm102a188a.h" -#include <commonlib/helpers.h> struct tegra_mipi_device mipi_device_data[NUM_DSI]; diff --git a/src/soc/nvidia/tegra210/include/soc/dma.h b/src/soc/nvidia/tegra210/include/soc/dma.h index 1093479..3cb94ce 100644 --- a/src/soc/nvidia/tegra210/include/soc/dma.h +++ b/src/soc/nvidia/tegra210/include/soc/dma.h @@ -19,6 +19,7 @@ #include <inttypes.h> #include <soc/addressmap.h> +#include <types.h> /* * The DMA engine operates on 4 bytes at a time, so make sure any data diff --git a/src/soc/nvidia/tegra210/mipi-phy.c b/src/soc/nvidia/tegra210/mipi-phy.c index 4e6bdf0..4e56730 100644 --- a/src/soc/nvidia/tegra210/mipi-phy.c +++ b/src/soc/nvidia/tegra210/mipi-phy.c @@ -13,9 +13,7 @@ * GNU General Public License for more details. */ -#include <stdint.h> #include <stdlib.h> - #include <soc/addressmap.h> #include <soc/clock.h> #include <device/device.h> @@ -25,6 +23,7 @@ #include <soc/mipi_display.h> #include <soc/tegra_dsi.h> #include <soc/mipi-phy.h> +#include <types.h> int mipi_dphy_set_timing(struct tegra_dsi *dsi) { diff --git a/src/soc/nvidia/tegra210/spi.c b/src/soc/nvidia/tegra210/spi.c index edb052d..9310e0c 100644 --- a/src/soc/nvidia/tegra210/spi.c +++ b/src/soc/nvidia/tegra210/spi.c @@ -26,9 +26,8 @@ #include <soc/addressmap.h> #include <soc/dma.h> #include <soc/spi.h> -#include <stdint.h> -#include <stdlib.h> #include <symbols.h> +#include <types.h> #if defined(CONFIG_DEBUG_SPI) && CONFIG_DEBUG_SPI # define DEBUG_SPI(x,...) printk(BIOS_DEBUG, "TEGRA_SPI: " x) diff --git a/src/soc/qualcomm/ipq806x/include/soc/clock.h b/src/soc/qualcomm/ipq806x/include/soc/clock.h index 482dead..7ecc1ee 100644 --- a/src/soc/qualcomm/ipq806x/include/soc/clock.h +++ b/src/soc/qualcomm/ipq806x/include/soc/clock.h @@ -34,6 +34,7 @@ #define __IPQ860X_CLOCK_H_ #include <soc/iomap.h> +#include <types.h> /* UART clock @ 7.3728 MHz */ #define UART_DM_CLK_RX_TX_BIT_RATE 0xCC diff --git a/src/soc/rockchip/common/gpio.c b/src/soc/rockchip/common/gpio.c index fa0990b..3d7e161 100644 --- a/src/soc/rockchip/common/gpio.c +++ b/src/soc/rockchip/common/gpio.c @@ -20,6 +20,7 @@ #include <soc/grf.h> #include <soc/soc.h> #include <stdlib.h> +#include <types.h> static void gpio_set_dir(gpio_t gpio, enum gpio_dir dir) { diff --git a/src/soc/rockchip/rk3399/include/soc/mipi.h b/src/soc/rockchip/rk3399/include/soc/mipi.h index f304d8f..43ab7b9 100644 --- a/src/soc/rockchip/rk3399/include/soc/mipi.h +++ b/src/soc/rockchip/rk3399/include/soc/mipi.h @@ -17,6 +17,7 @@ #define __RK_MIPI_H #include <stdlib.h> +#include <types.h> struct rk_mipi_regs { u32 dsi_version; diff --git a/src/soc/rockchip/rk3399/mipi.c b/src/soc/rockchip/rk3399/mipi.c index cc16563..1f3f02c 100644 --- a/src/soc/rockchip/rk3399/mipi.c +++ b/src/soc/rockchip/rk3399/mipi.c @@ -20,13 +20,13 @@ #include <edid.h> #include <gpio.h> #include <stdlib.h> -#include <stdint.h> #include <string.h> #include <soc/addressmap.h> #include <soc/clock.h> #include <soc/display.h> #include <soc/mipi.h> #include <soc/soc.h> +#include <types.h> #include <timer.h> static struct rk_mipi_dsi rk_mipi[2] = { -- To view, visit https://review.coreboot.org/c/coreboot/+/32810 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2db0a647bc657a3626cb5e78f23e9198e290261a Gerrit-Change-Number: 32810 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 5

Change in ...coreboot[master]: src/southbridge: Add missing 'include <types.h>'
by Patrick Georgi (Code Review) 29 May '19

29 May '19

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/32809 ) Change subject: src/southbridge: Add missing 'include <types.h>' ...................................................................... src/southbridge: Add missing 'include <types.h>' <types.h> is supposed to provide <stdint.h> and <stddef.h>. When <types.h> is included, <stdint.h> and/or <stddef.h> is removed. Change-Id: I4d8628e4ce3c7f80da2590b4cad618b290e0d513 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32809 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao(a)intel.com> --- M src/southbridge/amd/pi/hudson/hudson.c M src/southbridge/amd/pi/hudson/lpc.c M src/southbridge/amd/sb700/ide.c M src/southbridge/amd/sb700/sata.c M src/southbridge/amd/sb700/usb.c M src/southbridge/intel/bd82x6x/sata.c M src/southbridge/intel/common/smbus.c M src/southbridge/intel/i82801ix/sata.c M src/southbridge/intel/i82801jx/sata.c M src/southbridge/intel/ibexpeak/sata.c 10 files changed, 24 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Lijian Zhao: Looks good to me, approved diff --git a/src/southbridge/amd/pi/hudson/hudson.c b/src/southbridge/amd/pi/hudson/hudson.c index e1ea2ce..a331c57 100644 --- a/src/southbridge/amd/pi/hudson/hudson.c +++ b/src/southbridge/amd/pi/hudson/hudson.c @@ -14,16 +14,16 @@ */ #include <console/console.h> - #include <arch/io.h> #include <device/mmio.h> #include <arch/acpi.h> - #include <device/device.h> #include <device/pci.h> #include <device/pci_def.h> #include <device/pci_ids.h> #include <device/pci_ops.h> +#include <types.h> + #include "hudson.h" #include "smbus.h" #include "smi.h" diff --git a/src/southbridge/amd/pi/hudson/lpc.c b/src/southbridge/amd/pi/hudson/lpc.c index abb92f2..5354a27 100644 --- a/src/southbridge/amd/pi/hudson/lpc.c +++ b/src/southbridge/amd/pi/hudson/lpc.c @@ -27,6 +27,8 @@ #include <arch/acpi.h> #include <pc80/i8254.h> #include <pc80/i8259.h> +#include <types.h> + #include "hudson.h" #include "pci_devs.h" diff --git a/src/southbridge/amd/sb700/ide.c b/src/southbridge/amd/sb700/ide.c index 6734643..0b11db3 100644 --- a/src/southbridge/amd/sb700/ide.c +++ b/src/southbridge/amd/sb700/ide.c @@ -19,6 +19,8 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> #include <option.h> +#include <types.h> + #include "sb700.h" static void ide_init(struct device *dev) diff --git a/src/southbridge/amd/sb700/sata.c b/src/southbridge/amd/sb700/sata.c index 39aef63..292a7f2 100644 --- a/src/southbridge/amd/sb700/sata.c +++ b/src/southbridge/amd/sb700/sata.c @@ -23,6 +23,8 @@ #include <arch/io.h> #include <device/mmio.h> #include <option.h> +#include <types.h> + #include "sb700.h" static int sata_drive_detect(int portnum, uint16_t iobar) diff --git a/src/southbridge/amd/sb700/usb.c b/src/southbridge/amd/sb700/usb.c index da65311..4109e88 100644 --- a/src/southbridge/amd/sb700/usb.c +++ b/src/southbridge/amd/sb700/usb.c @@ -21,6 +21,8 @@ #include <device/pci_ehci.h> #include <device/mmio.h> #include <option.h> +#include <types.h> + #include "sb700.h" static struct pci_operations lops_pci = { diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c index 91c87bf..6a39873 100644 --- a/src/southbridge/intel/bd82x6x/sata.c +++ b/src/southbridge/intel/bd82x6x/sata.c @@ -20,9 +20,11 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include "pch.h" #include <pc80/mc146818rtc.h> #include <acpi/sata.h> +#include <types.h> + +#include "pch.h" typedef struct southbridge_intel_bd82x6x_config config_t; diff --git a/src/southbridge/intel/common/smbus.c b/src/southbridge/intel/common/smbus.c index 4b08c48..af1eb60 100644 --- a/src/southbridge/intel/common/smbus.c +++ b/src/southbridge/intel/common/smbus.c @@ -19,6 +19,8 @@ #include <console/console.h> #include <device/smbus_def.h> #include <stdlib.h> +#include <types.h> + #include "smbus.h" diff --git a/src/southbridge/intel/i82801ix/sata.c b/src/southbridge/intel/i82801ix/sata.c index 6155c15..49d2d36 100644 --- a/src/southbridge/intel/i82801ix/sata.c +++ b/src/southbridge/intel/i82801ix/sata.c @@ -22,8 +22,10 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include "i82801ix.h" #include <pc80/mc146818rtc.h> +#include <types.h> + +#include "i82801ix.h" typedef struct southbridge_intel_i82801ix_config config_t; diff --git a/src/southbridge/intel/i82801jx/sata.c b/src/southbridge/intel/i82801jx/sata.c index 8de2d74..ddaa783 100644 --- a/src/southbridge/intel/i82801jx/sata.c +++ b/src/southbridge/intel/i82801jx/sata.c @@ -22,8 +22,10 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include "i82801jx.h" #include <pc80/mc146818rtc.h> +#include <types.h> + +#include "i82801jx.h" typedef struct southbridge_intel_i82801jx_config config_t; diff --git a/src/southbridge/intel/ibexpeak/sata.c b/src/southbridge/intel/ibexpeak/sata.c index 112445b..e03f8b5 100644 --- a/src/southbridge/intel/ibexpeak/sata.c +++ b/src/southbridge/intel/ibexpeak/sata.c @@ -21,9 +21,11 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include "pch.h" #include <pc80/mc146818rtc.h> #include <acpi/sata.h> +#include <types.h> + +#include "pch.h" typedef struct southbridge_intel_ibexpeak_config config_t; -- To view, visit https://review.coreboot.org/c/coreboot/+/32809 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4d8628e4ce3c7f80da2590b4cad618b290e0d513 Gerrit-Change-Number: 32809 Gerrit-PatchSet: 2 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in ...coreboot[master]: src/northbridge: Add missing 'include <types.h>'
by Patrick Georgi (Code Review) 29 May '19

29 May '19

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/32808 ) Change subject: src/northbridge: Add missing 'include <types.h>' ...................................................................... src/northbridge: Add missing 'include <types.h>' <types.h> is supposed to provide <stdint.h> and <stddef.h>. When <types.h> is included, <stdint.h> and/or <stddef.h> is removed. Change-Id: Iad5367bed844b866b2ad87639eee29a16d9a99ed Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32808 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao(a)intel.com> --- M src/northbridge/amd/amdfam10/link_control.c M src/northbridge/amd/amdfam10/misc_control.c M src/northbridge/amd/amdfam10/northbridge.c M src/northbridge/amd/amdht/h3finit.c M src/northbridge/amd/amdmct/mct_ddr3/mct_d.c M src/northbridge/amd/amdmct/mct_ddr3/s3utils.c M src/northbridge/amd/amdmct/wrappers/mcti_d.c M src/northbridge/intel/gm45/gma.c M src/northbridge/intel/haswell/gma.c M src/northbridge/intel/i945/early_init.c M src/northbridge/intel/i945/gma.c M src/northbridge/intel/nehalem/gma.c M src/northbridge/intel/nehalem/raminit.c M src/northbridge/intel/pineview/early_init.c M src/northbridge/intel/pineview/gma.c M src/northbridge/intel/sandybridge/early_init.c M src/northbridge/intel/sandybridge/gma.c M src/northbridge/intel/sandybridge/raminit.c M src/northbridge/intel/x4x/gma.c M src/northbridge/intel/x4x/raminit.c 20 files changed, 32 insertions(+), 12 deletions(-) Approvals: build bot (Jenkins): Verified Lijian Zhao: Looks good to me, approved diff --git a/src/northbridge/amd/amdfam10/link_control.c b/src/northbridge/amd/amdfam10/link_control.c index 871a436..3847723 100644 --- a/src/northbridge/amd/amdfam10/link_control.c +++ b/src/northbridge/amd/amdfam10/link_control.c @@ -25,6 +25,7 @@ #include <device/pci_ops.h> #include <pc80/mc146818rtc.h> #include <cpu/amd/model_10xxx_rev.h> +#include <types.h> #include "amdfam10.h" diff --git a/src/northbridge/amd/amdfam10/misc_control.c b/src/northbridge/amd/amdfam10/misc_control.c index bbaec53..b0a1ab6 100644 --- a/src/northbridge/amd/amdfam10/misc_control.c +++ b/src/northbridge/amd/amdfam10/misc_control.c @@ -32,6 +32,7 @@ #include <lib.h> #include <cbmem.h> #include <cpu/amd/model_10xxx_rev.h> +#include <types.h> #include "amdfam10.h" diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 1d071c1..a681961 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -34,6 +34,7 @@ #include <cpu/amd/amdfam10_sysconf.h> #include <cpu/amd/msr.h> #include <cpu/amd/family_10h-family_15h/ram_calc.h> +#include <types.h> #if CONFIG(LOGICAL_CPUS) #include <cpu/amd/multicore.h> diff --git a/src/northbridge/amd/amdht/h3finit.c b/src/northbridge/amd/amdht/h3finit.c index 8c33ad8..cda0a28 100644 --- a/src/northbridge/amd/amdht/h3finit.c +++ b/src/northbridge/amd/amdht/h3finit.c @@ -36,6 +36,7 @@ #include <device/pci_def.h> #include <northbridge/amd/amdfam10/raminit.h> #include <northbridge/amd/amdfam10/amdfam10.h> +#include <types.h> /*---------------------------------------------------------------------------- * DEFINITIONS AND MACROS diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index 74e5234..42e91b6 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -43,7 +43,9 @@ #include <device/pci_ops.h> #include <arch/acpi.h> #include <string.h> +#include <types.h> #include <device/dram/ddr3.h> + #include "s3utils.h" #include "mct_d_gcc.h" #include "mct_d.h" diff --git a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c index a78a752..d991002 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c @@ -30,6 +30,8 @@ #include <spi_flash.h> #include <pc80/mc146818rtc.h> #include <inttypes.h> +#include <types.h> + #include "mct_d.h" #include "mct_d_gcc.h" diff --git a/src/northbridge/amd/amdmct/wrappers/mcti_d.c b/src/northbridge/amd/amdmct/wrappers/mcti_d.c index 7aaf016..b8042fe 100644 --- a/src/northbridge/amd/amdmct/wrappers/mcti_d.c +++ b/src/northbridge/amd/amdmct/wrappers/mcti_d.c @@ -19,6 +19,7 @@ #include <arch/cpu.h> #include <cpu/amd/msr.h> #include <console/console.h> +#include <types.h> #include "mcti.h" diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c index 3549b49..a2de7f0 100644 --- a/src/northbridge/intel/gm45/gma.c +++ b/src/northbridge/intel/gm45/gma.c @@ -27,6 +27,7 @@ #include <commonlib/helpers.h> #include <cbmem.h> #include <southbridge/intel/i82801ix/nvs.h> +#include <types.h> #include "drivers/intel/gma/i915_reg.h" #include "chip.h" diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index 1b2430f..607fab7 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -31,6 +31,7 @@ #include <southbridge/intel/lynxpoint/nvs.h> #include <stdlib.h> #include <string.h> +#include <types.h> #include "chip.h" #include "haswell.h" diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index 84d9c10..f9167df 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <stdint.h> #include <stdlib.h> #include <cf9_reset.h> #include <console/console.h> @@ -22,9 +21,11 @@ #include <device/pci_def.h> #include <cbmem.h> #include <romstage_handoff.h> -#include "i945.h" #include <pc80/mc146818rtc.h> #include <southbridge/intel/common/gpio.h> +#include <types.h> + +#include "i945.h" int i945_silicon_revision(void) { diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index 1d20533..54ff47c 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -33,6 +33,7 @@ #include <commonlib/helpers.h> #include <cbmem.h> #include <southbridge/intel/i82801gx/nvs.h> +#include <types.h> #include "i945.h" #include "chip.h" diff --git a/src/northbridge/intel/nehalem/gma.c b/src/northbridge/intel/nehalem/gma.c index 8c0117f..087d37e 100644 --- a/src/northbridge/intel/nehalem/gma.c +++ b/src/northbridge/intel/nehalem/gma.c @@ -31,6 +31,7 @@ #include <southbridge/intel/ibexpeak/nvs.h> #include <drivers/intel/gma/opregion.h> #include <cbmem.h> +#include <types.h> #include "chip.h" #include "nehalem.h" diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c index 5b6077f..15d6abb 100644 --- a/src/northbridge/intel/nehalem/raminit.c +++ b/src/northbridge/intel/nehalem/raminit.c @@ -30,18 +30,18 @@ #include <device/device.h> #include <halt.h> #include <spd.h> -#include "raminit.h" -#include "chip.h" #include <timestamp.h> #include <cpu/x86/mtrr.h> #include <cpu/intel/speedstep.h> #include <cpu/intel/turbo.h> #include <mrc_cache.h> - -#include "nehalem.h" - #include <southbridge/intel/ibexpeak/me.h> #include <delay.h> +#include <types.h> + +#include "chip.h" +#include "nehalem.h" +#include "raminit.h" #define NORTHBRIDGE PCI_DEV(0, 0, 0) #define SOUTHBRIDGE PCI_DEV(0, 0x1f, 0) diff --git a/src/northbridge/intel/pineview/early_init.c b/src/northbridge/intel/pineview/early_init.c index 509ab4e..be6a5e2 100644 --- a/src/northbridge/intel/pineview/early_init.c +++ b/src/northbridge/intel/pineview/early_init.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ -#include <stdint.h> #include <stdlib.h> #include <console/console.h> #include <arch/io.h> @@ -24,6 +23,7 @@ #include <northbridge/intel/pineview/pineview.h> #include <northbridge/intel/pineview/chip.h> #include <pc80/mc146818rtc.h> +#include <types.h> #define LPC PCI_DEV(0, 0x1f, 0) #define D0F0 PCI_DEV(0, 0, 0) diff --git a/src/northbridge/intel/pineview/gma.c b/src/northbridge/intel/pineview/gma.c index 019f764..dd6cb32 100644 --- a/src/northbridge/intel/pineview/gma.c +++ b/src/northbridge/intel/pineview/gma.c @@ -23,10 +23,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> - #include <drivers/intel/gma/i915_reg.h> -#include "chip.h" -#include "pineview.h" #include <drivers/intel/gma/intel_bios.h> #include <drivers/intel/gma/i915.h> #include <drivers/intel/gma/opregion.h> @@ -34,6 +31,10 @@ #include <cbmem.h> #include <pc80/vga.h> #include <pc80/vga_io.h> +#include <types.h> + +#include "chip.h" +#include "pineview.h" #define GTTSIZE (512*1024) diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c index 34aec38..fd3d34f 100644 --- a/src/northbridge/intel/sandybridge/early_init.c +++ b/src/northbridge/intel/sandybridge/early_init.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ -#include <stdint.h> #include <stdlib.h> #include <console/console.h> #include <arch/io.h> @@ -22,6 +21,8 @@ #include <device/pci_def.h> #include <pc80/mc146818rtc.h> #include <romstage_handoff.h> +#include <types.h> + #include "sandybridge.h" static void sandybridge_setup_bars(void) diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c index cb6782e..1005288 100644 --- a/src/northbridge/intel/sandybridge/gma.c +++ b/src/northbridge/intel/sandybridge/gma.c @@ -27,6 +27,7 @@ #include <drivers/intel/gma/opregion.h> #include <southbridge/intel/bd82x6x/pch.h> #include <cbmem.h> +#include <types.h> #include "chip.h" #include "sandybridge.h" diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index f67d61f..c13ae37 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -30,6 +30,7 @@ #include <southbridge/intel/common/smbus.h> #include <southbridge/intel/bd82x6x/pch.h> #include <cpu/x86/msr.h> +#include <types.h> #include "raminit_native.h" #include "raminit_common.h" diff --git a/src/northbridge/intel/x4x/gma.c b/src/northbridge/intel/x4x/gma.c index c4e8bf1..61731fe 100644 --- a/src/northbridge/intel/x4x/gma.c +++ b/src/northbridge/intel/x4x/gma.c @@ -29,6 +29,7 @@ #include <drivers/intel/gma/libgfxinit.h> #include <pc80/vga.h> #include <pc80/vga_io.h> +#include <types.h> #include "chip.h" #include "drivers/intel/gma/i915_reg.h" diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c index 7fed1ef..bd6536a 100644 --- a/src/northbridge/intel/x4x/raminit.c +++ b/src/northbridge/intel/x4x/raminit.c @@ -32,6 +32,7 @@ #include <device/dram/ddr3.h> #include <mrc_cache.h> #include <timestamp.h> +#include <types.h> #include "iomap.h" #include "x4x.h" -- To view, visit https://review.coreboot.org/c/coreboot/+/32808 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iad5367bed844b866b2ad87639eee29a16d9a99ed Gerrit-Change-Number: 32808 Gerrit-PatchSet: 3 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in ...coreboot[master]: src/{ec,vendorcode}: Add missing 'include <types.h>
by HAOUAS Elyes (Code Review) 29 May '19

29 May '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32807 Change subject: src/{ec,vendorcode}: Add missing 'include <types.h> ...................................................................... src/{ec,vendorcode}: Add missing 'include <types.h> <types.h> is supposed to provide <stdint.h> and <stddef.h>. So when <types.h> is included, <stdint.h> and/or <stddef.h> is removed. Change-Id: I1eb4163fb36a47b584f1fc9dd3c012e2930e9866 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/ec/lenovo/h8/h8.c M src/ec/lenovo/h8/wwan.c M src/ec/lenovo/pmh7/pmh7.c M src/vendorcode/siemens/hwilib/hwilib.c 4 files changed, 5 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/32807/1 diff --git a/src/ec/lenovo/h8/h8.c b/src/ec/lenovo/h8/h8.c index de4f2c2..f707014c 100644 --- a/src/ec/lenovo/h8/h8.c +++ b/src/ec/lenovo/h8/h8.c @@ -23,6 +23,7 @@ #include <smbios.h> #include <pc80/mc146818rtc.h> #include <pc80/keyboard.h> +#include <types.h> #include "h8.h" #include "chip.h" diff --git a/src/ec/lenovo/h8/wwan.c b/src/ec/lenovo/h8/wwan.c index cf3c8f7..e79cb61 100644 --- a/src/ec/lenovo/h8/wwan.c +++ b/src/ec/lenovo/h8/wwan.c @@ -18,6 +18,7 @@ #include <device/device.h> #include <ec/acpi/ec.h> #include <option.h> +#include <types.h> #include "h8.h" #include "chip.h" diff --git a/src/ec/lenovo/pmh7/pmh7.c b/src/ec/lenovo/pmh7/pmh7.c index 986abb5..ef505cd1 100644 --- a/src/ec/lenovo/pmh7/pmh7.c +++ b/src/ec/lenovo/pmh7/pmh7.c @@ -20,6 +20,7 @@ #include <stdlib.h> #include <pc80/mc146818rtc.h> #include <delay.h> +#include <types.h> #include "pmh7.h" #include "chip.h" diff --git a/src/vendorcode/siemens/hwilib/hwilib.c b/src/vendorcode/siemens/hwilib/hwilib.c index 1213dce..a4d87ad 100644 --- a/src/vendorcode/siemens/hwilib/hwilib.c +++ b/src/vendorcode/siemens/hwilib/hwilib.c @@ -18,8 +18,9 @@ #include <console/console.h> #include <device/mmio.h> #include <arch/early_variables.h> -#include "hwilib.h" +#include <types.h> +#include "hwilib.h" #define MAX_BLOCK_NUM 4 #define LEN_HIB 0x1fd -- To view, visit https://review.coreboot.org/c/coreboot/+/32807 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1eb4163fb36a47b584f1fc9dd3c012e2930e9866 Gerrit-Change-Number: 32807 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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