EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33047
Change subject: mb/google/sarien: Send post code to the EC ......................................................................
mb/google/sarien: Send post code to the EC
Use the mainboard post code hook to inform the wilco EC driver of the every stage.
BUG=b:124401932,b:133466714,b:133600566 BRANCH=sarien TEST=Remove DIMM module, confirm diagnostic LED pattern for memory failure (2 amber, 4 white).
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: Ic71e4a6e62b63ca2fd189957c4d6f49b61b934de --- M src/mainboard/google/sarien/Makefile.inc A src/mainboard/google/sarien/ec.c M src/mainboard/google/sarien/ramstage.c M src/mainboard/google/sarien/romstage.c M src/mainboard/google/sarien/variants/sarien/include/variant/ec.h 5 files changed, 33 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/33047/1
diff --git a/src/mainboard/google/sarien/Makefile.inc b/src/mainboard/google/sarien/Makefile.inc index 6fd23ce..7c37bc9 100644 --- a/src/mainboard/google/sarien/Makefile.inc +++ b/src/mainboard/google/sarien/Makefile.inc @@ -29,5 +29,10 @@
ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB) += hda_verb.c
+bootblock-$(CONFIG_EC_GOOGLE_WILCO) += ec.c +ramstage-$(CONFIG_EC_GOOGLE_WILCO) += ec.c +romstage-$(CONFIG_EC_GOOGLE_WILCO) += ec.c +verstage-$(CONFIG_EC_GOOGLE_WILCO) += ec.c + subdirs-y += variants/$(VARIANT_DIR) CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include diff --git a/src/mainboard/google/sarien/ec.c b/src/mainboard/google/sarien/ec.c new file mode 100644 index 0000000..acf6877 --- /dev/null +++ b/src/mainboard/google/sarien/ec.c @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <ec/google/wilco/commands.h> +#include <variant/ec.h> + +void mainboard_post(uint8_t value) +{ + wilco_ec_save_post_code(value); +} + diff --git a/src/mainboard/google/sarien/ramstage.c b/src/mainboard/google/sarien/ramstage.c index e246419..2c296dc 100644 --- a/src/mainboard/google/sarien/ramstage.c +++ b/src/mainboard/google/sarien/ramstage.c @@ -15,12 +15,12 @@
#include <arch/acpi.h> #include <drivers/vpd/vpd.h> -#include <ec/google/wilco/commands.h> #include <smbios.h> #include <soc/gpio.h> #include <soc/ramstage.h> #include <variant/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> +#include <variant/ec.h>
#if CONFIG(GENERATE_SMBIOS_TABLES) #define VPD_KEY_SYSTEM_SERIAL "serial_number" @@ -70,11 +70,6 @@ cnl_configure_pads(gpio_table, num_gpios); }
-void mainboard_post(uint8_t value) -{ - wilco_ec_save_post_code(value); -} - static void mainboard_enable(struct device *dev) { dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; diff --git a/src/mainboard/google/sarien/romstage.c b/src/mainboard/google/sarien/romstage.c index 20eee7f..fe8d03e 100644 --- a/src/mainboard/google/sarien/romstage.c +++ b/src/mainboard/google/sarien/romstage.c @@ -16,6 +16,7 @@ #include <ec/google/wilco/romstage.h> #include <soc/cnl_memcfg_init.h> #include <soc/romstage.h> +#include <variant/ec.h>
static const struct cnl_mb_cfg memcfg = { /* Access memory info through SMBUS. */ diff --git a/src/mainboard/google/sarien/variants/sarien/include/variant/ec.h b/src/mainboard/google/sarien/variants/sarien/include/variant/ec.h index 01a17b5..9358deb 100644 --- a/src/mainboard/google/sarien/variants/sarien/include/variant/ec.h +++ b/src/mainboard/google/sarien/variants/sarien/include/variant/ec.h @@ -18,6 +18,7 @@
#include <soc/gpe.h> #include <soc/gpio.h> +#include <console/console.h>
/* EC wake pin */ #define EC_WAKE_PIN GPE0_DW1_12 @@ -31,4 +32,6 @@ /* Enable DPTF */ #define EC_ENABLE_DPTF
+void mainboard_post(uint8_t value); + #endif
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/33047
to look at the new patch set (#2).
Change subject: mb/google/sarien: Send post code to the EC ......................................................................
mb/google/sarien: Send post code to the EC
Use the mainboard post code hook to inform the wilco EC driver of the every stage.
BUG=b:124401932,b:133466714,b:133600566 BRANCH=sarien TEST=Remove DIMM module, confirm diagnostic LED pattern for memory failure (2 amber, 4 white).
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: Ic71e4a6e62b63ca2fd189957c4d6f49b61b934de --- M src/mainboard/google/sarien/Makefile.inc A src/mainboard/google/sarien/ec.c M src/mainboard/google/sarien/ramstage.c M src/mainboard/google/sarien/romstage.c M src/mainboard/google/sarien/variants/sarien/include/variant/ec.h 5 files changed, 32 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/33047/2
Duncan Laurie has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33047 )
Change subject: mb/google/sarien: Send post code to the EC ......................................................................
Patch Set 6: Code-Review+2
I verified that removing the DIMMs results in the expected 2 amber 4 white flashes.
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33047 )
Change subject: mb/google/sarien: Send post code to the EC ......................................................................
Patch Set 6:
Patch Set 6: Code-Review+2
I verified that removing the DIMMs results in the expected 2 amber 4 white flashes.
verify pass in our side as well.
Frank Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33047 )
Change subject: mb/google/sarien: Send post code to the EC ......................................................................
Patch Set 6: Code-Review+1
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33047 )
Change subject: mb/google/sarien: Send post code to the EC ......................................................................
Patch Set 6: Code-Review+2
Furquan Shaikh has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/33047 )
Change subject: mb/google/sarien: Send post code to the EC ......................................................................
mb/google/sarien: Send post code to the EC
Use the mainboard post code hook to inform the wilco EC driver of the every stage.
BUG=b:124401932,b:133466714,b:133600566 BRANCH=sarien TEST=Remove DIMM module, confirm diagnostic LED pattern for memory failure (2 amber, 4 white).
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Signed-off-by: Duncan Laurie dlaurie@google.com Change-Id: Ic71e4a6e62b63ca2fd189957c4d6f49b61b934de Reviewed-on: https://review.coreboot.org/c/coreboot/+/33047 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Duncan Laurie dlaurie@chromium.org Reviewed-by: Frank Wu frank_wu@compal.corp-partner.google.com Reviewed-by: Furquan Shaikh furquan@google.com --- M src/mainboard/google/sarien/Makefile.inc A src/mainboard/google/sarien/ec.c M src/mainboard/google/sarien/ramstage.c 3 files changed, 28 insertions(+), 6 deletions(-)
Approvals: build bot (Jenkins): Verified Duncan Laurie: Looks good to me, approved Furquan Shaikh: Looks good to me, approved Frank Wu: Looks good to me, but someone else must approve
diff --git a/src/mainboard/google/sarien/Makefile.inc b/src/mainboard/google/sarien/Makefile.inc index 6fd23ce..7c37bc9 100644 --- a/src/mainboard/google/sarien/Makefile.inc +++ b/src/mainboard/google/sarien/Makefile.inc @@ -29,5 +29,10 @@
ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB) += hda_verb.c
+bootblock-$(CONFIG_EC_GOOGLE_WILCO) += ec.c +ramstage-$(CONFIG_EC_GOOGLE_WILCO) += ec.c +romstage-$(CONFIG_EC_GOOGLE_WILCO) += ec.c +verstage-$(CONFIG_EC_GOOGLE_WILCO) += ec.c + subdirs-y += variants/$(VARIANT_DIR) CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include diff --git a/src/mainboard/google/sarien/ec.c b/src/mainboard/google/sarien/ec.c new file mode 100644 index 0000000..fd8e84f --- /dev/null +++ b/src/mainboard/google/sarien/ec.c @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <ec/google/wilco/commands.h> +#include <variant/ec.h> + +void mainboard_post(uint8_t value) +{ + wilco_ec_save_post_code(value); +} diff --git a/src/mainboard/google/sarien/ramstage.c b/src/mainboard/google/sarien/ramstage.c index e246419..1d22046 100644 --- a/src/mainboard/google/sarien/ramstage.c +++ b/src/mainboard/google/sarien/ramstage.c @@ -15,7 +15,6 @@
#include <arch/acpi.h> #include <drivers/vpd/vpd.h> -#include <ec/google/wilco/commands.h> #include <smbios.h> #include <soc/gpio.h> #include <soc/ramstage.h> @@ -70,11 +69,6 @@ cnl_configure_pads(gpio_table, num_gpios); }
-void mainboard_post(uint8_t value) -{ - wilco_ec_save_post_code(value); -} - static void mainboard_enable(struct device *dev) { dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
-
Duncan Laurie (Code Review) -
EricR Lai (Code Review)
-
Frank Wu (Code Review)
-
Furquan Shaikh (Code Review)