coreboot-gerrit April 2019

coreboot-gerrit@coreboot.org

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1219 discussions

Change in ...coreboot[master]: nb/intel/sandybridge: Drop iommu.c and rename functions
by Patrick Rudolph (Code Review) 03 Apr '19

03 Apr '19

Hello Patrick Rudolph, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/32068 to look at the new patch set (#4). Change subject: nb/intel/sandybridge: Drop iommu.c and rename functions ...................................................................... nb/intel/sandybridge: Drop iommu.c and rename functions * Move the contents of iommu.c to early_init.c. * Name the functions like done in intel/soc/common. * Move PAMx register setup to own function Preparations for integration in soc/intel/common/* Tested on Lenovo T520 (Intel Sandy Bridge). Still boots to OS, no errors visible in dmesg. Change-Id: I3ec395bf6722bceb84316e92733dcfcd7a093639 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/northbridge/intel/sandybridge/Makefile.inc M src/northbridge/intel/sandybridge/early_init.c D src/northbridge/intel/sandybridge/iommu.c M src/northbridge/intel/sandybridge/romstage.c M src/northbridge/intel/sandybridge/sandybridge.h 5 files changed, 47 insertions(+), 63 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/32068/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/32068 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3ec395bf6722bceb84316e92733dcfcd7a093639 Gerrit-Change-Number: 32068 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: [WIP]mb/google/sarien: Fix touch screen power leakage during s0ix
by Roy Mingi Park (Code Review) 03 Apr '19

03 Apr '19

Roy Mingi Park has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32165 Change subject: [WIP]mb/google/sarien: Fix touch screen power leakage during s0ix ...................................................................... [WIP]mb/google/sarien: Fix touch screen power leakage during s0ix Change-Id: Ie64d6ea673b069363227750198c59ab3a163094b Signed-off-by: Roy Mingi Park <roy.mingi.park(a)intel.com> --- M src/mainboard/google/sarien/variants/arcada/devicetree.cb 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/32165/1 diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index 4bf3736..f519a15 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -304,6 +304,7 @@ register "generic.probed" = "1" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E7)" register "generic.enable_delay_ms" = "5" + register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)" register "generic.has_power_resource" = "1" register "generic.disable_gpio_export_in_crs" = "1" register "hid_desc_reg_offset" = "0x1" -- To view, visit https://review.coreboot.org/c/coreboot/+/32165 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie64d6ea673b069363227750198c59ab3a163094b Gerrit-Change-Number: 32165 Gerrit-PatchSet: 1 Gerrit-Owner: Roy Mingi Park <roy.mingi.park(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: src/drivers/intel/fsp2_0: Added FSP_S component to VBOOT Stage Verifi...
by build bot (Jenkins) (Code Review) 02 Apr '19

02 Apr '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32155 ) Change subject: src/drivers/intel/fsp2_0: Added FSP_S component to VBOOT Stage Verification. FSP_S component will be verified in RAMSTAGE. ...................................................................... Patch Set 1: (6 comments) https://review.coreboot.org/#/c/32155/1/src/drivers/intel/fsp2_0/silicon_in… File src/drivers/intel/fsp2_0/silicon_init.c: https://review.coreboot.org/#/c/32155/1/src/drivers/intel/fsp2_0/silicon_in… PS1, Line 29: * overriden by VBOOT mechanism. 'overriden' may be misspelled - perhaps 'overridden'? https://review.coreboot.org/#/c/32155/1/src/drivers/intel/fsp2_0/silicon_in… PS1, Line 32: const char * name) "foo * bar" should be "foo *bar" https://review.coreboot.org/#/c/32155/1/src/drivers/intel/fsp2_0/silicon_in… PS1, Line 34: /* no op */ code indent should use tabs where possible https://review.coreboot.org/#/c/32155/1/src/drivers/intel/fsp2_0/silicon_in… PS1, Line 43: printk (BIOS_ERR, "ERROR: Unable to locate %s\n", prog_name(fsps)); line over 80 characters https://review.coreboot.org/#/c/32155/1/src/drivers/intel/fsp2_0/silicon_in… PS1, Line 43: printk (BIOS_ERR, "ERROR: Unable to locate %s\n", prog_name(fsps)); space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/32155/1/src/drivers/intel/fsp2_0/silicon_in… PS1, Line 113: trailing whitespace -- To view, visit https://review.coreboot.org/c/coreboot/+/32155 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifefad96b54388143fecb56f0402c3b627ae6350d Gerrit-Change-Number: 32155 Gerrit-PatchSet: 1 Gerrit-Owner: Amol N Sukerkar <amol.n.sukerkar(a)intel.com> Gerrit-Reviewer: Amol N Sukerkar <amol.n.sukerkar(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 02 Apr 2019 21:45:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: libpayload: Fix CONFIG_LP_DEBUG_MALLOC for 64-bit archs
by Julius Werner (Code Review) 02 Apr '19

02 Apr '19

Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/14921 ) Change subject: libpayload: Fix CONFIG_LP_DEBUG_MALLOC for 64-bit archs ...................................................................... Patch Set 6: *ping* Hung-Te, do you still want this? -- To view, visit https://review.coreboot.org/c/coreboot/+/14921 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib54ebc3cfba99f372690365b78c7ceb372c0bd45 Gerrit-Change-Number: 14921 Gerrit-PatchSet: 6 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philippe Mathieu-Daudé <f4bug(a)amsat.org> Gerrit-Reviewer: Uwe Hermann <uwe(a)hermann-uwe.de> Gerrit-Reviewer: You-Cheng Syu <youcheng(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 02 Apr 2019 21:34:27 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: Patch SSDTs into qemu, and add VPD area to the fmap for q35 as a proo...
by John Looney (Code Review) 02 Apr '19

02 Apr '19

John Looney has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32081 Change subject: Patch SSDTs into qemu, and add VPD area to the fmap for q35 as a proof of concept ...................................................................... Patch SSDTs into qemu, and add VPD area to the fmap for q35 as a proof of concept Change-Id: I8c31fa79e13be237a752f47e72a6a7025fe9dffd --- M src/arch/x86/acpi.c M src/mainboard/emulation/qemu-i440fx/fw_cfg.c M src/mainboard/emulation/qemu-i440fx/fw_cfg.h M src/mainboard/emulation/qemu-q35/Kconfig 4 files changed, 21 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/32081/1 diff --git a/src/arch/x86/acpi.c b/src/arch/x86/acpi.c index f08a401..7bbbd2f 100644 --- a/src/arch/x86/acpi.c +++ b/src/arch/x86/acpi.c @@ -38,7 +38,6 @@ */ #include <console/console.h> -#include <string.h> #include <arch/acpi.h> #include <arch/acpi_ivrs.h> #include <arch/acpigen.h> diff --git a/src/mainboard/emulation/qemu-i440fx/fw_cfg.c b/src/mainboard/emulation/qemu-i440fx/fw_cfg.c index 3acb11e..2c5124b 100644 --- a/src/mainboard/emulation/qemu-i440fx/fw_cfg.c +++ b/src/mainboard/emulation/qemu-i440fx/fw_cfg.c @@ -225,6 +225,8 @@ BiosLinkerLoaderEntry *s; unsigned long *addrs, current; uint8_t *ptr; + acpi_rsdp_t *rsdp = NULL; + acpi_header_t *ssdt; int i, j, src, dst, max; if (fw_cfg_check_file(&f, "etc/table-loader")) @@ -251,6 +253,10 @@ printk(BIOS_DEBUG, "QEMU: loading \"%s\" to 0x%lx (len %d)\n", s[i].alloc.file, current, f.size); + if(!strncmp(s[i].alloc.file, "etc/acpi/rsdp", 13)) { + printk(BIOS_DEBUG, "Found RSDP at 0x%lx\n", current); + rsdp = (acpi_rsdp_t *) current; + } fw_cfg_get(f.select, (void *)current, f.size); addrs[i] = current; current += f.size; @@ -322,6 +328,16 @@ }; } + if(rsdp) { + ssdt = (acpi_header_t *)current; + acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); + if (ssdt->length > sizeof(acpi_header_t)) { + current += ssdt->length; + acpi_add_table(rsdp, ssdt); + current = acpi_align_current(current); + } + } + printk(BIOS_DEBUG, "QEMU: loaded ACPI tables from fw_cfg.\n"); free(s); free(addrs); diff --git a/src/mainboard/emulation/qemu-i440fx/fw_cfg.h b/src/mainboard/emulation/qemu-i440fx/fw_cfg.h index 975801b..070d61d 100644 --- a/src/mainboard/emulation/qemu-i440fx/fw_cfg.h +++ b/src/mainboard/emulation/qemu-i440fx/fw_cfg.h @@ -14,6 +14,7 @@ #define FW_CFG_H #include "fw_cfg_if.h" +int is_rsdp(char *); void fw_cfg_get(uint16_t entry, void *dst, int dstlen); int fw_cfg_check_file(FWCfgFile *file, const char *name); int fw_cfg_max_cpus(void); diff --git a/src/mainboard/emulation/qemu-q35/Kconfig b/src/mainboard/emulation/qemu-q35/Kconfig index 815b93b..0672092 100644 --- a/src/mainboard/emulation/qemu-q35/Kconfig +++ b/src/mainboard/emulation/qemu-q35/Kconfig @@ -54,4 +54,8 @@ hex default 0x4000 +config FMDFILE + string + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/board.fmd" + endif # BOARD_EMULATION_QEMU_X86_Q35 -- To view, visit https://review.coreboot.org/c/coreboot/+/32081 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8c31fa79e13be237a752f47e72a6a7025fe9dffd Gerrit-Change-Number: 32081 Gerrit-PatchSet: 1 Gerrit-Owner: John Looney <john.looney(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: Patch an SSDT onto the end of the ACPI tables built for qemu-i440fx, ...
by John Looney (Code Review) 02 Apr '19

02 Apr '19

John Looney has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32143 Change subject: Patch an SSDT onto the end of the ACPI tables built for qemu-i440fx, and thus qemu-q35 also. ...................................................................... Patch an SSDT onto the end of the ACPI tables built for qemu-i440fx, and thus qemu-q35 also. This will allow qemu to setup cbmem, and allow VPD variables to be accessible from operating systems booted by qemu. This has been tested by booting a qemu-q35 instance from a coreboot image with a VPD partition defined in the fmap. On booting, /sys/firmware/vpd/ro existed as it does on real hardware. A subsequent commit will contain default fmaps for qemu images, which will include small VPD partitions. Change-Id: I25e8f7876eb90384220ba95ef547911b92c74dfd --- M src/mainboard/emulation/qemu-i440fx/Kconfig M src/mainboard/emulation/qemu-i440fx/fw_cfg.c M src/mainboard/emulation/qemu-q35/Kconfig 3 files changed, 39 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/32143/1 diff --git a/src/mainboard/emulation/qemu-i440fx/Kconfig b/src/mainboard/emulation/qemu-i440fx/Kconfig index 23526f9..f9577b6 100644 --- a/src/mainboard/emulation/qemu-i440fx/Kconfig +++ b/src/mainboard/emulation/qemu-i440fx/Kconfig @@ -46,4 +46,8 @@ hex default 0x4000 +config FMDFILE + string + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/board.fmd" + endif # BOARD_EMULATION_QEMU_X86_I440FX diff --git a/src/mainboard/emulation/qemu-i440fx/fw_cfg.c b/src/mainboard/emulation/qemu-i440fx/fw_cfg.c index 3acb11e..1ee8b72 100644 --- a/src/mainboard/emulation/qemu-i440fx/fw_cfg.c +++ b/src/mainboard/emulation/qemu-i440fx/fw_cfg.c @@ -22,8 +22,8 @@ #include "fw_cfg.h" #include "fw_cfg_if.h" -#define FW_CFG_PORT_CTL 0x0510 -#define FW_CFG_PORT_DATA 0x0511 +#define FW_CFG_PORT_CTL 0x0510 +#define FW_CFG_PORT_DATA 0x0511 static int fw_cfg_detected; @@ -37,7 +37,7 @@ fw_cfg_get(FW_CFG_SIGNATURE, sig, sizeof(sig)); detected = memcmp(sig, qsig, 4) == 0; printk(BIOS_INFO, "QEMU: firmware config interface %s\n", - detected ? "detected" : "not found"); + detected ? "detected" : "not found"); fw_cfg_detected = detected + 1; } return fw_cfg_detected - 1; @@ -97,7 +97,7 @@ } static int fw_cfg_e820_read(FwCfgE820Entry *entry, uint32_t *size, - uint32_t *pos) + uint32_t *pos) { if (*pos + sizeof(*entry) > *size) return -1; @@ -209,8 +209,8 @@ typedef struct BiosLinkerLoaderEntry BiosLinkerLoaderEntry; enum { - BIOS_LINKER_LOADER_COMMAND_ALLOCATE = 0x1, - BIOS_LINKER_LOADER_COMMAND_ADD_POINTER = 0x2, + BIOS_LINKER_LOADER_COMMAND_ALLOCATE = 0x1, + BIOS_LINKER_LOADER_COMMAND_ADD_POINTER = 0x2, BIOS_LINKER_LOADER_COMMAND_ADD_CHECKSUM = 0x3, }; @@ -225,6 +225,8 @@ BiosLinkerLoaderEntry *s; unsigned long *addrs, current; uint8_t *ptr; + acpi_rsdp_t *rsdp = NULL; + acpi_header_t *ssdt; int i, j, src, dst, max; if (fw_cfg_check_file(&f, "etc/table-loader")) @@ -251,13 +253,18 @@ printk(BIOS_DEBUG, "QEMU: loading \"%s\" to 0x%lx (len %d)\n", s[i].alloc.file, current, f.size); + if (!strncmp(s[i].alloc.file, "etc/acpi/rsdp", 13)) { + printk(BIOS_DEBUG, "Found RSDP at 0x%lx\n", current); + rsdp = (acpi_rsdp_t *)current; + } fw_cfg_get(f.select, (void *)current, f.size); addrs[i] = current; current += f.size; break; case BIOS_LINKER_LOADER_COMMAND_ADD_POINTER: - src = -1; dst = -1; + src = -1; + dst = -1; for (j = 0; j < i; j++) { if (s[j].command != BIOS_LINKER_LOADER_COMMAND_ALLOCATE) continue; @@ -317,11 +324,21 @@ default: printk(BIOS_DEBUG, "QEMU: acpi: unknown script cmd 0x%x @ %p\n", - s[i].command, s+i); + s[i].command, s + i); goto err; }; } + if (rsdp) { + ssdt = (acpi_header_t *)current; + acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); + if (ssdt->length > sizeof(acpi_header_t)) { + current += ssdt->length; + acpi_add_table(rsdp, ssdt); + current = acpi_align_current(current); + } + } + printk(BIOS_DEBUG, "QEMU: loaded ACPI tables from fw_cfg.\n"); free(s); free(addrs); @@ -360,8 +377,7 @@ insb(FW_CFG_PORT_DATA, &entry, sizeof(entry)); buf = malloc(entry.length - sizeof(entry)); insb(FW_CFG_PORT_DATA, buf, entry.length - sizeof(entry)); - if (entry.headertype == SMBIOS_FIELD_ENTRY && - entry.tabletype == 1) { + if (entry.headertype == SMBIOS_FIELD_ENTRY && entry.tabletype == 1) { switch (entry.fieldoffset) { case offsetof(struct smbios_type1, manufacturer): type1_manufacturer = strdup(buf); @@ -393,10 +409,10 @@ int l, count = 0; char *s; - t0 = (void*)current; + t0 = (void *)current; current += t0->length; for (;;) { - s = (void*)current; + s = (void *)current; l = strlen(s); if (!l) return current + (count ? 1 : 2); @@ -435,14 +451,14 @@ * see src/arch/x86/boot/smbios.c), then find type0 table. */ for (i = 0; i < 16384; i++) { - str = (char*)(*current - i); + str = (char *)(*current - i); if (strcmp(str, "coreboot") == 0) break; } if (i == 16384) return 0; i += sizeof(struct smbios_type0) - 2; - t0 = (struct smbios_type0*)(*current - i); + t0 = (struct smbios_type0 *)(*current - i); if (t0->type != SMBIOS_BIOS_INFORMATION || t0->handle != 0) return 0; printk(BIOS_DEBUG, "QEMU: coreboot type0 table found at 0x%lx.\n", @@ -457,7 +473,7 @@ fw_cfg_get(f.select, (void *)start, f.size); end = start; do { - t0 = (struct smbios_type0*)end; + t0 = (struct smbios_type0 *)end; if (t0->type == SMBIOS_END_OF_TABLE) break; end = smbios_next(end); diff --git a/src/mainboard/emulation/qemu-q35/Kconfig b/src/mainboard/emulation/qemu-q35/Kconfig index 815b93b..0672092 100644 --- a/src/mainboard/emulation/qemu-q35/Kconfig +++ b/src/mainboard/emulation/qemu-q35/Kconfig @@ -54,4 +54,8 @@ hex default 0x4000 +config FMDFILE + string + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/board.fmd" + endif # BOARD_EMULATION_QEMU_X86_Q35 -- To view, visit https://review.coreboot.org/c/coreboot/+/32143 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I25e8f7876eb90384220ba95ef547911b92c74dfd Gerrit-Change-Number: 32143 Gerrit-PatchSet: 1 Gerrit-Owner: John Looney <john.looney(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: TEST
by HAOUAS Elyes (Code Review) 02 Apr '19

02 Apr '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32128 Change subject: TEST ...................................................................... TEST Change-Id: Id50a0d3c875c9d71a78b22cba1a0cc9410786c91 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/google/smaug/romstage.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/32128/1 diff --git a/src/mainboard/google/smaug/romstage.c b/src/mainboard/google/smaug/romstage.c index fd7c07f..affb04f 100644 --- a/src/mainboard/google/smaug/romstage.c +++ b/src/mainboard/google/smaug/romstage.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +/* Just for test */ #include <delay.h> #include <soc/addressmap.h> #include <device/i2c_simple.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/32128 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id50a0d3c875c9d71a78b22cba1a0cc9410786c91 Gerrit-Change-Number: 32128 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: nb/intel/i945: Correct SLP_S4# comment
by HAOUAS Elyes (Code Review) 02 Apr '19

02 Apr '19

HAOUAS Elyes has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/28395 ) Change subject: nb/intel/i945: Correct SLP_S4# comment ...................................................................... Abandoned TODO: move the sb code to southbridge -- To view, visit https://review.coreboot.org/c/coreboot/+/28395 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I86df0df5337397d2c23ca311ecae1c8a38eb32f0 Gerrit-Change-Number: 28395 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: abandon

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Change in ...coreboot[master]: fsp platforms: Notify FSP after PCI device init
by Martin Roth (Code Review) 02 Apr '19

02 Apr '19

Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/10100 ) Change subject: fsp platforms: Notify FSP after PCI device init ...................................................................... Patch Set 4: I don't remember all of the issues surrounding this, but I seem to recall that it needed to be in this spot. This might fix one issue on minnowmax, but this is common code, so might break things on other platforms. I'd advise caution in moving this. -- To view, visit https://review.coreboot.org/c/coreboot/+/10100 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia6508c07aa53ba436bb5899a48ecd64a117524e5 Gerrit-Change-Number: 10100 Gerrit-PatchSet: 4 Gerrit-Owner: David Imhoff <dimhoff_devel(a)xs4all.nl> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Ben Gardner <gardner.ben(a)gmail.com> Gerrit-Reviewer: David Imhoff <dimhoff_devel(a)xs4all.nl> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Name of user not set #1000214 Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 02 Apr 2019 17:03:56 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: payloads/tianocore: Don't fail on resetting boot logo
by Matt DeVillier (Code Review) 02 Apr '19

02 Apr '19

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32133 Change subject: payloads/tianocore: Don't fail on resetting boot logo ...................................................................... payloads/tianocore: Don't fail on resetting boot logo If using a commit/branch which doesn't use a boot logo, we don't want the build to fail unnecessarily Test: build with upstream Tianocore commit hash, avoid failure after successful compilation. Change-Id: Ic41bacbb97926e9538f434aecc0f0eebc5f6326f Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M payloads/external/tianocore/Makefile 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/32133/1 diff --git a/payloads/external/tianocore/Makefile b/payloads/external/tianocore/Makefile index 2c7439c..d5e26de 100644 --- a/payloads/external/tianocore/Makefile +++ b/payloads/external/tianocore/Makefile @@ -100,7 +100,7 @@ fi; \ build $(BUILD_STR); \ mv $(project_dir)/Build/CorebootPayloadPkg*/*/FV/UEFIPAYLOAD.fd $(project_dir)/Build/UEFIPAYLOAD.fd; \ - git checkout CorebootPayloadPkg/Logo/Logo.bmp > /dev/null 2>&1 + git checkout CorebootPayloadPkg/Logo/Logo.bmp > /dev/null 2>&1 | true clean: test -d $(project_dir) && (cd $(project_dir); rm -rf Build; rm -f Conf/tools_def.txt) || exit 0 -- To view, visit https://review.coreboot.org/c/coreboot/+/32133 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic41bacbb97926e9538f434aecc0f0eebc5f6326f Gerrit-Change-Number: 32133 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

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coreboot-gerrit April 2019