coreboot-gerrit April 2019

coreboot-gerrit@coreboot.org

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Change in ...coreboot[master]: soc/intel/braswell: Correct serial IRQ support
by Michał Żygowski (Code Review) 03 Apr '19

03 Apr '19

Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29398 ) Change subject: soc/intel/braswell: Correct serial IRQ support ...................................................................... Patch Set 12: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29398 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7844cad69dc0563fa6109d779d0afb7c2edd7245 Gerrit-Change-Number: 29398 Gerrit-PatchSet: 12 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Wed, 03 Apr 2019 14:14:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/lenovo/r500: Add mainboard
by Patrick Rudolph (Code Review) 03 Apr '19

03 Apr '19

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/28644 ) Change subject: mb/lenovo/r500: Add mainboard ...................................................................... Patch Set 8: Code-Review+1 (1 comment) The VBT wasn't added for other variants yet, as there are too different panels. What's the state on R500? https://review.coreboot.org/#/c/28644/8/src/mainboard/lenovo/t400/variants/… File src/mainboard/lenovo/t400/variants/t400/overridetree.cb: https://review.coreboot.org/#/c/28644/8/src/mainboard/lenovo/t400/variants/… PS8, Line 6: chip drivers/lenovo/hybrid_graphics why is there no hybridge graphics enabled on R500. Some models ship with an ATI GPU. -- To view, visit https://review.coreboot.org/c/coreboot/+/28644 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9e129b2e916acdf2b8534fa9d8d2cfc8f64f5815 Gerrit-Change-Number: 28644 Gerrit-PatchSet: 8 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 03 Apr 2019 14:05:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: vendorcode/eltan: Add vendor code for measured and verified boot
by Frans Hendriks (Code Review) 03 Apr '19

03 Apr '19

Hello Philipp Deppenwiese, build bot (Jenkins), Martin Roth, Patrick Georgi, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/30218 to look at the new patch set (#10). Change subject: vendorcode/eltan: Add vendor code for measured and verified boot ...................................................................... vendorcode/eltan: Add vendor code for measured and verified boot This patch contains the general files for the vendorcode/eltan that has been uploaded recently: - Add eltan directory to vendorcode - Add documentation about the support in the vendorcode directories. - Add the Makefile.inc and Kconfig for the vendorcode/eltan and vendorcode/eltan/security BUG=N/A TEST=Created verified binary and verify logging on Portwell PQ-M107 Change-Id: Ic1d5a21d40b6a31886777e8e9fe7b28c860f1a80 Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- A Documentation/vendorcode/eltan/index.md A Documentation/vendorcode/eltan/security.md M src/vendorcode/Makefile.inc A src/vendorcode/eltan/Kconfig A src/vendorcode/eltan/Makefile.inc A src/vendorcode/eltan/security/Kconfig A src/vendorcode/eltan/security/Makefile.inc 7 files changed, 127 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/30218/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/30218 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic1d5a21d40b6a31886777e8e9fe7b28c860f1a80 Gerrit-Change-Number: 30218 Gerrit-PatchSet: 10 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Patrick Rudolph Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: mb/google/sarien/variants/sarien: Update thermal configuration for DPTF
by John Su (Code Review) 03 Apr '19

03 Apr '19

John Su has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32118 Change subject: mb/google/sarien/variants/sarien: Update thermal configuration for DPTF ...................................................................... mb/google/sarien/variants/sarien: Update thermal configuration for DPTF Follow thermal table for second tunning. BUG=b:129509918 TEST=Built and tested on sarien system Change-Id: I64844b84891dc3ab7abe9378cdca5dcf57b3e433 Signed-off-by: John Su <john_su(a)compal.corp-partner.google.com> --- M src/mainboard/google/sarien/variants/sarien/devicetree.cb M src/mainboard/google/sarien/variants/sarien/include/variant/acpi/dptf.asl 2 files changed, 10 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/32118/1 diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index 2714b60..4544b0f 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -42,7 +42,7 @@ register "SlowSlewRateForGt" = "2" register "SlowSlewRateForSa" = "2" register "SlowSlewRateForFivr" = "2" - register "tdp_pl1_override" = "25" + register "tdp_pl1_override" = "15" register "tdp_pl2_override" = "51" register "Device4Enable" = "1" # Enable eDP device diff --git a/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/dptf.asl b/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/dptf.asl index be052f8..0cdbcd1 100644 --- a/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/dptf.asl @@ -13,7 +13,7 @@ * GNU General Public License for more details. */ -#define DPTF_CPU_PASSIVE 95 +#define DPTF_CPU_PASSIVE 99 #define DPTF_CPU_CRITICAL 105 /* Skin Sensor for CPU VR temperature monitor */ @@ -25,7 +25,7 @@ /* Memory Sensor for DDR temperature monitor */ #define DPTF_TSR1_SENSOR_ID 2 #define DPTF_TSR1_SENSOR_NAME "DDR" -#define DPTF_TSR1_PASSIVE 56 +#define DPTF_TSR1_PASSIVE 55 #define DPTF_TSR1_CRITICAL 100 /* M.2 Sensor for Ambient temperature monitor */ @@ -39,16 +39,16 @@ Name (DTRT, Package () { /* CPU Throttle Effect on CPU */ - Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 5000, 10, 0, 0, 0, 0 }, + Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 250, 10, 0, 0, 0, 0 }, /* CPU Throttle Effect on Skin (TSR0) */ - Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 200, 10, 0, 0, 0, 0 }, + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 250, 10, 0, 0, 0, 0 }, /* CPU Throttle Effect on DDR (TSR1) */ - Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 2000, 10, 0, 0, 0, 0 }, + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 250, 10, 0, 0, 0, 0 }, /* CPU Throttle Effect on Ambient (TSR2) */ - Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR2, 200, 10, 0, 0, 0, 0 }, + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR2, 250, 10, 0, 0, 0, 0 }, }) Name (MPPC, Package () @@ -56,15 +56,15 @@ 0x2, /* Revision */ Package () { /* Power Limit 1 */ 0, /* PowerLimitIndex, 0 for Power Limit 1 */ - 3000, /* PowerLimitMinimum */ - 25000, /* PowerLimitMaximum */ + 5000, /* PowerLimitMinimum */ + 15000, /* PowerLimitMaximum */ 10000, /* TimeWindowMinimum */ 10000, /* TimeWindowMaximum */ 100 /* StepSize */ }, Package () { /* Power Limit 2 */ 1, /* PowerLimitIndex, 1 for Power Limit 2 */ - 3000, /* PowerLimitMinimum */ + 5000, /* PowerLimitMinimum */ 51000, /* PowerLimitMaximum */ 28000, /* TimeWindowMinimum */ 28000, /* TimeWindowMaximum */ -- To view, visit https://review.coreboot.org/c/coreboot/+/32118 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I64844b84891dc3ab7abe9378cdca5dcf57b3e433 Gerrit-Change-Number: 32118 Gerrit-PatchSet: 1 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/poppy/variant/atlas: change speaker IV channels
by Jenny Tc (Code Review) 03 Apr '19

03 Apr '19

Jenny Tc has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31637 Change subject: mb/google/poppy/variant/atlas: change speaker IV channels ...................................................................... mb/google/poppy/variant/atlas: change speaker IV channels Change speaker IV channels for max98373 to match with 24 bit topology firmware BUG=b:110795132 BRANCH=none TEST=Verify playback after flashing CQ-DEPEND=*806750 Change-Id: Ib572e6ae219f899f332dcdb0661eb4eee36fc019 Signed-off-by: Jenny TC <jenny.tc(a)intel.com> --- M src/mainboard/google/poppy/variants/atlas/devicetree.cb 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/31637/1 diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb index 5b49884..d653993 100644 --- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb +++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb @@ -310,16 +310,16 @@ device pci 19.1 off end # I2C #5 device pci 19.2 on chip drivers/i2c/max98373 - register "vmon_slot_no" = "4" - register "imon_slot_no" = "5" + register "vmon_slot_no" = "1" + register "imon_slot_no" = "0" register "uid" = "0" register "desc" = ""RIGHT SPEAKER AMP"" register "name" = ""MAXR"" device i2c 31 on end end chip drivers/i2c/max98373 - register "vmon_slot_no" = "6" - register "imon_slot_no" = "7" + register "vmon_slot_no" = "3" + register "imon_slot_no" = "2" register "uid" = "1" register "desc" = ""LEFT SPEAKER AMP"" register "name" = ""MAXL"" -- To view, visit https://review.coreboot.org/c/coreboot/+/31637 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib572e6ae219f899f332dcdb0661eb4eee36fc019 Gerrit-Change-Number: 31637 Gerrit-PatchSet: 1 Gerrit-Owner: Jenny Tc <jenny.tc(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/poppy/variant/nocturne: change speaker IV channels
by Jenny Tc (Code Review) 03 Apr '19

03 Apr '19

Jenny Tc has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31636 Change subject: mb/google/poppy/variant/nocturne: change speaker IV channels ...................................................................... mb/google/poppy/variant/nocturne: change speaker IV channels Change speaker IV channels for max98373 to match with 24 bit topology firmware BUG=b:110795132 BRANCH=none TEST=Verify playback after flashing CQ-DEPEND=*806750 Change-Id: I5d94d473b25b23e206c998ca9bd8bd776b76d2bb Signed-off-by: Jenny TC <jenny.tc(a)intel.com> --- M src/mainboard/google/poppy/variants/nocturne/devicetree.cb 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/31636/1 diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb index 4d9403c..5b84c96 100644 --- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb @@ -403,16 +403,16 @@ end # I2C #5 device pci 19.2 on chip drivers/i2c/max98373 - register "vmon_slot_no" = "4" - register "imon_slot_no" = "5" + register "vmon_slot_no" = "1" + register "imon_slot_no" = "0" register "uid" = "0" register "desc" = ""RIGHT SPEAKER AMP"" register "name" = ""MAXR"" device i2c 32 on end end chip drivers/i2c/max98373 - register "vmon_slot_no" = "6" - register "imon_slot_no" = "7" + register "vmon_slot_no" = "3" + register "imon_slot_no" = "2" register "uid" = "1" register "desc" = ""LEFT SPEAKER AMP"" register "name" = ""MAXL"" -- To view, visit https://review.coreboot.org/c/coreboot/+/31636 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5d94d473b25b23e206c998ca9bd8bd776b76d2bb Gerrit-Change-Number: 31636 Gerrit-PatchSet: 1 Gerrit-Owner: Jenny Tc <jenny.tc(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: IntelFB: Add support for Intel font driver
by Maulik V Vaghela (Code Review) 03 Apr '19

03 Apr '19

Maulik V Vaghela has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/30182 ) Change subject: IntelFB: Add support for Intel font driver ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/30182 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I70715d9c84dae2d0efa1631649ce27ea3c39e237 Gerrit-Change-Number: 30182 Gerrit-PatchSet: 3 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: abandon

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Change in ...coreboot[master]: mb/google/fizz/variants/karma: Clear GPP_B4 when entering S5
by David Wu (Code Review) 03 Apr '19

03 Apr '19

David Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29796 ) Change subject: mb/google/fizz/variants/karma: Clear GPP_B4 when entering S5 ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/#/c/29796/2//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/29796/2//COMMIT_MSG@11 PS2, Line 11: BUG=b:124197348 > The issue is not accessible to all reviewers, so please add a summary of the issue to the commit mes […] See comment3 below. for scenario 2, need setting GPP_B4 to low in S5. Thanks. ================================== Please refer to the attached photos for the power sequence requirement of LG touch screen . scenario 1 : power on Tuning the power sequence by hardware R/C delay as the attached circuit The sequence spec : Vlcd must lead Vusb more than 60 ms . scenario 2 : power off Need firmware's help to turn off TS power by pulling low the "PCH_TS_EN" pin (GPP_B4) when received "power off" command . The sequence spec : Vlcd must lag Vusb more than 0 ms . scenario 3: sleep mode/suspend (S3) In order to keep the system can be waked up by touch screen so must let Vusb be kept . The firmware don't need to do anything for touch screen power during s3 . The waveforms after tuning were attached as well , please have a look . Blue color - Vusb Yellow color - Vlcd -- To view, visit https://review.coreboot.org/c/coreboot/+/29796 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I65deb33a45fdc0c0ce64deaa29c2790029dc1d12 Gerrit-Change-Number: 29796 Gerrit-PatchSet: 2 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 03 Apr 2019 05:46:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Comment-In-Reply-To: David Wu <david_wu(a)quanta.corp-partner.google.com> Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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Change in ...coreboot[master]: util/kconfig: Fix missing library issue with ld 2.24 and newer
by Werner Zeh (Code Review) 03 Apr '19

03 Apr '19

Werner Zeh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32137 Change subject: util/kconfig: Fix missing library issue with ld 2.24 and newer ...................................................................... util/kconfig: Fix missing library issue with ld 2.24 and newer When invoking 'make menuconfig' with gcc 4.9.2 an error is thrown: ld: build/util/kconfig/lxdialog/checklist.o: undefined reference to symbol 'acs_map' This happens with ld version 2.24 and newer when menuconfig is executed for the first time after make clean. This does not happen with ld 2.20 (part of gcc 4.4.7). It can be fixed with the flag -ltinfo in HOST_LOADLIBES. Change-Id: I6216bb4d276d4bf98aa4ec06457b809fdcd73235 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M util/kconfig/Makefile 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/32137/1 diff --git a/util/kconfig/Makefile b/util/kconfig/Makefile index a79229d..bf9db64 100644 --- a/util/kconfig/Makefile +++ b/util/kconfig/Makefile @@ -133,7 +133,7 @@ # we really need to do so. (Do not call gcc as part of make mrproper) HOST_EXTRACFLAGS += $(shell $(CONFIG_SHELL) $(check-lxdialog) -ccflags) \ -DLOCALE -HOST_LOADLIBES = $(shell $(CONFIG_SHELL) $(check-lxdialog) -ldflags $(HOSTCC)) +HOST_LOADLIBES = $(shell $(CONFIG_SHELL) $(check-lxdialog) -ldflags $(HOSTCC)) -ltinfo # =========================================================================== -- To view, visit https://review.coreboot.org/c/coreboot/+/32137 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6216bb4d276d4bf98aa4ec06457b809fdcd73235 Gerrit-Change-Number: 32137 Gerrit-PatchSet: 1 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: sb/intel/bd82x6x/early_pch: Make use of RCBA and DMIBAR marcros
by Patrick Rudolph (Code Review) 03 Apr '19

03 Apr '19

Hello Patrick Rudolph, Paul Menzel, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/32072 to look at the new patch set (#5). Change subject: sb/intel/bd82x6x/early_pch: Make use of RCBA and DMIBAR marcros ...................................................................... sb/intel/bd82x6x/early_pch: Make use of RCBA and DMIBAR marcros Use RCBA and DMIBAR macros to get rid of DEFAULT_RCBA and DEFAULT_DMIBAR. Tested on Lenovo T520 (Intel Sandy Bridge). Still boots to OS, no errors visible in dmesg. Change-Id: Ic9be2240ea10b17c8cc289007dccadbb9e3f69ab Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/southbridge/intel/bd82x6x/early_pch.c 1 file changed, 164 insertions(+), 162 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/32072/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/32072 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic9be2240ea10b17c8cc289007dccadbb9e3f69ab Gerrit-Change-Number: 32072 Gerrit-PatchSet: 5 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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coreboot-gerrit April 2019