coreboot-gerrit April 2019

coreboot-gerrit@coreboot.org

1 participants
1219 discussions

Change in ...coreboot[master]: Documentation/gfx/libgfxinit.md: Align line breaks
by Phil (Code Review) 04 Apr '19

04 Apr '19

Phil has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32147 Change subject: Documentation/gfx/libgfxinit.md: Align line breaks ...................................................................... Documentation/gfx/libgfxinit.md: Align line breaks Remove word splitting '-' at line breaks, since they show up within the lines of the rendered html. Change-Id: Ifbd43628f60057a0666fe221de1fe85f0a29cd2d Signed-off-by: Philipp Bartsch <phil(a)grmr.de> --- M Documentation/gfx/libgfxinit.md 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/32147/1 diff --git a/Documentation/gfx/libgfxinit.md b/Documentation/gfx/libgfxinit.md index 2086a90..c50761a 100644 --- a/Documentation/gfx/libgfxinit.md +++ b/Documentation/gfx/libgfxinit.md @@ -48,9 +48,9 @@ * `lightup_ok`: returns whether the initialization succeeded `1` or failed `0`. Currently, only the case that no display - could be found counts as failure. A failure at a la- - ter stage (e.g. failure to train a DP) is not propa- - gated. + could be found counts as failure. A failure at a + later stage (e.g. failure to train a DP) is not + propagated. GMA: Per Board Configuration ---------------------------- -- To view, visit https://review.coreboot.org/c/coreboot/+/32147 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifbd43628f60057a0666fe221de1fe85f0a29cd2d Gerrit-Change-Number: 32147 Gerrit-PatchSet: 1 Gerrit-Owner: Phil Gerrit-MessageType: newchange

5 4

Change in ...coreboot[master]: Documentation: Fix invisisible text
by Phil (Code Review) 04 Apr '19

04 Apr '19

Phil has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32146 Change subject: Documentation: Fix invisisible text ...................................................................... Documentation: Fix invisisible text Encapsulate angled brackets in backticks '<filepath>' to make text visible in html rendering. Change-Id: I1ab926956c909aa3cd2fd92068ccb7b800dd1d4a Signed-off-by: Philipp Bartsch <phil(a)grmr.de> --- M Documentation/lessons/lesson2.md 1 file changed, 4 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/32146/1 diff --git a/Documentation/lessons/lesson2.md b/Documentation/lessons/lesson2.md index c9c9484..d6f800c 100644 --- a/Documentation/lessons/lesson2.md +++ b/Documentation/lessons/lesson2.md @@ -130,8 +130,9 @@ one-line description of what you changed in the files using the template below: -<filepath>: Short description +`<filepath>: Short description` *ex. cpu/amd/pi/00630F01: Fix checkpatch warnings and errors* + **Note:** It is good practice to use present tense in your descriptions and do not punctuate your summary. @@ -171,8 +172,9 @@ description of what you changed in the files according to the template below: -<filepath>: Short description +`<filepath>: Short description` *ex. cpu/amd/pi/00630F01: Fix checkpatch warnings and errors* + **Note:** It is good practice to use present tense in your descriptions and do not punctuate your short description. -- To view, visit https://review.coreboot.org/c/coreboot/+/32146 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1ab926956c909aa3cd2fd92068ccb7b800dd1d4a Gerrit-Change-Number: 32146 Gerrit-PatchSet: 1 Gerrit-Owner: Phil Gerrit-MessageType: newchange

5 5

Change in ...coreboot[master]: Documentation: Fix broken link
by Phil (Code Review) 04 Apr '19

04 Apr '19

Phil has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32145 Change subject: Documentation: Fix broken link ...................................................................... Documentation: Fix broken link Change-Id: Idd08bc49fb7bf3770e03f747d97d90aacc12eada Signed-off-by: Philipp Bartsch <phil(a)grmr.de> --- M Documentation/getting_started/writing_documentation.md 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/32145/1 diff --git a/Documentation/getting_started/writing_documentation.md b/Documentation/getting_started/writing_documentation.md index 0ba17e3..4faec18 100644 --- a/Documentation/getting_started/writing_documentation.md +++ b/Documentation/getting_started/writing_documentation.md @@ -106,5 +106,5 @@ [guide]: http://www.sphinx-doc.org/en/stable/install.html [Sphinx]: http://www.sphinx-doc.org/en/master/ [Markdown Guide]: https://www.markdownguide.org/ -[Gerrit Guidelines]: https://doc.coreboot.org/gerrit_guidelines.html +[Gerrit Guidelines]: gerrit_guidelines.md [review.coreboot.org]: https://review.coreboot.org -- To view, visit https://review.coreboot.org/c/coreboot/+/32145 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idd08bc49fb7bf3770e03f747d97d90aacc12eada Gerrit-Change-Number: 32145 Gerrit-PatchSet: 1 Gerrit-Owner: Phil Gerrit-MessageType: newchange

4 3

Change in ...coreboot[master]: soc/nvidia/tegra210: Increase bootblock size
by Martin Roth (Code Review) 04 Apr '19

04 Apr '19

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32163 Change subject: soc/nvidia/tegra210: Increase bootblock size ...................................................................... soc/nvidia/tegra210: Increase bootblock size There's an issue with the newest toolchain that is blowing the bootblock size on Smaug when compiling for chromeos. Increasing the bootblock size by 2KB will take care of the issue for a while. Signed-off-by: Martin Roth <martinroth(a)chromium.org> Change-Id: I58f7f1cedc8fc5b4c4287f5a120ed76140e1f7a9 --- M src/soc/nvidia/tegra210/include/soc/memlayout.ld 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/32163/1 diff --git a/src/soc/nvidia/tegra210/include/soc/memlayout.ld b/src/soc/nvidia/tegra210/include/soc/memlayout.ld index 1817135..5d7481b 100644 --- a/src/soc/nvidia/tegra210/include/soc/memlayout.ld +++ b/src/soc/nvidia/tegra210/include/soc/memlayout.ld @@ -38,9 +38,9 @@ STACK(0x4000CC00, 3K) #endif TIMESTAMP(0x4000D800, 2K) - BOOTBLOCK(0x4000E000, 28K) - VERSTAGE(0x40015000, 66K) - ROMSTAGE(0x40025800, 106K) + BOOTBLOCK(0x4000E000, 30K) + VERSTAGE(0x40015800, 66K) + ROMSTAGE(0x40026000, 104K) SRAM_END(0x40040000) DRAM_START(0x80000000) -- To view, visit https://review.coreboot.org/c/coreboot/+/32163 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I58f7f1cedc8fc5b4c4287f5a120ed76140e1f7a9 Gerrit-Change-Number: 32163 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

4 3

Change in ...coreboot[master]: mb/intel/coffeelake_rvp: Configure FSP UPDs of DDI ports for cmlrvp
by V Sowmya (Code Review) 04 Apr '19

04 Apr '19

V Sowmya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32140 Change subject: mb/intel/coffeelake_rvp: Configure FSP UPDs of DDI ports for cmlrvp ...................................................................... mb/intel/coffeelake_rvp: Configure FSP UPDs of DDI ports for cmlrvp This patch configures FSP UPD values for HPD and DDC of DDI ports for CMLRVP. BUG=none TEST= Tested that eDP works on CMLRVP. Change-Id: If8c8480eaf2d63cec0b5598b5af3088c630dd78a Signed-off-by: V Sowmya <v.sowmya(a)intel.com> --- M src/mainboard/intel/coffeelake_rvp/variants/cml_u/devicetree.cb 1 file changed, 13 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/32140/1 diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cml_u/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cml_u/devicetree.cb index 6484330..241ac33 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/cml_u/devicetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/cml_u/devicetree.cb @@ -10,6 +10,19 @@ register "HeciEnabled" = "1" register "s0ix_enable" = "1" + # Enable eDP device + register "DdiPortEdp" = "1" + # Enable HPD for DDI ports B/C + register "DdiPortBHpd" = "1" + register "DdiPortCHpd" = "1" + register "DdiPortDHpd" = "1" + register "DdiPortFHpd" = "1" + # Enable DDC for DDI ports B/C + register "DdiPortBDdc" = "1" + register "DdiPortCDdc" = "1" + register "DdiPortDDdc" = "1" + register "DdiPortFDdc" = "1" + register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, [PchSerialIoIndexI2C1] = PchSerialIoPci, -- To view, visit https://review.coreboot.org/c/coreboot/+/32140 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If8c8480eaf2d63cec0b5598b5af3088c630dd78a Gerrit-Change-Number: 32140 Gerrit-PatchSet: 1 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-MessageType: newchange

4 3

Change in ...coreboot[master]: mb/google/hatch: Create kohaku variant
by Shelley Chen (Code Review) 04 Apr '19

04 Apr '19

Shelley Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32160 Change subject: mb/google/hatch: Create kohaku variant ...................................................................... mb/google/hatch: Create kohaku variant Creating Kohaku hatch variant. Currently taking a copy of the hatch variant. Kohaku-specific changes to come in future CLs. BUG=b:129706980 BRANCH=NONE TEST=NONE Change-Id: Ib4b8c2c8332910d992549e3aae8e6aff5234698b Signed-off-by: Shelley Chen <shchen(a)google.com> --- A src/mainboard/google/hatch/variants/kohaku/Makefile.inc A src/mainboard/google/hatch/variants/kohaku/include/variant/acpi/dptf.asl A src/mainboard/google/hatch/variants/kohaku/include/variant/ec.h A src/mainboard/google/hatch/variants/kohaku/include/variant/gpio.h A src/mainboard/google/hatch/variants/kohaku/overridetree.cb 5 files changed, 96 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/32160/1 diff --git a/src/mainboard/google/hatch/variants/kohaku/Makefile.inc b/src/mainboard/google/hatch/variants/kohaku/Makefile.inc new file mode 100644 index 0000000..cf6ee5a --- /dev/null +++ b/src/mainboard/google/hatch/variants/kohaku/Makefile.inc @@ -0,0 +1,20 @@ +## This file is part of the coreboot project. +## +## Copyright 2019 Google LLC +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +SPD_SOURCES = 4G_2400 # 0b000 +SPD_SOURCES += empty_ddr4 # 0b001 +SPD_SOURCES += 8G_2400 # 0b010 +SPD_SOURCES += 8G_2666 # 0b011 +SPD_SOURCES += 16G_2400 # 0b100 +SPD_SOURCES += 16G_2666 # 0b101 diff --git a/src/mainboard/google/hatch/variants/kohaku/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/kohaku/include/variant/acpi/dptf.asl new file mode 100644 index 0000000..31f72b3 --- /dev/null +++ b/src/mainboard/google/hatch/variants/kohaku/include/variant/acpi/dptf.asl @@ -0,0 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/acpi/dptf.asl> diff --git a/src/mainboard/google/hatch/variants/kohaku/include/variant/ec.h b/src/mainboard/google/hatch/variants/kohaku/include/variant/ec.h new file mode 100644 index 0000000..c36f957 --- /dev/null +++ b/src/mainboard/google/hatch/variants/kohaku/include/variant/ec.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef VARIANT_EC_H +#define VARIANT_EC_H + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/hatch/variants/kohaku/include/variant/gpio.h b/src/mainboard/google/hatch/variants/kohaku/include/variant/gpio.h new file mode 100644 index 0000000..5d69eed --- /dev/null +++ b/src/mainboard/google/hatch/variants/kohaku/include/variant/gpio.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include <baseboard/gpio.h> + +#endif diff --git a/src/mainboard/google/hatch/variants/kohaku/overridetree.cb b/src/mainboard/google/hatch/variants/kohaku/overridetree.cb new file mode 100644 index 0000000..6e6414e --- /dev/null +++ b/src/mainboard/google/hatch/variants/kohaku/overridetree.cb @@ -0,0 +1,18 @@ +chip soc/intel/cannonlake + + register "SerialIoDevMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoPci, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + [PchSerialIoIndexSPI0] = PchSerialIoPci, + [PchSerialIoIndexSPI1] = PchSerialIoPci, + [PchSerialIoIndexSPI2] = PchSerialIoDisabled, + [PchSerialIoIndexUART0] = PchSerialIoPci, + [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoDisabled, + }" + +end -- To view, visit https://review.coreboot.org/c/coreboot/+/32160 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib4b8c2c8332910d992549e3aae8e6aff5234698b Gerrit-Change-Number: 32160 Gerrit-PatchSet: 1 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-MessageType: newchange

3 4

Change in ...coreboot[master]: vboot: remove Kconfig option VBOOT_PHYSICAL_REC_SWITCH
by Joel Kitching (Code Review) 04 Apr '19

04 Apr '19

Joel Kitching has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32135 Change subject: vboot: remove Kconfig option VBOOT_PHYSICAL_REC_SWITCH ...................................................................... vboot: remove Kconfig option VBOOT_PHYSICAL_REC_SWITCH This option is duplicated in depthcharge: https://crrev.com/c/1545144 BUG=b:124141368, b:124192753, chromium:943150 TEST=make clean && make test-abuild CQ-DEPEND=CL:1545144 BRANCH=none Change-Id: I48e20ad21cdcb948a23387d3e5fcf142723b0c82 Signed-off-by: Joel Kitching <kitching(a)google.com> --- M src/mainboard/google/beltino/Kconfig M src/mainboard/google/fizz/Kconfig M src/mainboard/google/jecht/Kconfig M src/mainboard/google/sarien/Kconfig M src/mainboard/google/veyron_mickey/Kconfig M src/mainboard/google/veyron_rialto/Kconfig M src/mainboard/samsung/lumpy/Kconfig M src/mainboard/samsung/stumpy/Kconfig M src/security/vboot/Kconfig M src/security/vboot/vboot_handoff.c 10 files changed, 0 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/32135/1 diff --git a/src/mainboard/google/beltino/Kconfig b/src/mainboard/google/beltino/Kconfig index 8ebabe0..872d49d 100644 --- a/src/mainboard/google/beltino/Kconfig +++ b/src/mainboard/google/beltino/Kconfig @@ -16,7 +16,6 @@ if BOARD_GOOGLE_BASEBOARD_BELTINO config VBOOT - select VBOOT_PHYSICAL_REC_SWITCH select VBOOT_VBNV_CMOS config MAINBOARD_DIR diff --git a/src/mainboard/google/fizz/Kconfig b/src/mainboard/google/fizz/Kconfig index 3c8215b..acaf8a6 100644 --- a/src/mainboard/google/fizz/Kconfig +++ b/src/mainboard/google/fizz/Kconfig @@ -39,7 +39,6 @@ config VBOOT select EC_GOOGLE_CHROMEEC_SWITCHES - select VBOOT_PHYSICAL_REC_SWITCH select HAS_RECOVERY_MRC_CACHE select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN diff --git a/src/mainboard/google/jecht/Kconfig b/src/mainboard/google/jecht/Kconfig index 58f3252..15ed05b 100644 --- a/src/mainboard/google/jecht/Kconfig +++ b/src/mainboard/google/jecht/Kconfig @@ -16,7 +16,6 @@ select CHROMEOS_RAMOOPS_DYNAMIC config VBOOT - select VBOOT_PHYSICAL_REC_SWITCH select VBOOT_VBNV_CMOS config MAINBOARD_DIR diff --git a/src/mainboard/google/sarien/Kconfig b/src/mainboard/google/sarien/Kconfig index 6164c8e..58ab300 100644 --- a/src/mainboard/google/sarien/Kconfig +++ b/src/mainboard/google/sarien/Kconfig @@ -108,6 +108,5 @@ select HAS_RECOVERY_MRC_CACHE select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN select VBOOT_LID_SWITCH - select VBOOT_PHYSICAL_REC_SWITCH endif # BOARD_GOOGLE_BASEBOARD_SARIEN diff --git a/src/mainboard/google/veyron_mickey/Kconfig b/src/mainboard/google/veyron_mickey/Kconfig index 9858479..46bc0de 100644 --- a/src/mainboard/google/veyron_mickey/Kconfig +++ b/src/mainboard/google/veyron_mickey/Kconfig @@ -28,7 +28,6 @@ select MAINBOARD_HAS_TPM1 config VBOOT - select VBOOT_PHYSICAL_REC_SWITCH select VBOOT_VBNV_FLASH config MAINBOARD_DIR diff --git a/src/mainboard/google/veyron_rialto/Kconfig b/src/mainboard/google/veyron_rialto/Kconfig index 2aea219..189f010 100644 --- a/src/mainboard/google/veyron_rialto/Kconfig +++ b/src/mainboard/google/veyron_rialto/Kconfig @@ -28,7 +28,6 @@ select MAINBOARD_HAS_TPM1 config VBOOT - select VBOOT_PHYSICAL_REC_SWITCH select VBOOT_VBNV_FLASH config MAINBOARD_DIR diff --git a/src/mainboard/samsung/lumpy/Kconfig b/src/mainboard/samsung/lumpy/Kconfig index 37c967f..2d1544b 100644 --- a/src/mainboard/samsung/lumpy/Kconfig +++ b/src/mainboard/samsung/lumpy/Kconfig @@ -25,7 +25,6 @@ select INTEL_INT15 config VBOOT - select VBOOT_PHYSICAL_REC_SWITCH select VBOOT_VBNV_CMOS config MAINBOARD_DIR diff --git a/src/mainboard/samsung/stumpy/Kconfig b/src/mainboard/samsung/stumpy/Kconfig index d17dc68..a2919f9 100644 --- a/src/mainboard/samsung/stumpy/Kconfig +++ b/src/mainboard/samsung/stumpy/Kconfig @@ -21,7 +21,6 @@ select INTEL_INT15 config VBOOT - select VBOOT_PHYSICAL_REC_SWITCH select VBOOT_VBNV_CMOS config MAINBOARD_DIR diff --git a/src/security/vboot/Kconfig b/src/security/vboot/Kconfig index ca25423..257ce98 100644 --- a/src/security/vboot/Kconfig +++ b/src/security/vboot/Kconfig @@ -191,12 +191,6 @@ bool default n -config VBOOT_PHYSICAL_REC_SWITCH - bool - default n - help - Whether this platform has a physical recovery switch. - config VBOOT_LID_SWITCH bool default n diff --git a/src/security/vboot/vboot_handoff.c b/src/security/vboot/vboot_handoff.c index 1f6d4ee..2f239e6 100644 --- a/src/security/vboot/vboot_handoff.c +++ b/src/security/vboot/vboot_handoff.c @@ -79,8 +79,6 @@ vb_sd->flags |= VBSD_LF_DEV_SWITCH_ON; } /* TODO: Set these in depthcharge */ - if (!CONFIG(VBOOT_PHYSICAL_REC_SWITCH)) - vb_sd->flags |= VBSD_BOOT_REC_SWITCH_VIRTUAL; if (CONFIG(VBOOT_OPROM_MATTERS)) { vb_sd->flags |= VBSD_OPROM_MATTERS; /* -- To view, visit https://review.coreboot.org/c/coreboot/+/32135 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I48e20ad21cdcb948a23387d3e5fcf142723b0c82 Gerrit-Change-Number: 32135 Gerrit-PatchSet: 1 Gerrit-Owner: Joel Kitching <kitching(a)google.com> Gerrit-MessageType: newchange

6 6

Change in ...coreboot[master]: src/soc/intel/braswell/chip.c: Configure LPSS devices in correct mode
by Michał Żygowski (Code Review) 04 Apr '19

04 Apr '19

Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29284 ) Change subject: src/soc/intel/braswell/chip.c: Configure LPSS devices in correct mode ...................................................................... Patch Set 3: > Patch Set 3: > > > Patch Set 3: > > > > is the default PCI mode? (since you're not explicitly setting it) > > what are the consequences of not passing the correct mode to FSP? > > Default can be PCI or ACPI, depending on values devicetree.cb. > The child devices need to operate ACPI mode when the LPSS is operating in ACPI mode. For this reason the patch is uploaded. > > FSP MR2 does a check for ACPI mode and change the device mode. Supplying incorrect configuration will be corrected by FSP, but to be futher proof supply correct configuration to FSP. By looking at the BSF file for Braswell FSP, the I2C and other LPSS devices are defined as Enable/Disable switches, so only binary configuration (0 or 1). Does it mean that that Intel did not document the ACPI mode as a 3rd option in the BSF and Integration Guide? -- To view, visit https://review.coreboot.org/c/coreboot/+/29284 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie271d8cb9f30f0c0ba538f1530cfb82f1306fea8 Gerrit-Change-Number: 29284 Gerrit-PatchSet: 3 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Thu, 04 Apr 2019 09:34:26 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: {src,util}: Correct typo in comment and debug string
by Michał Żygowski (Code Review) 04 Apr '19

04 Apr '19

Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29321 ) Change subject: {src,util}: Correct typo in comment and debug string ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29321 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0362bb8d7c883e7fcbc6a2fc2f9918251f0d8d6e Gerrit-Change-Number: 29321 Gerrit-PatchSet: 4 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 04 Apr 2019 09:07:47 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: src/soc/intel/braswell/acpi/lpss.asl: Remove SPI1 and PWM asl code
by Michał Żygowski (Code Review) 04 Apr '19

04 Apr '19

Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29417 ) Change subject: src/soc/intel/braswell/acpi/lpss.asl: Remove SPI1 and PWM asl code ...................................................................... Patch Set 3: > Patch Set 1: > > > Patch Set 1: > > > > Please use runtime detection and ssdt code to achieve the same functionality. > > The standard Intel FSP disables both SPI1 and PWM. All system using this FSP will not have the SPI1 and PWM enabled. Adding runtime detection will take boot time, where the result will be constant on these system. > > I dont know if Google Cyan use standard FSP binary. If so I suggest removing the SPI1 and PWM ASL code. > For Google Cyan the SP1 and PWM ASL code can be added to mainboard directory when required. > > I suggest to move this code to Google Cyan? Since I am not familiar with peripheral usage on Chromebooks, I am adding Matt on CC. Matt, could You please share Your opinion and possibly review the patch? -- To view, visit https://review.coreboot.org/c/coreboot/+/29417 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iec2ca7520081d00bf7a53d58ee054aa6f23e5606 Gerrit-Change-Number: 29417 Gerrit-PatchSet: 3 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Thu, 04 Apr 2019 08:53:42 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit April 2019