Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/28464 )
Change subject: src/drivers/intel/fsp1_1: Configure UART after memory init
......................................................................
Patch Set 2:
> Patch Set 2:
>
> > Patch Set 2:
> >
> > Opened bug report at https://github.com/IntelFsp/FSP/issues/15
>
> Intel will not only update Braswell FSP anymore, only for security issues.
>
> Does it make sense implementing this patch for now? (Can be removed when new FSP contains fix for this.
Since I feel the same, I'm leaving my +2. Hope other developers will take Your reasoning into consideration and merge the patch.
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Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29661 )
Change subject: {drivers,mb,soc/intel/braswell}: Add support for Braswell FSP MR2
......................................................................
Patch Set 8:
> Patch Set 5:
>
> >> Usage of 'old non MR2 fields should be moved to 'Braswell' mainboards.
> >
> > but the current header is newer than MR2 (1.1.7.0 v 1.1.4.1). and since all existing boards compile with it, seems like MR2 should be the special case/exception requiring manual selection
>
> Um, how about always selecting the respective case:
> select SOC_INTEL_BRASWELL__BSWFSP_
> or
> select SOC_INTEL_BRASWELL_BSWSBFSP
>
> I've also opened a ticket
> https://github.com/IntelFsp/FSP/issues/14
> We should at least ask for an update, shouldn't we :)
Have upload new patch. No config is used, but developer can specify the location of the FspUpdVpd.h.
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Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/28464 )
Change subject: src/drivers/intel/fsp1_1: Configure UART after memory init
......................................................................
Patch Set 2:
> Patch Set 2:
>
> Opened bug report at https://github.com/IntelFsp/FSP/issues/15
Intel will not only update Braswell FSP anymore, only for security issues.
Does it make sense implementing this patch for now? (Can be removed when new FSP contains fix for this.
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Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29414 )
Change subject: src/soc/intel/braswell: Remove disabled LPE acpi code
......................................................................
Patch Set 5:
(1 comment)
> Patch Set 5:
>
> (1 comment)
https://review.coreboot.org/#/c/29414/5/src/soc/intel/braswell/acpi/southcl…
File src/soc/intel/braswell/acpi/southcluster.asl:
https://review.coreboot.org/#/c/29414/5/src/soc/intel/braswell/acpi/southcl…
PS5, Line 290:
:
> wouldn't it be easier to just guard this with a Kconfig option, eg BRASWELL_USE_LPE_AUDIO, vs adding […]
I did this in patchset 1, but got comment having runtime detection.
I expect that none on the Braswell platforms are using LPE devices, but this SSDT is required to be backwards compatible.
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Hello Patrick Rudolph, Huang Jin, Arthur Heymans, York Yang, Lee Leahy, build bot (Jenkins), Hannah Williams, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/29662
to look at the new patch set (#8).
Change subject: soc/intel/braswell: Add C_ENVIRONMENT_BOOTBLOCK support
......................................................................
soc/intel/braswell: Add C_ENVIRONMENT_BOOTBLOCK support
No C_ENVIRONMENT_BOOTBLOCK support for Braswell is available.
Enable support and add required files for the Braswell Bootblock in C.
The next changes are made support C_ENVIRONMENT_BOOTBLOCK:
- (Re)init console in function romstage_c_entry() .
- Add car_stage_entry() function bootblock-c_entry() functions
- Specify config DCACHE_BSP_STACK_SIZE and C_ENV_BOOTBLOCK_SIZE
- Add bootblokc_c_entry()
BUG=NA
TEST=Portwell PQ7-M107
Change-Id: Iab48ad72f1514c93f20d70db5ef4fd8fa2383e8c
Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com>
---
M src/drivers/intel/fsp1_1/car.c
M src/soc/intel/braswell/Kconfig
M src/soc/intel/braswell/Makefile.inc
M src/soc/intel/braswell/bootblock/bootblock.c
R src/soc/intel/braswell/bootblock/cache_as_ram_cbootblock.S
M src/soc/intel/braswell/romstage/Makefile.inc
A src/soc/intel/braswell/romstage/car_stage_entry.S
7 files changed, 113 insertions(+), 103 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/29662/8
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Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29796 )
Change subject: mb/google/fizz/variants/karma: Clear GPP_B4 when entering S5
......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/#/c/29796/2//COMMIT_MSG
Commit Message:
https://review.coreboot.org/#/c/29796/2//COMMIT_MSG@11
PS2, Line 11: BUG=b:124197348
> See comment3 below. for scenario 2, need setting GPP_B4 to low in S5. Thanks. […]
Thank you.
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Hello Alexander Couzens, Patrick Rudolph, Angel Pons, Paul Menzel, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#9).
Change subject: mb/lenovo/r500: Add mainboard
......................................................................
mb/lenovo/r500: Add mainboard
Tested:
- Ethernet NIC
- Wifi RFKill
- USB
- LVDS, VGA with libgfxinit
- Booting with dock attached (COM1)
- Keyboard, trackpoint
- SeaBIOS 1.12
- S3 resume
- Tested in descriptor mode, with vendor FD and ME
Untested:
- SATA (likely works)
- Trackpad (my cable is broken, likely works)
- Displayport (likely works)
- Descriptorless mode
- DVD drive
- Extra battery
Does not work:
- Dock hotplug
- Quad core CPU (hangs during AP init, probably needs hardware mod)
- Models with a sole ATI GPU (needs probing of PEG in romstage)
- Hotplugging the expresscard slot (works with 'echo 1 | sudo tee
/sys/bus/pci/rescan')
TODO:
- proper dock support
- documentation
note: This board was hard to flash, I had to desolder the flash.
TESTED: on a R500 with an Intel iGPU, SeaBIOS 1.12, Debian 9,
Linux 4.9 from USB
Change-Id: I9e129b2e916acdf2b8534fa9d8d2cfc8f64f5815
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/mainboard/lenovo/t400/Kconfig
M src/mainboard/lenovo/t400/Kconfig.name
M src/mainboard/lenovo/t400/Makefile.inc
M src/mainboard/lenovo/t400/devicetree.cb
M src/mainboard/lenovo/t400/dsdt.asl
M src/mainboard/lenovo/t400/romstage.c
A src/mainboard/lenovo/t400/variants/r500/Makefile.inc
A src/mainboard/lenovo/t400/variants/r500/data.vbt
A src/mainboard/lenovo/t400/variants/r500/gpio.c
A src/mainboard/lenovo/t400/variants/r500/overridetree.cb
A src/mainboard/lenovo/t400/variants/t400/Makefile.inc
R src/mainboard/lenovo/t400/variants/t400/gpio.c
A src/mainboard/lenovo/t400/variants/t400/overridetree.cb
13 files changed, 262 insertions(+), 40 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/28644/9
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