April 2019 - coreboot-gerrit - mail.coreboot.org

Change in ...coreboot[master]: fsp platforms: Notify FSP after PCI device init
by Philipp Deppenwiese (Code Review) April 2, 2019

April 2, 2019

Philipp Deppenwiese has uploaded a new patch set (#3) to the change originally created by David Imhoff. ( https://review.coreboot.org/c/coreboot/+/10100 ) Change subject: fsp platforms: Notify FSP after PCI device init ...................................................................... fsp platforms: Notify FSP after PCI device init Notify FSP of the EnumInitPhaseAfterPciEnumeration stage after PCI device initialization. As described in fsp-architecture-spec.pdf, April 2014, Par 6.8.3. This fixes shutdown issues on Minnowboard Max. TEST=Built and booted on Minnowboard Max. Verified power LED off after Linux power off. Change-Id: Ia6508c07aa53ba436bb5899a48ecd64a117524e5 Signed-off-by: David Imhoff <dimhoff_devel(a)xs4all.nl> --- M src/drivers/intel/fsp1_0/fsp_util.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/10100/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/10100 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia6508c07aa53ba436bb5899a48ecd64a117524e5 Gerrit-Change-Number: 10100 Gerrit-PatchSet: 3 Gerrit-Owner: David Imhoff <dimhoff_devel(a)xs4all.nl> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Ben Gardner <gardner.ben(a)gmail.com> Gerrit-Reviewer: David Imhoff <dimhoff_devel(a)xs4all.nl> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Name of user not set #1000214 Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: fsp platforms: Notify FSP after PCI device init
by Philipp Deppenwiese (Code Review) April 2, 2019

April 2, 2019

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/10100 ) Change subject: fsp platforms: Notify FSP after PCI device init ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/10100 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia6508c07aa53ba436bb5899a48ecd64a117524e5 Gerrit-Change-Number: 10100 Gerrit-PatchSet: 2 Gerrit-Owner: David Imhoff <dimhoff_devel(a)xs4all.nl> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Ben Gardner <gardner.ben(a)gmail.com> Gerrit-Reviewer: David Imhoff <dimhoff_devel(a)xs4all.nl> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Name of user not set #1000214 Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 02 Apr 2019 16:22:48 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: Little bit more helpful, giving back the lines for each file if any
by Balázs Vinarz (Code Review) April 2, 2019

April 2, 2019

Balázs Vinarz has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30988 Change subject: Little bit more helpful, giving back the lines for each file if any ...................................................................... Little bit more helpful, giving back the lines for each file if any Change-Id: I8ae13f62c6e2cd87278fefab8de5faf0d1bc0a90 --- M util/lint/lint-stable-003-whitespace 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/30988/1 diff --git a/util/lint/lint-stable-003-whitespace b/util/lint/lint-stable-003-whitespace index f9b7891..b2011e7 100755 --- a/util/lint/lint-stable-003-whitespace +++ b/util/lint/lint-stable-003-whitespace @@ -20,7 +20,7 @@ # shellcheck disable=SC2086,SC2046 if uname | grep -qi "linux"; then - grep -l "[[:space:]][[:space:]]*$" \ + grep -n -H "[[:space:]][[:space:]]*$" \ $(git ls-files $INCLUDELIST | \ grep -Ev "($EXCLUDELIST)" ) | \ sed -e "s,^.*$,File & has lines ending with whitespace.," -- To view, visit https://review.coreboot.org/c/coreboot/+/30988 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8ae13f62c6e2cd87278fefab8de5faf0d1bc0a90 Gerrit-Change-Number: 30988 Gerrit-PatchSet: 1 Gerrit-Owner: Balázs Vinarz <vinibali1(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: util/superiotool/winbond: Fix 0x4f Bank 0 value
by Paul Menzel (Code Review) April 2, 2019

April 2, 2019

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/23762 ) Change subject: util/superiotool/winbond: Fix 0x4f Bank 0 value ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/23762 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaf21da25281bfc1479b7d15fa29dcebf014570e5 Gerrit-Change-Number: 23762 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 02 Apr 2019 14:35:05 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/braswell: Correct serial IRQ support
by Frans Hendriks (Code Review) April 2, 2019

April 2, 2019

Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29398 ) Change subject: soc/intel/braswell: Correct serial IRQ support ...................................................................... Patch Set 12: (1 comment) Update covering the remarks. https://review.coreboot.org/#/c/29398/10/src/soc/intel/braswell/southcluste… File src/soc/intel/braswell/southcluster.c: https://review.coreboot.org/#/c/29398/10/src/soc/intel/braswell/southcluste… PS10, Line 97: (pci_read_config32(dev, IBASE) & ~0xF) > Why use ILB_BASE_ADDRESS above and then this here? Correct in new patch. Use same construction -- To view, visit https://review.coreboot.org/c/coreboot/+/29398 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7844cad69dc0563fa6109d779d0afb7c2edd7245 Gerrit-Change-Number: 29398 Gerrit-PatchSet: 12 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Tue, 02 Apr 2019 13:33:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/braswell: Correct serial IRQ support
by Frans Hendriks (Code Review) April 2, 2019

April 2, 2019

Hello Patrick Rudolph, Paul Menzel, build bot (Jenkins), Hannah Williams, Michał Żygowski, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29398 to look at the new patch set (#12). Change subject: soc/intel/braswell: Correct serial IRQ support ...................................................................... soc/intel/braswell: Correct serial IRQ support Serial IRQ was configured in quiet mode, but not enabled. Enable serial IRQ and use 'enum seriirq_mode' as a devicetree option. Function sc_enable_serial_irqs() is added to enabled serial IRQs. enable_serirq_quiet_mode() is renamed to sc_set_serial_irqs_mode(). This function use the 'serirq_mode' to set the mode. The call to this function is moved from finalize to init having serial IRQs enable in early stage. Serial IRQs must be enabled in continuous mode for at least one frame before switching into quiet mode. BUG=N/A TEST=Portwell PQ7-M107 Change-Id: I7844cad69dc0563fa6109d779d0afb7c2edd7245 Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/soc/intel/braswell/chip.h M src/soc/intel/braswell/include/soc/lpc.h M src/soc/intel/braswell/southcluster.c 3 files changed, 38 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/29398/12 -- To view, visit https://review.coreboot.org/c/coreboot/+/29398 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7844cad69dc0563fa6109d779d0afb7c2edd7245 Gerrit-Change-Number: 29398 Gerrit-PatchSet: 12 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: bootmode: display_init_required() to check VBOOT and OPROM_MATTERS
by Julius Werner (Code Review) April 2, 2019

April 2, 2019

Julius Werner has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32112 Change subject: bootmode: display_init_required() to check VBOOT and OPROM_MATTERS ...................................................................... bootmode: display_init_required() to check VBOOT and OPROM_MATTERS Skipping display init on normal-mode boot is a vboot feature, not specific to Chrome OS. Fix the code in display_init_required() to check CONFIG_VBOOT rather than CONFIG_CHROMEOS now that the two aren't always the same anymore. Also add a check to guarantee at compile time that VBOOT_OPROM_MATTERS is enabled on all platforms that make a check to this function (when VBOOT is also enabled). The whole display skipping mechanism is based on the oprom_needed NVRAM flag, and skipping display init without enabling the option to tell vboot that it needs to pay attention to that flag would make the whole thing not work right. Change-Id: I5d6421509bdcdaa61b78015af3fa6241fe75bb7f Signed-off-by: Julius Werner <jwerner(a)chromium.org> --- M src/lib/bootmode.c 1 file changed, 6 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/32112/1 diff --git a/src/lib/bootmode.c b/src/lib/bootmode.c index e402536..b7ab649 100644 --- a/src/lib/bootmode.c +++ b/src/lib/bootmode.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include <assert.h> #include <bootmode.h> #include <vendorcode/google/chromeos/chromeos.h> @@ -35,8 +36,12 @@ int display_init_required(void) { /* For Chrome OS always honor vboot_handoff_skip_display_init(). */ - if (CONFIG(CHROMEOS)) + if (CONFIG(VBOOT)) { + if (!CONFIG(VBOOT_OPROM_MATTERS)) + dead_code("If you call display_init_required() anywhere" + ", you need to select VBOOT_OPROM_MATTERS!"); return !vboot_handoff_skip_display_init(); + } /* By default always initialize display. */ return 1; -- To view, visit https://review.coreboot.org/c/coreboot/+/32112 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5d6421509bdcdaa61b78015af3fa6241fe75bb7f Gerrit-Change-Number: 32112 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: nb/intel/i945: Correct SLP_S4# comment
by Paul Menzel (Code Review) April 2, 2019

April 2, 2019

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/28395 ) Change subject: nb/intel/i945: Correct SLP_S4# comment ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/28395/1//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/28395/1//COMMIT_MSG@9 PS1, Line 9: Bit #3 of GEN_PMCON_3 register will enable : SLP_S4# Assertion Stretch. This should fit on one line. -- To view, visit https://review.coreboot.org/c/coreboot/+/28395 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I86df0df5337397d2c23ca311ecae1c8a38eb32f0 Gerrit-Change-Number: 28395 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 02 Apr 2019 11:47:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/google/fizz/variants/karma: Clear GPP_B4 when entering S5
by Paul Menzel (Code Review) April 2, 2019

April 2, 2019

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29796 ) Change subject: mb/google/fizz/variants/karma: Clear GPP_B4 when entering S5 ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/#/c/29796/2//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/29796/2//COMMIT_MSG@11 PS2, Line 11: BUG=b:124197348 > Please refer to https://partnerissuetracker.corp.google.com/u/0/issues/124197348#comment3 […] The issue is not accessible to all reviewers, so please add a summary of the issue to the commit message. -- To view, visit https://review.coreboot.org/c/coreboot/+/29796 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I65deb33a45fdc0c0ce64deaa29c2790029dc1d12 Gerrit-Change-Number: 29796 Gerrit-PatchSet: 2 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 02 Apr 2019 11:22:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: David Wu <david_wu(a)quanta.corp-partner.google.com> Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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Change in ...coreboot[master]: mediatek/mt8183: Fix RTC initialization flow
by Ran Bi (Code Review) April 2, 2019

April 2, 2019

Ran Bi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31968 Change subject: mediatek/mt8183: Fix RTC initialization flow ...................................................................... mediatek/mt8183: Fix RTC initialization flow 1. fix RTC initialization flow 2. fix RTC lpd settings BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui Change-Id: I6f26edd6699c2f6d9af80c285b70742b44407136 Signed-off-by: Ran Bi <ran.bi(a)mediatek.com> --- M src/soc/mediatek/common/include/soc/rtc_common.h M src/soc/mediatek/common/rtc.c M src/soc/mediatek/mt8173/include/soc/rtc.h M src/soc/mediatek/mt8173/rtc.c M src/soc/mediatek/mt8183/include/soc/rtc.h M src/soc/mediatek/mt8183/rtc.c 6 files changed, 77 insertions(+), 35 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/31968/1 diff --git a/src/soc/mediatek/common/include/soc/rtc_common.h b/src/soc/mediatek/common/include/soc/rtc_common.h index 41e772e..b652ad5 100644 --- a/src/soc/mediatek/common/include/soc/rtc_common.h +++ b/src/soc/mediatek/common/include/soc/rtc_common.h @@ -99,7 +99,6 @@ int rtc_writeif_unlock(void); void rtc_xosc_write(u16 val); int rtc_reg_init(void); -u8 rtc_check_state(void); void rtc_boot_common(void); #endif /* SOC_MEDIATEK_RTC_COMMON_H */ diff --git a/src/soc/mediatek/common/rtc.c b/src/soc/mediatek/common/rtc.c index fd40cb5..647ae1e 100644 --- a/src/soc/mediatek/common/rtc.c +++ b/src/soc/mediatek/common/rtc.c @@ -137,7 +137,7 @@ return rtc_write_trigger(); } -u8 rtc_check_state(void) +static u8 rtc_check_state(void) { u16 con; u16 pwrky1; @@ -147,6 +147,9 @@ pwrap_read(RTC_POWERKEY1, &pwrky1); pwrap_read(RTC_POWERKEY2, &pwrky2); + printk(BIOS_INFO, "[RTC] con = %x, pwrkey1 = %x, pwrkey2 = %x\n", + con, pwrky1, pwrky2); + if (con & RTC_CON_LPSTA_RAW) return RTC_STATE_INIT; diff --git a/src/soc/mediatek/mt8173/include/soc/rtc.h b/src/soc/mediatek/mt8173/include/soc/rtc.h index fe5cbac..0ee944a 100644 --- a/src/soc/mediatek/mt8173/include/soc/rtc.h +++ b/src/soc/mediatek/mt8173/include/soc/rtc.h @@ -112,7 +112,7 @@ /* external API */ void rtc_osc_init(void); -int rtc_init(u8 recover); +bool rtc_init(u8 recover); void rtc_boot(void); #endif /* SOC_MEDIATEK_MT8173_RTC_H */ diff --git a/src/soc/mediatek/mt8173/rtc.c b/src/soc/mediatek/mt8173/rtc.c index 5b7d486..056c051 100644 --- a/src/soc/mediatek/mt8173/rtc.c +++ b/src/soc/mediatek/mt8173/rtc.c @@ -71,15 +71,15 @@ } /* rtc init check */ -int rtc_init(u8 recover) +bool rtc_init(u8 recover) { printk(BIOS_INFO, "[RTC] %s recovery: %d\n", __func__, recover); if (!rtc_writeif_unlock()) - return 0; + return false; if (!rtc_gpio_init()) - return 0; + return false; /* Use SW to detect 32K mode instead of HW */ if (recover) @@ -94,7 +94,7 @@ pwrap_write(RTC_POWERKEY1, RTC_POWERKEY1_KEY); pwrap_write(RTC_POWERKEY2, RTC_POWERKEY2_KEY); if (!rtc_write_trigger()) - return 0; + return false; if (recover) pwrap_write_field(PMIC_RG_CHRSTATUS, 0, 0x4, 9); @@ -102,11 +102,11 @@ rtc_xosc_write(0); if (!rtc_reg_init()) - return 0; + return false; if (!rtc_lpd_init()) - return 0; + return false; - return 1; + return true; } /* enable rtc bbpu */ diff --git a/src/soc/mediatek/mt8183/include/soc/rtc.h b/src/soc/mediatek/mt8183/include/soc/rtc.h index 08ebe98..b0c1d4a 100644 --- a/src/soc/mediatek/mt8183/include/soc/rtc.h +++ b/src/soc/mediatek/mt8183/include/soc/rtc.h @@ -106,6 +106,14 @@ RTC_REG_XOSC32_ENB = 1 << 15 }; +enum { + RTC_LPD_OPT_XOSC_AND_EOSC_LPD = 0 << 13, + RTC_LPD_OPT_EOSC_LPD = 1 << 13, + RTC_LPD_OPT_XOSC_LPD = 2 << 13, + RTC_LPD_OPT_F32K_CK_ALIVE = 3 << 13, + RTC_LPD_OPT_MASK = 3 << 13 +}; + /* PMIC TOP Register Definition */ enum { PMIC_RG_SCK_TOP_CON0 = 0x050C @@ -142,7 +150,7 @@ /* external API */ void rtc_bbpu_power_on(void); void rtc_osc_init(void); -int rtc_init(u8 recover); +bool rtc_init(u8 recover); void rtc_boot(void); #endif /* SOC_MEDIATEK_MT8183_RTC_H */ diff --git a/src/soc/mediatek/mt8183/rtc.c b/src/soc/mediatek/mt8183/rtc.c index d67315b..69e4f0c 100644 --- a/src/soc/mediatek/mt8183/rtc.c +++ b/src/soc/mediatek/mt8183/rtc.c @@ -64,7 +64,8 @@ /* Export 32K clock RTC_32K2V8 */ pwrap_read(RTC_CON, &con); - con &= (RTC_CON_LPSTA_RAW | RTC_CON_LPRST | RTC_CON_EOSC32_LPEN); + con &= (RTC_CON_LPSTA_RAW | RTC_CON_LPRST | RTC_CON_EOSC32_LPEN + | RTC_CON_XOSC32_LPEN); con |= (RTC_CON_GPEN | RTC_CON_GOE); con &= ~(RTC_CON_F32KOB); pwrap_write(RTC_CON, con); @@ -81,9 +82,17 @@ /* low power detect setting */ static int rtc_lpd_init(void) { - u16 con; + u16 con, sec; - con = pwrap_read(RTC_CON, &con) | RTC_CON_XOSC32_LPEN; + /* set RTC_LPD_OPT */ + pwrap_read(RTC_AL_SEC, &sec); + sec |= RTC_LPD_OPT_F32K_CK_ALIVE; + pwrap_write(RTC_AL_SEC, sec); + if (!rtc_write_trigger()) + return 0; + + pwrap_read(RTC_CON, &con); + con |= RTC_CON_XOSC32_LPEN; con &= ~RTC_CON_LPRST; pwrap_write(RTC_CON, con); if (!rtc_write_trigger()) @@ -99,7 +108,8 @@ if (!rtc_write_trigger()) return 0; - con = pwrap_read(RTC_CON, &con) | RTC_CON_EOSC32_LPEN; + pwrap_read(RTC_CON, &con); + con |= RTC_CON_EOSC32_LPEN; con &= ~RTC_CON_LPRST; pwrap_write(RTC_CON, con); if (!rtc_write_trigger()) @@ -115,6 +125,18 @@ if (!rtc_write_trigger()) return 0; + pwrap_read(RTC_CON, &con); + con &= ~RTC_CON_XOSC32_LPEN; + pwrap_write(RTC_CON, con); + + /* set RTC_LPD_OPT */ + pwrap_read(RTC_AL_SEC, &sec); + sec &= ~RTC_LPD_OPT_MASK; + sec |= RTC_LPD_OPT_EOSC_LPD; + pwrap_write(RTC_AL_SEC, sec); + if (!rtc_write_trigger()) + return 0; + return 1; } @@ -142,36 +164,46 @@ } /* rtc init check */ -int rtc_init(u8 recover) +bool rtc_init(u8 recover) { printk(BIOS_INFO, "[RTC] %s recovery: %d\n", __func__, recover); - if (!rtc_writeif_unlock()) - return 0; - - if (!rtc_gpio_init()) - return 0; - - /* using dcxo 32K clock */ - rtc_enable_dcxo(); - - if (recover) - mdelay(20); - /* write powerkeys */ pwrap_write(RTC_POWERKEY1, RTC_POWERKEY1_KEY); pwrap_write(RTC_POWERKEY2, RTC_POWERKEY2_KEY); if (!rtc_write_trigger()) - return 0; + return false; + + if (!rtc_writeif_unlock()) + return false; + + /* using dcxo 32K clock */ + rtc_enable_dcxo(); + if (recover) + mdelay(20); + + if (!rtc_gpio_init()) + return false; + + if (!rtc_hw_init()) + return false; if (!rtc_reg_init()) - return 0; - if (!rtc_lpd_init()) - return 0; - if (!rtc_hw_init()) - return 0; + return false; - return 1; + if (!rtc_lpd_init()) + return false; + + /* write powerkeys again to enable lpd */ + pwrap_write(RTC_POWERKEY1, RTC_POWERKEY1_KEY); + pwrap_write(RTC_POWERKEY2, RTC_POWERKEY2_KEY); + if (!rtc_write_trigger()) + return false; + + if (!rtc_writeif_unlock()) + return false; + + return true; } /* enable rtc bbpu */ -- To view, visit https://review.coreboot.org/c/coreboot/+/31968 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6f26edd6699c2f6d9af80c285b70742b44407136 Gerrit-Change-Number: 31968 Gerrit-PatchSet: 1 Gerrit-Owner: Ran Bi <ran.bi(a)mediatek.com> Gerrit-MessageType: newchange

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