coreboot-gerrit April 2019

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Change in ...coreboot[master]: mb/aopen/dxplplusu: Remove redundant use of ACPI offset operator
by HAOUAS Elyes (Code Review) 01 Apr '19

01 Apr '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32127 Change subject: mb/aopen/dxplplusu: Remove redundant use of ACPI offset operator ...................................................................... mb/aopen/dxplplusu: Remove redundant use of ACPI offset operator Change-Id: I790303a1fab64dbbe749563325394b9be2c109ad Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/aopen/dxplplusu/acpi/i82801db.asl 1 file changed, 17 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/32127/1 diff --git a/src/mainboard/aopen/dxplplusu/acpi/i82801db.asl b/src/mainboard/aopen/dxplplusu/acpi/i82801db.asl index 4be964d..5cd077b 100644 --- a/src/mainboard/aopen/dxplplusu/acpi/i82801db.asl +++ b/src/mainboard/aopen/dxplplusu/acpi/i82801db.asl @@ -85,10 +85,23 @@ OperationRegion (ACPI, SystemIO, 0x0400, 0xC0) Field (ACPI, ByteAcc, NoLock, Preserve) { - Offset (0x00), PS1L,8, PS1H,8, PE1L,8, PE1H,8, - Offset (0x28), GS0L,8, GS0H,8, GSPL,8, GSPH,8, - Offset (0x2C), GE0L,8, GE0H,8, GEPL,8, GEPH,8, - Offset (0xB8), GPLV,8 + PS1L, 8, + PS1H, 8, + PE1L, 8, + PE1H, 8, + + Offset (0x28), + GS0L, 8, + GS0H, 8, + GSPL, 8, + GSPH, 8, + GE0L, 8, + GE0H, 8, + GEPL, 8, + GEPH, 8, + + Offset (0xB8), + GPLV, 8 } Name (MSBF, ResourceTemplate () -- To view, visit https://review.coreboot.org/c/coreboot/+/32127 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I790303a1fab64dbbe749563325394b9be2c109ad Gerrit-Change-Number: 32127 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 2

Change in ...coreboot[master]: mb/*/devicetree.cb: Set PrimaryDisplay for skl/kbl
by Maxim Polyakov (Code Review) 01 Apr '19

01 Apr '19

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32102 Change subject: mb/*/devicetree.cb: Set PrimaryDisplay for skl/kbl ...................................................................... mb/*/devicetree.cb: Set PrimaryDisplay for skl/kbl Set PrimaryDisplay option in the devicetree.cb for all motherboards with Skylake/Kaby Lake processor. Change-Id: Ibed05fc9171e2bd73654f0da6273a8534746913d Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/mainboard/asrock/h110m/devicetree.cb M src/mainboard/google/eve/devicetree.cb M src/mainboard/google/fizz/variants/baseboard/devicetree.cb M src/mainboard/google/glados/variants/asuka/devicetree.cb M src/mainboard/google/glados/variants/caroline/devicetree.cb M src/mainboard/google/glados/variants/cave/devicetree.cb M src/mainboard/google/glados/variants/chell/devicetree.cb M src/mainboard/google/glados/variants/glados/devicetree.cb M src/mainboard/google/glados/variants/lars/devicetree.cb M src/mainboard/google/glados/variants/sentry/devicetree.cb M src/mainboard/google/poppy/variants/atlas/devicetree.cb M src/mainboard/google/poppy/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/nami/devicetree.cb M src/mainboard/google/poppy/variants/nautilus/devicetree.cb M src/mainboard/google/poppy/variants/nocturne/devicetree.cb M src/mainboard/google/poppy/variants/rammus/devicetree.cb M src/mainboard/google/poppy/variants/soraka/devicetree.cb M src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb M src/mainboard/intel/kunimitsu/devicetree.cb M src/mainboard/intel/saddlebrook/devicetree.cb M src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb M src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb 22 files changed, 22 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/32102/1 diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb index 9e2fca0..c79fccf 100644 --- a/src/mainboard/asrock/h110m/devicetree.cb +++ b/src/mainboard/asrock/h110m/devicetree.cb @@ -47,6 +47,7 @@ register "HeciEnabled" = "0" register "InternalGfx" = "1" register "SkipExtGfxScan" = "0" + register "PrimaryDisplay" = "Display_PEG" register "Device4Enable" = "1" register "SaGv" = "SaGv_Enabled" register "PmTimerDisabled" = "0" diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb index 2f275ac..839c830 100644 --- a/src/mainboard/google/eve/devicetree.cb +++ b/src/mainboard/google/eve/devicetree.cb @@ -43,6 +43,7 @@ register "PttSwitch" = "0" register "InternalGfx" = "1" register "SkipExtGfxScan" = "1" + register "PrimaryDisplay" = "Display_Auto" register "Device4Enable" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb index bfabe29..80a0eb8 100644 --- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb @@ -78,6 +78,7 @@ register "PttSwitch" = "0" register "InternalGfx" = "1" register "SkipExtGfxScan" = "1" + register "PrimaryDisplay" = "Display_Auto" register "Device4Enable" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" diff --git a/src/mainboard/google/glados/variants/asuka/devicetree.cb b/src/mainboard/google/glados/variants/asuka/devicetree.cb index e0a792d..3b3f71d 100644 --- a/src/mainboard/google/glados/variants/asuka/devicetree.cb +++ b/src/mainboard/google/glados/variants/asuka/devicetree.cb @@ -35,6 +35,7 @@ register "ScsSdCardEnabled" = "0" register "InternalGfx" = "1" register "SkipExtGfxScan" = "1" + register "PrimaryDisplay" = "Display_Auto" register "Device4Enable" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" diff --git a/src/mainboard/google/glados/variants/caroline/devicetree.cb b/src/mainboard/google/glados/variants/caroline/devicetree.cb index 0f5a911..77ac89f 100644 --- a/src/mainboard/google/glados/variants/caroline/devicetree.cb +++ b/src/mainboard/google/glados/variants/caroline/devicetree.cb @@ -45,6 +45,7 @@ register "PttSwitch" = "0" register "InternalGfx" = "1" register "SkipExtGfxScan" = "1" + register "PrimaryDisplay" = "Display_Auto" register "Device4Enable" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" diff --git a/src/mainboard/google/glados/variants/cave/devicetree.cb b/src/mainboard/google/glados/variants/cave/devicetree.cb index a9b28a8..02b06fd 100644 --- a/src/mainboard/google/glados/variants/cave/devicetree.cb +++ b/src/mainboard/google/glados/variants/cave/devicetree.cb @@ -45,6 +45,7 @@ register "PttSwitch" = "0" register "InternalGfx" = "1" register "SkipExtGfxScan" = "1" + register "PrimaryDisplay" = "Display_Auto" register "Device4Enable" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" diff --git a/src/mainboard/google/glados/variants/chell/devicetree.cb b/src/mainboard/google/glados/variants/chell/devicetree.cb index 07467b3..730ea42 100644 --- a/src/mainboard/google/glados/variants/chell/devicetree.cb +++ b/src/mainboard/google/glados/variants/chell/devicetree.cb @@ -45,6 +45,7 @@ register "PttSwitch" = "0" register "InternalGfx" = "1" register "SkipExtGfxScan" = "1" + register "PrimaryDisplay" = "Display_Auto" register "Device4Enable" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" diff --git a/src/mainboard/google/glados/variants/glados/devicetree.cb b/src/mainboard/google/glados/variants/glados/devicetree.cb index d4266cc..8aa165c 100644 --- a/src/mainboard/google/glados/variants/glados/devicetree.cb +++ b/src/mainboard/google/glados/variants/glados/devicetree.cb @@ -45,6 +45,7 @@ register "PttSwitch" = "0" register "InternalGfx" = "1" register "SkipExtGfxScan" = "1" + register "PrimaryDisplay" = "Display_Auto" register "Device4Enable" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" diff --git a/src/mainboard/google/glados/variants/lars/devicetree.cb b/src/mainboard/google/glados/variants/lars/devicetree.cb index f3f5eab..e33342a 100644 --- a/src/mainboard/google/glados/variants/lars/devicetree.cb +++ b/src/mainboard/google/glados/variants/lars/devicetree.cb @@ -33,6 +33,7 @@ register "ScsSdCardEnabled" = "0" register "InternalGfx" = "1" register "SkipExtGfxScan" = "1" + register "PrimaryDisplay" = "Display_Auto" register "Device4Enable" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" diff --git a/src/mainboard/google/glados/variants/sentry/devicetree.cb b/src/mainboard/google/glados/variants/sentry/devicetree.cb index 5cce0f0..65a5fee 100644 --- a/src/mainboard/google/glados/variants/sentry/devicetree.cb +++ b/src/mainboard/google/glados/variants/sentry/devicetree.cb @@ -35,6 +35,7 @@ register "ScsSdCardEnabled" = "2" register "InternalGfx" = "1" register "SkipExtGfxScan" = "1" + register "PrimaryDisplay" = "Display_Auto" register "Device4Enable" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb index 87d7348..43ee482 100644 --- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb +++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb @@ -51,6 +51,7 @@ register "PttSwitch" = "0" register "InternalGfx" = "1" register "SkipExtGfxScan" = "1" + register "PrimaryDisplay" = "Display_Auto" register "Device4Enable" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb index 7335c0a..ba681a8 100644 --- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb @@ -48,6 +48,7 @@ register "PttSwitch" = "0" register "InternalGfx" = "1" register "SkipExtGfxScan" = "1" + register "PrimaryDisplay" = "Display_Auto" register "Device4Enable" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb index 59cca29..d77a8d4 100644 --- a/src/mainboard/google/poppy/variants/nami/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb @@ -47,6 +47,7 @@ register "PttSwitch" = "0" register "InternalGfx" = "1" register "SkipExtGfxScan" = "1" + register "PrimaryDisplay" = "Display_Auto" register "Device4Enable" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb index fed85b6..8d4e6f8 100644 --- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb @@ -48,6 +48,7 @@ register "PttSwitch" = "0" register "InternalGfx" = "1" register "SkipExtGfxScan" = "1" + register "PrimaryDisplay" = "Display_Auto" register "Device4Enable" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb index ac52208..08899fc 100644 --- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb @@ -53,6 +53,7 @@ register "PttSwitch" = "0" register "InternalGfx" = "1" register "SkipExtGfxScan" = "1" + register "PrimaryDisplay" = "Display_Auto" register "Device4Enable" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb index 4f58f40..9285fa6 100644 --- a/src/mainboard/google/poppy/variants/rammus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb @@ -51,6 +51,7 @@ register "PttSwitch" = "0" register "InternalGfx" = "1" register "SkipExtGfxScan" = "1" + register "PrimaryDisplay" = "Display_Auto" register "Device4Enable" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb index d813cc1..6451523 100644 --- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb +++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb @@ -48,6 +48,7 @@ register "PttSwitch" = "0" register "InternalGfx" = "1" register "SkipExtGfxScan" = "1" + register "PrimaryDisplay" = "Display_Auto" register "Device4Enable" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" diff --git a/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb index fcd5aab..5098996 100644 --- a/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb @@ -29,6 +29,7 @@ register "ScsSdCardEnabled" = "2" register "InternalGfx" = "1" register "SkipExtGfxScan" = "1" + register "PrimaryDisplay" = "Display_Auto" register "Device4Enable" = "1" register "SaGv" = "SaGv_Enabled" diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb index ec1c11f..2f011d9 100644 --- a/src/mainboard/intel/kunimitsu/devicetree.cb +++ b/src/mainboard/intel/kunimitsu/devicetree.cb @@ -33,6 +33,7 @@ register "ScsSdCardEnabled" = "2" register "InternalGfx" = "1" register "SkipExtGfxScan" = "1" + register "PrimaryDisplay" = "Display_Auto" register "Device4Enable" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb index 2f84a5d..294f176b 100644 --- a/src/mainboard/intel/saddlebrook/devicetree.cb +++ b/src/mainboard/intel/saddlebrook/devicetree.cb @@ -41,6 +41,7 @@ register "ScsSdCardEnabled" = "0" register "InternalGfx" = "1" register "SkipExtGfxScan" = "1" + register "PrimaryDisplay" = "Display_Auto" register "Device4Enable" = "0" register "Heci3Enabled" = "0" diff --git a/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb b/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb index 8d2a436..b2b2377 100644 --- a/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb +++ b/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb @@ -59,6 +59,7 @@ register "InternalGfx" = "1" register "SkipExtGfxScan" = "1" register "Device4Enable" = "1" + register "PrimaryDisplay" = "Display_Auto" register "HeciEnabled" = "0" register "SaGv" = "3" register "PmConfigSlpS3MinAssert" = "2" # 50ms diff --git a/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb b/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb index 49af7b6..8968036 100644 --- a/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb +++ b/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb @@ -58,6 +58,7 @@ register "PttSwitch" = "0" register "InternalGfx" = "1" register "SkipExtGfxScan" = "1" + register "PrimaryDisplay" = "Display_Auto" register "Device4Enable" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" -- To view, visit https://review.coreboot.org/c/coreboot/+/32102 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibed05fc9171e2bd73654f0da6273a8534746913d Gerrit-Change-Number: 32102 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: util/sconfig: Emit array of PNP UART devices
by build bot (Jenkins) (Code Review) 01 Apr '19

01 Apr '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31934 ) Change subject: util/sconfig: Emit array of PNP UART devices ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/#/c/31934/4/util/sconfig/main.c File util/sconfig/main.c: https://review.coreboot.org/#/c/31934/4/util/sconfig/main.c@867 PS4, Line 867: fprintf(fil, "DEVTREE_CONST struct device *DEVTREE_CONST __pnp_serials[] = {"); line over 80 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/31934 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9330bcd5545ec3f94c1c14ed4a639f1ef0548e43 Gerrit-Change-Number: 31934 Gerrit-PatchSet: 4 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 01 Apr 2019 09:00:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: util/sconfig: Expose usable PCI and PNP device names
by build bot (Jenkins) (Code Review) 01 Apr '19

01 Apr '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31933 ) Change subject: util/sconfig: Expose usable PCI and PNP device names ...................................................................... Patch Set 4: (2 comments) https://review.coreboot.org/#/c/31933/4/util/sconfig/main.c File util/sconfig/main.c: https://review.coreboot.org/#/c/31933/4/util/sconfig/main.c@851 PS4, Line 851: fprintf(fil, "DEVTREE_CONST struct device *DEVTREE_CONST __pci_0_%02x_%d = &%s;\n", line over 80 characters https://review.coreboot.org/#/c/31933/4/util/sconfig/main.c@855 PS4, Line 855: fprintf(fil, "DEVTREE_CONST struct device *DEVTREE_CONST __pnp_%04x_%02x = &%s;\n", line over 80 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/31933 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I711058f5c809fa9bc7ea4333aaebad6847ebdfd4 Gerrit-Change-Number: 31933 Gerrit-PatchSet: 4 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 01 Apr 2019 09:00:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: device/pci: Rewrite PCI MMCONF with symbol reference
by build bot (Jenkins) (Code Review) 01 Apr '19

01 Apr '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31752 ) Change subject: device/pci: Rewrite PCI MMCONF with symbol reference ...................................................................... Patch Set 8: (4 comments) https://review.coreboot.org/#/c/31752/8/src/arch/x86/include/arch/pci_mmio_… File src/arch/x86/include/arch/pci_mmio_cfg_romcc.h: https://review.coreboot.org/#/c/31752/8/src/arch/x86/include/arch/pci_mmio_… PS8, Line 36: addr = (void *)(uintptr_t)(CONFIG_MMCONF_BASE_ADDRESS | dev | (reg & ~1)); line over 80 characters https://review.coreboot.org/#/c/31752/8/src/arch/x86/include/arch/pci_mmio_… PS8, Line 44: addr = (void *)(uintptr_t)(CONFIG_MMCONF_BASE_ADDRESS | dev | (reg & ~3)); line over 80 characters https://review.coreboot.org/#/c/31752/8/src/arch/x86/include/arch/pci_mmio_… PS8, Line 60: addr = (void *)(uintptr_t)(CONFIG_MMCONF_BASE_ADDRESS | dev | (reg & ~1)); line over 80 characters https://review.coreboot.org/#/c/31752/8/src/arch/x86/include/arch/pci_mmio_… PS8, Line 68: addr = (void *)(uintptr_t)(CONFIG_MMCONF_BASE_ADDRESS | dev | (reg & ~3)); line over 80 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/31752 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id112aa5e729ffd8015bb806786bdee38783b7ea9 Gerrit-Change-Number: 31752 Gerrit-PatchSet: 8 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Mon, 01 Apr 2019 08:59:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: mb/google/fizz/variants/karma: Clear GPP_B4 when entering S5
by Zhuohao Lee (Code Review) 01 Apr '19

01 Apr '19

Zhuohao Lee has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29796 ) Change subject: mb/google/fizz/variants/karma: Clear GPP_B4 when entering S5 ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/#/c/29796/2/src/mainboard/google/fizz/variants/… File src/mainboard/google/fizz/variants/karma/smihandler.c: https://review.coreboot.org/#/c/29796/2/src/mainboard/google/fizz/variants/… PS2, Line 4: 2018 > This CL is from November, so 2018 is correct Done. ok -- To view, visit https://review.coreboot.org/c/coreboot/+/29796 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I65deb33a45fdc0c0ce64deaa29c2790029dc1d12 Gerrit-Change-Number: 29796 Gerrit-PatchSet: 2 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 01 Apr 2019 08:39:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Zhuohao Lee <zhuohao(a)chromium.org> Comment-In-Reply-To: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/google/fizz/variants/karma: Clear GPP_B4 when entering S5
by Patrick Georgi (Code Review) 01 Apr '19

01 Apr '19

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29796 ) Change subject: mb/google/fizz/variants/karma: Clear GPP_B4 when entering S5 ...................................................................... Patch Set 2: Code-Review+1 (1 comment) LGTM but I'd prefer somebody who knows fizz/karma better to +2 it. https://review.coreboot.org/#/c/29796/2/src/mainboard/google/fizz/variants/… File src/mainboard/google/fizz/variants/karma/smihandler.c: https://review.coreboot.org/#/c/29796/2/src/mainboard/google/fizz/variants/… PS2, Line 4: 2018 > 2019 This CL is from November, so 2018 is correct -- To view, visit https://review.coreboot.org/c/coreboot/+/29796 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I65deb33a45fdc0c0ce64deaa29c2790029dc1d12 Gerrit-Change-Number: 29796 Gerrit-PatchSet: 2 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 01 Apr 2019 08:32:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/google/fizz/variants/karma: Clear GPP_B4 when entering S5
by Zhuohao Lee (Code Review) 01 Apr '19

01 Apr '19

Zhuohao Lee has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29796 ) Change subject: mb/google/fizz/variants/karma: Clear GPP_B4 when entering S5 ...................................................................... Patch Set 2: Code-Review+1 (1 comment) https://review.coreboot.org/#/c/29796/2/src/mainboard/google/fizz/variants/… File src/mainboard/google/fizz/variants/karma/smihandler.c: https://review.coreboot.org/#/c/29796/2/src/mainboard/google/fizz/variants/… PS2, Line 4: 2018 2019 -- To view, visit https://review.coreboot.org/c/coreboot/+/29796 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I65deb33a45fdc0c0ce64deaa29c2790029dc1d12 Gerrit-Change-Number: 29796 Gerrit-PatchSet: 2 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 01 Apr 2019 08:25:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: util/spdtool: Add tool to extract SPD from BLOBs
by Patrick Rudolph (Code Review) 01 Apr '19

01 Apr '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31385 Change subject: util/spdtool: Add tool to extract SPD from BLOBs ...................................................................... util/spdtool: Add tool to extract SPD from BLOBs Opens a binary file to extract DDR SPDs using known bits. At the moment only DDR4 SPDs are supported. Dumps the found SPDs into the current folder, as either binary or hex encoded file. Works with python2 and python3. Change-Id: I26dd73d43b724ea6891bb5b6e96856c42db8577c Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- A util/spdtool/description.md A util/spdtool/spdtool.py 2 files changed, 221 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/31385/1 diff --git a/util/spdtool/description.md b/util/spdtool/description.md new file mode 100644 index 0000000..39d4a5c --- /dev/null +++ b/util/spdtool/description.md @@ -0,0 +1,3 @@ +Dumps SPD ROMs from a given blob to seperate files using known patterns +and reserved bits. Useful for analysing firmware that holds SPDs on boards +that have soldered down DRAM. `python` diff --git a/util/spdtool/spdtool.py b/util/spdtool/spdtool.py new file mode 100644 index 0000000..c20ee57 --- /dev/null +++ b/util/spdtool/spdtool.py @@ -0,0 +1,218 @@ +#!/usr/bin/env python + +# spdtool - Tool for partial deblobbing of Intel ME/TXE firmware images +# Copyright (C) 2019 9elements Agency GmbH <patrick.rudolph(a)9elements.com> +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# +# Parse a BLOB and search for SPD files. +# First it is searched for a possible SPD header. +# +# For each candidate the function verify_match is invoked to check +# additional fields (known bits, reserved bits, CRC, ...) +# +# Dumps the found SPDs into the current folder. +# +# Implemented: +# DDR4 SPDs +# + +import argparse +import crc16 +import struct + +class Parser(object): + def __init__(self, blob, verbose=False, ignorecrc=False): + self.blob = blob + self.ignorecrc = ignorecrc + self.verbose = verbose + def get_matches(self): + """Return the first byte to look for""" + raise Exception("Function not implemented") + def verify_match(self, header, offset): + """Return true if it looks like a SPD""" + raise Exception("Function not implemented") + def get_len(self, header, offset): + """Return the length of the SPD""" + raise Exception("Function not implemented") + def get_part_number(self, offset): + """Return the part number in SPD""" + return "" + def get_manufacturer_id(self, offset): + """Return the manufacturer ID in SPD""" + return 0xffff + def get_mtransfers(self, offset): + """Return the number of MT/s""" + return 0 + + def get_manufacturer(self, offset): + """Return manufacturer as string""" + id = self.get_manufacturer_id(offset) + if id == 0xffff: + return "Unknown" + ids = { + 0x2c80: "Crucial/Micron", + 0x4304: "Ramaxel", + 0x4f01: "Transcend", + 0x9801: "Kingston", + 0x987f: "Hynix", + 0x9e02: "Corsair", + 0xb004: "OCZ", + 0xad80: "Hynix/Hyundai", + 0xb502: "SuperTalent", + 0xcd04: "GSkill", + 0xce80: "Samsung", + 0xfe02: "Elpida", + 0xff2c: "Micron", + } + if id in ids: + return ids[id] + return "Unknown" + + def blob_as_ord(self, offset): + """Helper for python2/python3 compability""" + return self.blob[offset] if type(self.blob[offset]) is int else ord(self.blob[offset]) + + def search(self, start): + """Search for SPD at start. Returns -1 on error or offset + if found. + """ + for i in self.get_matches(): + for offset in range(start, len(self.blob)): + if self.blob_as_ord(offset) != i: + continue + if not self.verify_match(i, offset): + continue + return offset, self.get_len(i, offset) + return -1, 0 + +class SPD4Parser(Parser): + def get_matches(self): + """Return DDR4 possible header candidates""" + ret = [] + for i in [1, 2, 3, 4]: + for j in [1, 2]: + ret.append(i + j * 16) + return ret + + def verify_match(self, header, offset): + """Verify DDR4 specific bit fields.""" + # offset 0 is a candidate, no need to validate + if self.blob_as_ord(offset + 1) == 0xff: + return False + if self.blob_as_ord(offset + 2) != 0x0c: + return False + if self.blob_as_ord(offset + 5) & 0xc0 > 0: + return False + if self.blob_as_ord(offset + 6) & 0xc > 0: + return False + if self.blob_as_ord(offset + 7) & 0xc0 > 0: + return False + if self.blob_as_ord(offset + 8) != 0: + return False + if self.blob_as_ord(offset + 9) & 0xf > 0: + return False + if self.verbose: + print("%x: Looks like DDR4 SPD" % offset) + + crc = crc16.crc16xmodem(self.blob[offset:offset + 0x7d + 1]) + # Vendors ignore the endianness... + crc_spd1 = self.blob_as_ord(offset + 0x7f) | (self.blob_as_ord(offset + 0x7e) << 8) + crc_spd2 = self.blob_as_ord(offset + 0x7e) | (self.blob_as_ord(offset + 0x7f) << 8) + if crc != crc_spd1 and crc != crc_spd2: + if self.verbose: + print("%x: CRC16 doesn't match" % offset) + if not self.ignorecrc: + return False + + return True + + def get_len(self, header, offset): + """Return the length of the SPD found.""" + if (header >> 4) & 7 == 1: + return 256 + if (header >> 4) & 7 == 2: + return 512 + return 0 + + def get_part_number(self, offset): + """Return part number as string""" + if offset + 0x15c > len(self.blob): + return "" + return self.blob[offset + 0x149:offset + 0x15c + 1].decode('utf-8').rstrip() + + def get_manufacturer_id(self, offset): + """Return manufacturer ID""" + if offset + 0x141 > len(self.blob): + return 0xffff + return struct.unpack('H', self.blob[offset + 0x140:offset + 0x141 + 1])[0] + + def get_mtransfers(self, offset): + """Return MT/s as specified by MTB and FTB""" + if offset + 0x7d > len(self.blob): + return 0 + + if self.blob_as_ord(offset + 0x11) != 0: + return 0 + mtb = 8.0 + ftb = 1000.0 + tckm = struct.unpack('B', self.blob[offset + 0x12:offset + 0x12 + 1])[0] + tckf = struct.unpack('b', self.blob[offset + 0x7d:offset + 0x7d + 1])[0] + return int(2000 / (tckm / mtb + tckf / ftb)) + +if __name__ == "__main__": + parser = argparse.ArgumentParser(description='SPD rom dumper') + parser.add_argument('--blob', required=True, + help='The ROM to search SPDs in.') + parser.add_argument('--spd4', action='store_true', default=False, + help='Search for DDR4 SPDs.') + parser.add_argument('--hex', action='store_true', default=False, + help='Store SPD in hex format otherwise binary.') + parser.add_argument('-v', '--verbose', help='increase output verbosity', + action='store_true') + parser.add_argument('--ignorecrc', help='Ignore CRC missmatch', + action='store_true', default=False) + args = parser.parse_args() + + blob = open(args.blob, "rb").read() + + if args.spd4: + p = SPD4Parser(blob, args.verbose, args.ignorecrc) + else: + raise Exception("Must specify one of the following arguments:\n--spd4") + + offset = 0 + length = 0 + cnt = 0 + while True: + offset, length = p.search(offset) + if length == 0: + break + print("Found SPD at 0x%x" % offset) + print(" '%s', size %d, manufacturer %s (0x%04x) %d MT/s\n" % + (p.get_part_number(offset), length, p.get_manufacturer(offset), + p.get_manufacturer_id(offset), p.get_mtransfers(offset))) + filename = "spd-%d-%s-%s.bin" % (cnt, p.get_part_number(offset), + p.get_manufacturer(offset)) + filename = filename.replace("/", "_") + filename = "".join([c for c in filename if c.isalpha() or c.isdigit() or c=='-' or c=='.' or c=='_']).rstrip() + if not args.hex: + open(filename, "wb").write(blob[offset:offset + length]) + else: + filename += ".hex" + fn = open(filename, "w") + j = 0 + for i in blob[offset:offset + length]: + fn.write("%02X%s" % (struct.unpack('B',i)[0], " " if j < 15 else "\n")) + j = (j + 1) % 16 + offset += 1 + cnt += 1 -- To view, visit https://review.coreboot.org/c/coreboot/+/31385 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I26dd73d43b724ea6891bb5b6e96856c42db8577c Gerrit-Change-Number: 31385 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: payloads/coreinfo: Free buffer before returning
by Jacob Garber (Code Review) 01 Apr '19

01 Apr '19

Jacob Garber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32094 Change subject: payloads/coreinfo: Free buffer before returning ...................................................................... payloads/coreinfo: Free buffer before returning This resolves CID 1373370 (RESOURCE_LEAK), which was partially fixed in 2d1e0eb. Signed-off-by: Jacob Garber <jgarber1(a)ualberta.ca> Change-Id: I0efe94b9dfb27746828055427029c01c7f407ec2 --- M payloads/coreinfo/timestamps_module.c 1 file changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/32094/1 diff --git a/payloads/coreinfo/timestamps_module.c b/payloads/coreinfo/timestamps_module.c index 0978f31..fe2d2b5 100644 --- a/payloads/coreinfo/timestamps_module.c +++ b/payloads/coreinfo/timestamps_module.c @@ -203,8 +203,10 @@ SCREEN_X, LINES_SHOWN); /* Sanity check, chars_count must be padded to full line */ - if (chars_count % SCREEN_X != 0) + if (chars_count % SCREEN_X != 0) { + free(buffer); return -2; + } g_lines_count = chars_count / SCREEN_X; g_max_cursor_line = MAX(g_lines_count - 1 - LINES_SHOWN, 0); -- To view, visit https://review.coreboot.org/c/coreboot/+/32094 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0efe94b9dfb27746828055427029c01c7f407ec2 Gerrit-Change-Number: 32094 Gerrit-PatchSet: 1 Gerrit-Owner: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-MessageType: newchange

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