Krishna P Bhat D has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32111
Change subject: mb/google/hatch: Re-configure GPP_A12 as GPO before entering sleep
......................................................................
mb/google/hatch: Re-configure GPP_A12 as GPO before entering sleep
GPP_A12 has a Native3 (SX_EXIT_HOLDOFF#) mode, which allows to delay
resuming to S0. If this pad is not locked and platform was not initially
designed for this functionality, malware could reconfigure this pads
setting under OS (switch to Native3), which would make platform not able
to resume until G3 is applied. To prevent misuse of this pad,
re-configure this pad before entering S3 and S5 to guarantee that the
pad configuration is correct.
BUG=b:128686027
Change-Id: I1e7979baa491acf2c56d223afb4618f0f6429e37
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d(a)intel.com>
---
M src/mainboard/google/hatch/variants/baseboard/gpio.c
1 file changed, 6 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/32111/1
diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c
index b974e49..8529d5916 100644
--- a/src/mainboard/google/hatch/variants/baseboard/gpio.c
+++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c
@@ -411,8 +411,12 @@
return gpio_table;
}
-/* Default GPIO settings before entering sleep. */
+/*
+ * Default GPIO settings before entering sleep. Configure A12: FPMCU_RST_ODL
+ * as GPO before entering sleep.
+ */
static const struct pad_config default_sleep_gpio_table[] = {
+ PAD_CFG_GPO(GPP_A12, 1, DEEP), /* FPMCU_RST_ODL */
};
/*
@@ -421,6 +425,7 @@
* turn off EN_PP3300_WWAN.
*/
static const struct pad_config s5_sleep_gpio_table[] = {
+ PAD_CFG_GPO(GPP_A12, 1, DEEP), /* FPMCU_RST_ODL */
PAD_CFG_GPO(GPP_A18, 0, DEEP), /* EN_PP3300_WWAN */
};
--
To view, visit https://review.coreboot.org/c/coreboot/+/32111
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I1e7979baa491acf2c56d223afb4618f0f6429e37
Gerrit-Change-Number: 32111
Gerrit-PatchSet: 1
Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com>
Gerrit-MessageType: newchange
Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30218 )
Change subject: vendorcode/eltan: Add vendor code for measured and verified boot
......................................................................
Patch Set 9:
(3 comments)
https://review.coreboot.org/#/c/30218/9/Documentation/vendorcode/eltan/secu…
File Documentation/vendorcode/eltan/security.md:
https://review.coreboot.org/#/c/30218/9/Documentation/vendorcode/eltan/secu…
PS9, Line 11: `3rdparty/vboot/firmware/2lib` are used.
Whitespace
https://review.coreboot.org/#/c/30218/9/Documentation/vendorcode/eltan/secu…
PS9, Line 18: verified boot support will use TPM2 device if available. The items specified
Whitespace
https://review.coreboot.org/#/c/30218/9/MAINTAINERS
File MAINTAINERS:
https://review.coreboot.org/#/c/30218/9/MAINTAINERS@619
PS9, Line 619: ELTAN VENDORCODE
MAINTAINERS changes must be done in an additional commit
--
To view, visit https://review.coreboot.org/c/coreboot/+/30218
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ic1d5a21d40b6a31886777e8e9fe7b28c860f1a80
Gerrit-Change-Number: 30218
Gerrit-PatchSet: 9
Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com>
Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com>
Gerrit-Reviewer: Martin Roth <martinroth(a)google.com>
Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com>
Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com>
Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-CC: Nico Huber <nico.h(a)gmx.de>
Gerrit-CC: Patrick Rudolph
Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net>
Gerrit-Comment-Date: Tue, 02 Apr 2019 07:39:16 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: No
Gerrit-MessageType: comment
Ronak Kanabar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31928 )
Change subject: soc/intel/cannonlake: enable VMX support
......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/#/c/31928/4/src/soc/intel/cannonlake/cpu.c
File src/soc/intel/cannonlake/cpu.c:
https://review.coreboot.org/#/c/31928/4/src/soc/intel/cannonlake/cpu.c@410
PS4, Line 410: VmxEnable is set and VtdDisable
> I asked there, too and didn't get an answer so far. Why disable VT-x […]
I will get back to you on this.
--
To view, visit https://review.coreboot.org/c/coreboot/+/31928
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I33dbffa6301afabd688080751ba3b85a43e00156
Gerrit-Change-Number: 31928
Gerrit-PatchSet: 5
Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com>
Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com>
Gerrit-Reviewer: Martin Roth <martinroth(a)google.com>
Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com>
Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com>
Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com>
Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Nico Huber <nico.h(a)gmx.de>
Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net>
Gerrit-CC: RONAK KANABAR <ronak199323(a)gmail.com>
Gerrit-CC: Thomas Heijligen <src(a)posteo.de>
Gerrit-Comment-Date: Tue, 02 Apr 2019 05:31:48 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: No
Comment-In-Reply-To: Ronak Kanabar <ronak.kanabar(a)intel.com>
Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de>
Comment-In-Reply-To: Patrick Georgi <pgeorgi(a)google.com>
Gerrit-MessageType: comment
Subrata Banik has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/32079 )
Change subject: drivers/intel/fsp2_0: Use same stack with coreboot
......................................................................
drivers/intel/fsp2_0: Use same stack with coreboot
This patch ensures to have same stack base for FSP and coreboot.
Feature added in FSP2.1
- Remove stack swapping from FSP.
- Stack will be shared between coreboot and FSP.
TEST=Build and boot FSP2.1 enable platform like dragonegg, iclrvp.
No car global variable corruption seen after enabling
this feature.
Change-Id: I673b4216d991d8ccad725c3931006a694184106c
Signed-off-by: Subrata Banik <subrata.banik(a)intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32079
Reviewed-by: Patrick Rudolph <siro(a)das-labor.org>
Reviewed-by: Furquan Shaikh <furquan(a)google.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/drivers/intel/fsp2_0/memory_init.c
1 file changed, 1 insertion(+), 1 deletion(-)
Approvals:
build bot (Jenkins): Verified
Furquan Shaikh: Looks good to me, approved
Patrick Rudolph: Looks good to me, approved
diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c
index f7cf0dd..985ee3a 100644
--- a/src/drivers/intel/fsp2_0/memory_init.c
+++ b/src/drivers/intel/fsp2_0/memory_init.c
@@ -172,7 +172,7 @@
* top and does not reinitialize stack pointer.
*/
if (CONFIG(FSP_USES_CB_STACK)) {
- arch_upd->StackBase = (void *)_car_stack_end;
+ arch_upd->StackBase = (void *)_car_stack_start;
arch_upd->StackSize = CONFIG_DCACHE_BSP_STACK_SIZE;
return CB_SUCCESS;
}
--
To view, visit https://review.coreboot.org/c/coreboot/+/32079
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I673b4216d991d8ccad725c3931006a694184106c
Gerrit-Change-Number: 32079
Gerrit-PatchSet: 4
Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com>
Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com>
Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org>
Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org>
Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com>
Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com>
Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com>
Gerrit-Reviewer: Shelley Chen <shchen(a)google.com>
Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net>
Gerrit-MessageType: merged
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32079 )
Change subject: drivers/intel/fsp2_0: Use same stack with coreboot
......................................................................
Patch Set 3: Code-Review+2
(1 comment)
https://review.coreboot.org/#/c/32079/3//COMMIT_MSG
Commit Message:
https://review.coreboot.org/#/c/32079/3//COMMIT_MSG@9
PS3, Line 9: This patch ensures to have same stack base for FSP and coreboot.
:
: Feature added in FSP2.1
: - Remove stack swapping from FSP.
: - Stack will be shared between coreboot and FSP.
> that was the actual intention at that time but if you calculate stack usage in CB:28358 then you wil […]
okay.
--
To view, visit https://review.coreboot.org/c/coreboot/+/32079
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I673b4216d991d8ccad725c3931006a694184106c
Gerrit-Change-Number: 32079
Gerrit-PatchSet: 3
Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com>
Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com>
Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org>
Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org>
Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com>
Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com>
Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com>
Gerrit-Reviewer: Shelley Chen <shchen(a)google.com>
Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net>
Gerrit-Comment-Date: Tue, 02 Apr 2019 00:30:27 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: Yes
Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com>
Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com>
Gerrit-MessageType: comment
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29796 )
Change subject: mb/google/fizz/variants/karma: Clear GPP_B4 when entering S5
......................................................................
Patch Set 2:
(2 comments)
https://review.coreboot.org/#/c/29796/2//COMMIT_MSG
Commit Message:
https://review.coreboot.org/#/c/29796/2//COMMIT_MSG@11
PS2, Line 11: BUG=b:124197348
Linked bug has no details about why this is required. Also, the bug talks about suspend stress test which is using S3 and this change seems to affect only S5.
https://review.coreboot.org/#/c/29796/2/src/mainboard/google/fizz/variants/…
File src/mainboard/google/fizz/variants/karma/smihandler.c:
https://review.coreboot.org/#/c/29796/2/src/mainboard/google/fizz/variants/…
PS2, Line 24: ACPI_S5
Do you need this for S3 too?
--
To view, visit https://review.coreboot.org/c/coreboot/+/29796
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I65deb33a45fdc0c0ce64deaa29c2790029dc1d12
Gerrit-Change-Number: 29796
Gerrit-PatchSet: 2
Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com>
Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com>
Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com>
Gerrit-Reviewer: Martin Roth <martinroth(a)google.com>
Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com>
Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)chromium.org>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Comment-Date: Mon, 01 Apr 2019 19:17:24 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: No
Gerrit-MessageType: comment
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/28395 )
Change subject: nb/intel/i945: Correct SLP_S4# comment
......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/#/c/28395/1//COMMIT_MSG
Commit Message:
https://review.coreboot.org/#/c/28395/1//COMMIT_MSG@7
PS1, Line 7: nb/intel/i945: Correct SLP_S4# comment
intel/i945,i82801g: Correct SLP_S4# comment
Motivation for topic line change is that the bit is really in the
southbridge device, while code is in northbridge.
--
To view, visit https://review.coreboot.org/c/coreboot/+/28395
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I86df0df5337397d2c23ca311ecae1c8a38eb32f0
Gerrit-Change-Number: 28395
Gerrit-PatchSet: 1
Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Gerrit-Comment-Date: Mon, 01 Apr 2019 18:54:43 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: No
Gerrit-MessageType: comment