April 2019 - coreboot-gerrit - mail.coreboot.org

Change in ...coreboot[master]: assert: Don't stringify 'message' in dead_code()
by Julius Werner (Code Review) April 1, 2019

April 1, 2019

Julius Werner has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32113 Change subject: assert: Don't stringify 'message' in dead_code() ...................................................................... assert: Don't stringify 'message' in dead_code() dead_code() is already supposed to be called with a string message, we don't need to stringify the argument again (and doing so makes the output look a bit weird). Change-Id: I63399dc484e2150d8c027bc0256d9285e471f7cc Signed-off-by: Julius Werner <jwerner(a)chromium.org> --- M src/include/assert.h 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/32113/1 diff --git a/src/include/assert.h b/src/include/assert.h index afbed03..6a442d6 100644 --- a/src/include/assert.h +++ b/src/include/assert.h @@ -45,7 +45,7 @@ * valid if a certain Kconfig option is set. */ #define __dead_code(message, line) do { \ - __attribute__((error(#message " in " __FILE__ ":" #line))) \ + __attribute__((error(message " in " __FILE__ ":" #line))) \ extern void dead_code_assertion_failed_##line(void); \ dead_code_assertion_failed_##line(); \ } while (0) -- To view, visit https://review.coreboot.org/c/coreboot/+/32113 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I63399dc484e2150d8c027bc0256d9285e471f7cc Gerrit-Change-Number: 32113 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: vboot: Select CONFIG_VBOOT_OPROM_MATTERS in more cases
by Julius Werner (Code Review) April 1, 2019

April 1, 2019

Hello Furquan Shaikh, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/32114 to review the following change. Change subject: vboot: Select CONFIG_VBOOT_OPROM_MATTERS in more cases ...................................................................... vboot: Select CONFIG_VBOOT_OPROM_MATTERS in more cases This patch enables CONFIG_VBOOT_OPROM_MATTERS in a few more cases where I think(?) it should be. Haswell, Broadwell and Baytrail Chromebooks have this enabled in their old depthcharge firmware branches -- we presumably just forgot to move it over when vboot2 migrated the option to coreboot. Braswell didn't, but it seems like this requirement was added when it was migrated to FSP 1.1...? (Not very sure about that one, but it does call load_vbt() right now which executes things based on display_init_required().) Additionally, it seems to make sense to enable it whenever the user explicitly selects VGA_ROM_RUN in menuconfig (like one of the Intel defconfigs does). Once we have all this, one could take a step back and ask whether this option still makes sense at all anymore. It's enabled for almost all devices (that work with vboot at all), it will presumably be enabled for all future devices, and it seems that most devices that don't enable it use libgfxinit, which as far as I can tell isn't gated on display_init_required() but probably should be. Realistically, whatever kind of display init a board needs to do (native or option ROM), it's probably expensive enough that it's worth skipping on a normal mode vboot boot, and we'd want to have this enabled by default on everything except boards that actually don't have a display. So maybe we should flip it around to CONFIG_VBOOT_OPROM_DOESNT_MATTER, but doing that would probably lead to nobody ever selecting it at all. Not sure what the best solution there is yet, but I think this patch at least moves things in the more correct direction. Change-Id: Id96a88296ddb9cfbb58ea67d93e1638d95570e2c Signed-off-by: Julius Werner <jwerner(a)chromium.org> --- M src/northbridge/intel/haswell/Kconfig M src/security/vboot/Kconfig M src/soc/intel/baytrail/Kconfig M src/soc/intel/braswell/Kconfig M src/soc/intel/broadwell/Kconfig 5 files changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/32114/1 diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig index 0362ffe..082f2d6 100644 --- a/src/northbridge/intel/haswell/Kconfig +++ b/src/northbridge/intel/haswell/Kconfig @@ -26,6 +26,7 @@ if NORTHBRIDGE_INTEL_HASWELL config VBOOT + select VBOOT_OPROM_MATTERS select VBOOT_STARTS_IN_ROMSTAGE config BOOTBLOCK_NORTHBRIDGE_INIT diff --git a/src/security/vboot/Kconfig b/src/security/vboot/Kconfig index ca25423..a0cfca5 100644 --- a/src/security/vboot/Kconfig +++ b/src/security/vboot/Kconfig @@ -171,6 +171,7 @@ config VBOOT_OPROM_MATTERS bool + default y if VGA_ROM_RUN default n help Set this option to indicate to vboot that this platform will skip its diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index e824ee4..a83a7e9 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -43,6 +43,7 @@ select CPU_HAS_L2_ENABLE_MSR config VBOOT + select VBOOT_OPROM_MATTERS select VBOOT_STARTS_IN_ROMSTAGE config BOOTBLOCK_CPU_INIT diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index fda5a6d..8db4795 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -53,6 +53,7 @@ select SOUTHBRIDGE_INTEL_COMMON_SMBUS config VBOOT + select VBOOT_OPROM_MATTERS select VBOOT_STARTS_IN_ROMSTAGE config BOOTBLOCK_CPU_INIT diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 1a8349d0..5f503da 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -65,6 +65,7 @@ default y config VBOOT + select VBOOT_OPROM_MATTERS select VBOOT_STARTS_IN_ROMSTAGE config BOOTBLOCK_CPU_INIT -- To view, visit https://review.coreboot.org/c/coreboot/+/32114 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id96a88296ddb9cfbb58ea67d93e1638d95570e2c Gerrit-Change-Number: 32114 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/sarien: Enable Bluetooth RF kill
by Lijian Zhao (Code Review) April 1, 2019

April 1, 2019

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32124 Change subject: mb/google/sarien: Enable Bluetooth RF kill ...................................................................... mb/google/sarien: Enable Bluetooth RF kill Add bluetooth Rfkill function to recover the Bluetooth controller in cases where itself has entered a bad state and needs to be recovered. Bug=b:123342945 TEST=Boot up into OS and dump SSDT table, check there's _DSD entry under Bluetooth devices with GPIO in. Also confirm bluetooth itself is functional. Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> Change-Id: I79a310a55d94d7d20d1705afc11fe47cbb81abc1 --- M src/mainboard/google/sarien/variants/sarien/devicetree.cb 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/32124/1 diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index 2714b60..72dea1e 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -264,6 +264,7 @@ chip drivers/usb/acpi register "desc" = ""Bluetooth"" register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H15)" device usb 2.9 on end end chip drivers/usb/acpi -- To view, visit https://review.coreboot.org/c/coreboot/+/32124 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I79a310a55d94d7d20d1705afc11fe47cbb81abc1 Gerrit-Change-Number: 32124 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: cpu/ti/am335x: Fix checkpatch warnings
by Daniel Lim Wee Soong (Code Review) April 1, 2019

April 1, 2019

Daniel Lim Wee Soong has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32119 Change subject: cpu/ti/am335x: Fix checkpatch warnings ...................................................................... cpu/ti/am335x: Fix checkpatch warnings Replace occurences of 'unsigned' with 'unsigned int' to fix WARNING: Prefer 'unsigned int' to bare use of 'unsigned' Signed-off-by: Daniel Lim Wee Soong <weesoong.lim(a)gmail.com> Change-Id: I94665e8fcb4719521d143774aa84f630b10ee68a --- M src/cpu/ti/am335x/gpio.c M src/cpu/ti/am335x/gpio.h 2 files changed, 11 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/32119/1 diff --git a/src/cpu/ti/am335x/gpio.c b/src/cpu/ti/am335x/gpio.c index e1c6967..2685839 100644 --- a/src/cpu/ti/am335x/gpio.c +++ b/src/cpu/ti/am335x/gpio.c @@ -18,9 +18,10 @@ #include <stdint.h> #include <stdlib.h> -static struct am335x_gpio_regs *gpio_regs_and_bit(unsigned gpio, uint32_t *bit) +static struct am335x_gpio_regs *gpio_regs_and_bit(unsigned int gpio, + uint32_t *bit) { - unsigned bank = gpio / AM335X_GPIO_BITS_PER_BANK; + unsigned int bank = gpio / AM335X_GPIO_BITS_PER_BANK; if (bank >= ARRAY_SIZE(am335x_gpio_banks)) { printk(BIOS_ERR, "Bad gpio index %d.\n", gpio); @@ -38,7 +39,7 @@ write32(&am335x_gpio_banks[i]->irqstatus_clr_0, 0xffffffff); } -int gpio_direction_input(unsigned gpio) +int gpio_direction_input(unsigned int gpio) { uint32_t bit; struct am335x_gpio_regs *regs = gpio_regs_and_bit(gpio, &bit); @@ -49,7 +50,7 @@ return 0; } -int gpio_direction_output(unsigned gpio, int value) +int gpio_direction_output(unsigned int gpio, int value) { uint32_t bit; struct am335x_gpio_regs *regs = gpio_regs_and_bit(gpio, &bit); @@ -64,7 +65,7 @@ return 0; } -int gpio_get_value(unsigned gpio) +int gpio_get_value(unsigned int gpio) { uint32_t bit; struct am335x_gpio_regs *regs = gpio_regs_and_bit(gpio, &bit); @@ -74,7 +75,7 @@ return (read32(&regs->datain) & bit) ? 1 : 0; } -int gpio_set_value(unsigned gpio, int value) +int gpio_set_value(unsigned int gpio, int value) { uint32_t bit; struct am335x_gpio_regs *regs = gpio_regs_and_bit(gpio, &bit); diff --git a/src/cpu/ti/am335x/gpio.h b/src/cpu/ti/am335x/gpio.h index c04a00c..616c0af 100644 --- a/src/cpu/ti/am335x/gpio.h +++ b/src/cpu/ti/am335x/gpio.h @@ -62,9 +62,9 @@ void am335x_disable_gpio_irqs(void); -int gpio_direction_input(unsigned gpio); -int gpio_direction_output(unsigned gpio, int value); -int gpio_get_value(unsigned gpio); -int gpio_set_value(unsigned gpio, int value); +int gpio_direction_input(unsigned int gpio); +int gpio_direction_output(unsigned int gpio, int value); +int gpio_get_value(unsigned int gpio); +int gpio_set_value(unsigned int gpio, int value); #endif /* __CPU_TI_AM335X_CLOCK_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/32119 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I94665e8fcb4719521d143774aa84f630b10ee68a Gerrit-Change-Number: 32119 Gerrit-PatchSet: 1 Gerrit-Owner: Daniel Lim Wee Soong <weesoong.lim(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/hatch: Unlock GPIO pads
by Krishna P Bhat D (Code Review) April 1, 2019

April 1, 2019

Krishna P Bhat D has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32126 Change subject: mb/google/hatch: Unlock GPIO pads ...................................................................... mb/google/hatch: Unlock GPIO pads GPP_A12 is being used as FPMCU_RST in hatch. This GPIO is being padlocked in FSP and cannot used in kernel. Hence unlock the GPIO pads to export this pin in kernel to be used as FPMCU_RST. BUG=b:128686027 Change-Id: Ie0439956e6c8e386435e535665ccaf2ab82adeb0 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d(a)intel.com> --- M src/mainboard/google/hatch/variants/baseboard/devicetree.cb 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/32126/1 diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index dc7cc24..984852f 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -73,6 +73,8 @@ register "DdiPortBHpd" = "1" register "DdiPortCHpd" = "1" register "tcc_offset" = "10" # TCC of 90C + # Unlock GPIO pads + register "PchUnlockGpioPads" = "1" register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC2)" # Type-C Port 0 register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC2)" # Type-C Port 1 -- To view, visit https://review.coreboot.org/c/coreboot/+/32126 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie0439956e6c8e386435e535665ccaf2ab82adeb0 Gerrit-Change-Number: 32126 Gerrit-PatchSet: 1 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/hatch: Set UPD to unlock GPP_A12 to use FPMCU_RST
by Krishna P Bhat D (Code Review) April 1, 2019

April 1, 2019

Krishna P Bhat D has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32110 Change subject: mb/google/hatch: Set UPD to unlock GPP_A12 to use FPMCU_RST ...................................................................... mb/google/hatch: Set UPD to unlock GPP_A12 to use FPMCU_RST GPP_A12 is being GPIO padlocked and cannot used in kernel. Unlock the GPIO pads to export this pin in kernel to be used as FPMCU_RST. GPP_A_12 has a Native3 (SX_EXIT_HOLDOFF#) mode, which allows to delay resuming to S0. If this pad is not locked and platform was not initially designed for this functionality, malware could reconfigure this pads setting under OS (switch to Native3), which would make platform not able to resume until G3 is applied. To prevent misuse of this pad, re-configure this pad before entering S3 and S5 to guarantee that the pad configuration is correct. BUG=b:128686027 Change-Id: Iad9e8a209dc3f8ca0c994e8c1da329918409a1d4 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d(a)intel.com> --- M src/mainboard/google/hatch/variants/baseboard/gpio.c M src/soc/intel/cannonlake/fsp_params.c 2 files changed, 9 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/32110/1 diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c index b974e49..8529d5916 100644 --- a/src/mainboard/google/hatch/variants/baseboard/gpio.c +++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c @@ -411,8 +411,12 @@ return gpio_table; } -/* Default GPIO settings before entering sleep. */ +/* + * Default GPIO settings before entering sleep. Configure A12: FPMCU_RST_ODL + * as GPO before entering sleep. + */ static const struct pad_config default_sleep_gpio_table[] = { + PAD_CFG_GPO(GPP_A12, 1, DEEP), /* FPMCU_RST_ODL */ }; /* @@ -421,6 +425,7 @@ * turn off EN_PP3300_WWAN. */ static const struct pad_config s5_sleep_gpio_table[] = { + PAD_CFG_GPO(GPP_A12, 1, DEEP), /* FPMCU_RST_ODL */ PAD_CFG_GPO(GPP_A18, 0, DEEP), /* EN_PP3300_WWAN */ }; diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index 6173403..57d004f 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -328,6 +328,9 @@ /* Set TccActivationOffset */ tconfig->TccActivationOffset = config->tcc_offset; + + /* Unlock all GPIO pads */ + tconfig->PchUnlockGpioPads = 1; } /* Mainboard GPIO Configuration */ -- To view, visit https://review.coreboot.org/c/coreboot/+/32110 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iad9e8a209dc3f8ca0c994e8c1da329918409a1d4 Gerrit-Change-Number: 32110 Gerrit-PatchSet: 1 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: {drivers,mb,soc/intel/braswell}: Add support for Braswell FSP MR2
by Frans Hendriks (Code Review) April 1, 2019

April 1, 2019

Hello Patrick Rudolph, Aaron Durbin, Nathaniel L Desimone, David Guckian, Subrata Banik, Matt DeVillier, build bot (Jenkins), Hannah Williams, Martin Roth, Patrick Georgi, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29661 to look at the new patch set (#8). Change subject: {drivers,mb,soc/intel/braswell}: Add support for Braswell FSP MR2 ...................................................................... {drivers,mb,soc/intel/braswell}: Add support for Braswell FSP MR2 In soc_silicon_init_params() and soc_display_silicon_init_params() SILICON_INIT_UPD element are used which do not exist in MR2. Modify these functions using MR2 elements only. Configuration of 'pre-MR2' elements is placed in mainboard code to be backwards compatible. BUG=NA TEST=Portwell PQ7-M107 Change-Id: Id40b5d46ddda93845d9739b56aaf7ad24ee89246 Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/drivers/intel/fsp1_1/Makefile.inc M src/mainboard/google/cyan/Makefile.inc A src/mainboard/google/cyan/ramstage.c M src/mainboard/intel/strago/ramstage.c M src/soc/intel/braswell/Makefile.inc M src/soc/intel/braswell/chip.c 6 files changed, 98 insertions(+), 33 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/29661/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/29661 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id40b5d46ddda93845d9739b56aaf7ad24ee89246 Gerrit-Change-Number: 29661 Gerrit-PatchSet: 8 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Guckian Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: mb/google/fizz/variants/karma: Clear GPP_B4 when entering S5
by David Wu (Code Review) April 1, 2019

April 1, 2019

Hello Zhuohao Lee, Stefan Reinauer, build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29796 to look at the new patch set (#2). Change subject: mb/google/fizz/variants/karma: Clear GPP_B4 when entering S5 ...................................................................... mb/google/fizz/variants/karma: Clear GPP_B4 when entering S5 Set GPP_B4 to low in S5 to meet touch panel power sequence BUG=b:124197348 BRANCH=master TEST=Verify GPP_B4 is low. Change-Id: I65deb33a45fdc0c0ce64deaa29c2790029dc1d12 Signed-off-by: David Wu <David_Wu(a)quanta.corp-partner.google.com> --- M src/mainboard/google/fizz/smihandler.c M src/mainboard/google/fizz/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/fizz/variants/karma/Makefile.inc A src/mainboard/google/fizz/variants/karma/smihandler.c 4 files changed, 36 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/29796/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29796 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I65deb33a45fdc0c0ce64deaa29c2790029dc1d12 Gerrit-Change-Number: 29796 Gerrit-PatchSet: 2 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: drivers/intel/fsp2_0: Use same stack with coreboot
by Subrata Banik (Code Review) April 1, 2019

April 1, 2019

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32079 ) Change subject: drivers/intel/fsp2_0: Use same stack with coreboot ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/#/c/32079/3//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/32079/3//COMMIT_MSG@9 PS3, Line 9: This patch ensures to have same stack base for FSP and coreboot. : : Feature added in FSP2.1 : - Remove stack swapping from FSP. : - Stack will be shared between coreboot and FSP. > Isn't this CL actually correcting the stack base pointer passed into FSP rather than enabling the fe […] that was the actual intention at that time but if you calculate stack usage in CB:28358 then you will realize it was using still using dedicated stack for cb and fsp. unless we point the same stack base, it can't make use of same stack. hence i have given commit title as "make use of same stack" and in description given the correct expectation from this CL -- To view, visit https://review.coreboot.org/c/coreboot/+/32079 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I673b4216d991d8ccad725c3931006a694184106c Gerrit-Change-Number: 32079 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 01 Apr 2019 02:10:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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