coreboot-gerrit April 2019

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Change in ...coreboot[master]: [WIP] mb/google/sarien: disable ISH UART
by Bora Guvendik (Code Review) 05 Apr '19

05 Apr '19

Bora Guvendik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32187 Change subject: [WIP] mb/google/sarien: disable ISH UART ...................................................................... [WIP] mb/google/sarien: disable ISH UART Disable unused GPIO for logging to save power number. BUG=none TEST=Boot to OS Change-Id: Icc7ff9e67380884cd3865f2864b9ec5faa86670c Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com> --- M src/mainboard/google/sarien/variants/arcada/gpio.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/32187/1 diff --git a/src/mainboard/google/sarien/variants/arcada/gpio.c b/src/mainboard/google/sarien/variants/arcada/gpio.c index 1b06301..8f950cb 100644 --- a/src/mainboard/google/sarien/variants/arcada/gpio.c +++ b/src/mainboard/google/sarien/variants/arcada/gpio.c @@ -123,9 +123,9 @@ /* ISH_SPI_MISO */ PAD_CFG_GPI(GPP_D11, NONE, DEEP), /* TBT_DET# */ /* ISH_SPI_MOSI */ PAD_NC(GPP_D12, NONE), /* ISH_CPU_UART0_RX */ -/* ISH_UART0_RXD */ PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1), +/* ISH_UART0_RXD */ PAD_NC(GPP_D13, NONE), /* ISH_CPU_UART0_TX */ -/* ISH_UART0_TXD */ PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1), +/* ISH_UART0_TXD */ PAD_NC(GPP_D14, NONE), /* ISH_UART0_RTS# */ PAD_CFG_GPO(GPP_D15, 1, DEEP), /* WWAN_FULL_PWR_EN */ /* ISH_UART0_CTS# */ PAD_NC(GPP_D16, NONE), /* DMIC_CLK1 */ PAD_CFG_GPI(GPP_D17, NONE, DEEP), /* KB_DET# */ -- To view, visit https://review.coreboot.org/c/coreboot/+/32187 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icc7ff9e67380884cd3865f2864b9ec5faa86670c Gerrit-Change-Number: 32187 Gerrit-PatchSet: 1 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/hatch: Move I2C/SPI options to override tree
by Furquan Shaikh (Code Review) 04 Apr '19

04 Apr '19

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32138 Change subject: mb/google/hatch: Move I2C/SPI options to override tree ...................................................................... mb/google/hatch: Move I2C/SPI options to override tree This change moves the I2C/SPI devices and configs which do not apply to all variants to override tree. Currently, there are just two variants. However, as we prepare to add more variants, these devices need to be moved out of the base devicetree. BUG=b:129728235 TEST=Verified that I2C/SPI devices are present in static.c for hatch and hatch_whl. Change-Id: I9426f6bf5f8514de5f1889e22e57105749fd92de Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/mainboard/google/hatch/Kconfig M src/mainboard/google/hatch/variants/baseboard/devicetree.cb M src/mainboard/google/hatch/variants/hatch/overridetree.cb A src/mainboard/google/hatch/variants/hatch_whl/overridetree.cb 4 files changed, 256 insertions(+), 121 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/32138/1 diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index b551065..4e4e00a 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -83,7 +83,7 @@ config OVERRIDE_DEVICETREE string - default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb" if !BOARD_GOOGLE_HATCH_WHL + default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb" config TPM_TIS_ACPI_INTERRUPT int diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index 984852f..b2b7183 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -17,35 +17,6 @@ # EC memory map range is 0x900-0x9ff register "gen3_dec" = "0x00fc0901" - # Intel Common SoC Config - #+-------------------+---------------------------+ - #| Field | Value | - #+-------------------+---------------------------+ - #| GSPI0 | cr50 TPM. Early init is | - #| | required to set up a BAR | - #| | for TPM communication | - #| | before memory is up | - #| GSPI1 | FP MCU | - #| I2C0 | Touchpad | - #| I2C1 | Touch screen | - #| I2C4 | Audio | - #+-------------------+---------------------------+ - register "common_soc_config" = "{ - .gspi[0] = { - .speed_mhz = 1, - .early_init = 1, - }, - .i2c[0] = { - .speed = I2C_SPEED_FAST, - }, - .i2c[1] = { - .speed = I2C_SPEED_FAST, - }, - .i2c[4] = { - .speed = I2C_SPEED_FAST, - }, - }" - # FSP configuration register "InternalGfx" = "1" register "SkipExtGfxScan" = "1" @@ -215,73 +186,10 @@ device pci 14.3 on end # CNVi wifi end device pci 14.5 on end # SDCard - device pci 15.0 on - chip drivers/i2c/generic - register "hid" = ""ELAN0000"" - register "desc" = ""ELAN Touchpad"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D21_IRQ)" - register "wake" = "GPE0_DW0_21" - device i2c 15 on end - end - end # I2C #0 - device pci 15.1 on - chip drivers/i2c/generic - register "hid" = ""ELAN0001"" - register "desc" = ""ELAN Touchscreen"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" - register "probed" = "1" - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" - register "reset_delay_ms" = "100" - register "reset_off_delay_ms" = "5" - register "has_power_resource" = "1" - register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C4)" - register "stop_off_delay_ms" = "5" - device i2c 49 on end - end - end # I2C #1 - device pci 15.2 on - chip drivers/generic/gpio_keys - register "name" = ""PENH"" - register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_HIGH(GPP_A8)" - register "key.dev_name" = ""EJCT"" - register "key.linux_code" = "SW_PEN_INSERTED" - register "key.linux_input_type" = "EV_SW" - register "key.label" = ""pen_eject"" - device generic 0 on end - end - end # I2C #2 - device pci 15.3 on - chip drivers/i2c/sx9310 - register "desc" = ""SAR Proximity Sensor"" - register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_A0_IRQ)" - register "speed" = "I2C_SPEED_FAST" - register "uid" = "1" - register "reg_prox_ctrl0" = "0x10" - register "reg_prox_ctrl1" = "0x00" - register "reg_prox_ctrl2" = "0x84" - register "reg_prox_ctrl3" = "0x0e" - register "reg_prox_ctrl4" = "0x07" - register "reg_prox_ctrl5" = "0xc6" - register "reg_prox_ctrl6" = "0x20" - register "reg_prox_ctrl7" = "0x0d" - register "reg_prox_ctrl8" = "0x8d" - register "reg_prox_ctrl9" = "0x43" - register "reg_prox_ctrl10" = "0x1f" - register "reg_prox_ctrl11" = "0x00" - register "reg_prox_ctrl12" = "0x00" - register "reg_prox_ctrl13" = "0x00" - register "reg_prox_ctrl14" = "0x00" - register "reg_prox_ctrl15" = "0x00" - register "reg_prox_ctrl16" = "0x00" - register "reg_prox_ctrl17" = "0x00" - register "reg_prox_ctrl18" = "0x00" - register "reg_prox_ctrl19" = "0x00" - register "reg_sar_ctrl0" = "0x50" - register "reg_sar_ctrl1" = "0x8a" - register "reg_sar_ctrl2" = "0x3c" - device i2c 28 on end - end - end # I2C #3 + device pci 15.0 on end # I2C #0 + device pci 15.1 on end # I2C #1 + device pci 15.2 on end # I2C #2 + device pci 15.3 on end # I2C #3 device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R @@ -289,20 +197,7 @@ device pci 16.4 off end # Management Engine Interface 3 device pci 16.5 off end # Management Engine Interface 4 device pci 17.0 on end # SATA - device pci 19.0 on - chip drivers/i2c/generic - register "hid" = ""10EC5682"" - register "name" = ""RT58"" - register "desc" = ""Realtek RT5682"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_H0_IRQ)" - register "property_count" = "1" - # Set the jd_src to RT5668_JD1 for jack detection - register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" - register "property_list[0].name" = ""realtek,jd-src"" - register "property_list[0].integer" = "1" - device i2c 1a on end - end - end #I2C #4 + device pci 19.0 on end #I2C #4 device pci 19.1 off end # I2C #5 device pci 19.2 off end # UART #2 device pci 1a.0 off end # eMMC @@ -335,16 +230,7 @@ device spi 0 on end end end # GSPI #0 - device pci 1e.3 on - chip drivers/spi/acpi - register "name" = ""CRFP"" - register "hid" = "ACPI_DT_NAMESPACE_HID" - register "uid" = "1" - register "compat_string" = ""google,cros-ec-spi"" - register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_A23_IRQ)" - device spi 1 on end - end # FPMCU - end # GSPI #1 + device pci 1e.3 on end # GSPI #1 device pci 1f.0 on chip ec/google/chromeec device pnp 0c09.0 on end diff --git a/src/mainboard/google/hatch/variants/hatch/overridetree.cb b/src/mainboard/google/hatch/variants/hatch/overridetree.cb index 6e6414e..28644d1 100644 --- a/src/mainboard/google/hatch/variants/hatch/overridetree.cb +++ b/src/mainboard/google/hatch/variants/hatch/overridetree.cb @@ -15,4 +15,127 @@ [PchSerialIoIndexUART2] = PchSerialIoDisabled, }" + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| GSPI1 | FP MCU | + #| I2C0 | Touchpad | + #| I2C1 | Touch screen | + #| I2C4 | Audio | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[4] = { + .speed = I2C_SPEED_FAST, + }, + }" + + device domain 0 on + device pci 15.0 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D21_IRQ)" + register "wake" = "GPE0_DW0_21" + device i2c 15 on end + end + end # I2C #0 + device pci 15.1 on + chip drivers/i2c/generic + register "hid" = ""ELAN0001"" + register "desc" = ""ELAN Touchscreen"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" + register "probed" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" + register "reset_delay_ms" = "100" + register "reset_off_delay_ms" = "5" + register "has_power_resource" = "1" + register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C4)" + register "stop_off_delay_ms" = "5" + device i2c 49 on end + end + end # I2C #1 + device pci 15.2 on + chip drivers/generic/gpio_keys + register "name" = ""PENH"" + register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_HIGH(GPP_A8)" + register "key.dev_name" = ""EJCT"" + register "key.linux_code" = "SW_PEN_INSERTED" + register "key.linux_input_type" = "EV_SW" + register "key.label" = ""pen_eject"" + device generic 0 on end + end + end # I2C #2 + device pci 15.3 on + chip drivers/i2c/sx9310 + register "desc" = ""SAR Proximity Sensor"" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_A0_IRQ)" + register "speed" = "I2C_SPEED_FAST" + register "uid" = "1" + register "reg_prox_ctrl0" = "0x10" + register "reg_prox_ctrl1" = "0x00" + register "reg_prox_ctrl2" = "0x84" + register "reg_prox_ctrl3" = "0x0e" + register "reg_prox_ctrl4" = "0x07" + register "reg_prox_ctrl5" = "0xc6" + register "reg_prox_ctrl6" = "0x20" + register "reg_prox_ctrl7" = "0x0d" + register "reg_prox_ctrl8" = "0x8d" + register "reg_prox_ctrl9" = "0x43" + register "reg_prox_ctrl10" = "0x1f" + register "reg_prox_ctrl11" = "0x00" + register "reg_prox_ctrl12" = "0x00" + register "reg_prox_ctrl13" = "0x00" + register "reg_prox_ctrl14" = "0x00" + register "reg_prox_ctrl15" = "0x00" + register "reg_prox_ctrl16" = "0x00" + register "reg_prox_ctrl17" = "0x00" + register "reg_prox_ctrl18" = "0x00" + register "reg_prox_ctrl19" = "0x00" + register "reg_sar_ctrl0" = "0x50" + register "reg_sar_ctrl1" = "0x8a" + register "reg_sar_ctrl2" = "0x3c" + device i2c 28 on end + end + end # I2C #3 + device pci 19.0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Realtek RT5682"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_H0_IRQ)" + register "property_count" = "1" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + end #I2C #4 + device pci 1e.3 on + chip drivers/spi/acpi + register "name" = ""CRFP"" + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "uid" = "1" + register "compat_string" = ""google,cros-ec-spi"" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_A23_IRQ)" + device spi 1 on end + end # FPMCU + end # GSPI #1 + end + end diff --git a/src/mainboard/google/hatch/variants/hatch_whl/overridetree.cb b/src/mainboard/google/hatch/variants/hatch_whl/overridetree.cb new file mode 100644 index 0000000..9b772c2 --- /dev/null +++ b/src/mainboard/google/hatch/variants/hatch_whl/overridetree.cb @@ -0,0 +1,126 @@ +chip soc/intel/cannonlake + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| GSPI1 | FP MCU | + #| I2C0 | Touchpad | + #| I2C1 | Touch screen | + #| I2C4 | Audio | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[4] = { + .speed = I2C_SPEED_FAST, + }, + }" + + device domain 0 on + device pci 15.0 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D21_IRQ)" + register "wake" = "GPE0_DW0_21" + device i2c 15 on end + end + end # I2C #0 + device pci 15.1 on + chip drivers/i2c/generic + register "hid" = ""ELAN0001"" + register "desc" = ""ELAN Touchscreen"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" + register "probed" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" + register "reset_delay_ms" = "100" + register "reset_off_delay_ms" = "5" + register "has_power_resource" = "1" + register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C4)" + register "stop_off_delay_ms" = "5" + device i2c 49 on end + end + end # I2C #1 + device pci 15.2 on + chip drivers/generic/gpio_keys + register "name" = ""PENH"" + register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_HIGH(GPP_A8)" + register "key.dev_name" = ""EJCT"" + register "key.linux_code" = "SW_PEN_INSERTED" + register "key.linux_input_type" = "EV_SW" + register "key.label" = ""pen_eject"" + device generic 0 on end + end + end # I2C #2 + device pci 15.3 on + chip drivers/i2c/sx9310 + register "desc" = ""SAR Proximity Sensor"" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_A0_IRQ)" + register "speed" = "I2C_SPEED_FAST" + register "uid" = "1" + register "reg_prox_ctrl0" = "0x10" + register "reg_prox_ctrl1" = "0x00" + register "reg_prox_ctrl2" = "0x84" + register "reg_prox_ctrl3" = "0x0e" + register "reg_prox_ctrl4" = "0x07" + register "reg_prox_ctrl5" = "0xc6" + register "reg_prox_ctrl6" = "0x20" + register "reg_prox_ctrl7" = "0x0d" + register "reg_prox_ctrl8" = "0x8d" + register "reg_prox_ctrl9" = "0x43" + register "reg_prox_ctrl10" = "0x1f" + register "reg_prox_ctrl11" = "0x00" + register "reg_prox_ctrl12" = "0x00" + register "reg_prox_ctrl13" = "0x00" + register "reg_prox_ctrl14" = "0x00" + register "reg_prox_ctrl15" = "0x00" + register "reg_prox_ctrl16" = "0x00" + register "reg_prox_ctrl17" = "0x00" + register "reg_prox_ctrl18" = "0x00" + register "reg_prox_ctrl19" = "0x00" + register "reg_sar_ctrl0" = "0x50" + register "reg_sar_ctrl1" = "0x8a" + register "reg_sar_ctrl2" = "0x3c" + device i2c 28 on end + end + end # I2C #3 + device pci 19.0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Realtek RT5682"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_H0_IRQ)" + register "property_count" = "1" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + end #I2C #4 + device pci 1e.3 on + chip drivers/spi/acpi + register "name" = ""CRFP"" + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "uid" = "1" + register "compat_string" = ""google,cros-ec-spi"" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_A23_IRQ)" + device spi 1 on end + end # FPMCU + end # GSPI #1 + end + +end -- To view, visit https://review.coreboot.org/c/coreboot/+/32138 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9426f6bf5f8514de5f1889e22e57105749fd92de Gerrit-Change-Number: 32138 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: src/soc/intel/braswell/acpi/lpss.asl: Remove SPI1 and PWM asl code
by Matt DeVillier (Code Review) 04 Apr '19

04 Apr '19

Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29417 ) Change subject: src/soc/intel/braswell/acpi/lpss.asl: Remove SPI1 and PWM asl code ...................................................................... Patch Set 3: > Matt, could You please share Your opinion and possibly review the patch? I'm not aware of these devices being used on any BSW Chromebook, but I can test the patch to be sure of no adverse reaction. Even though disabled by default, I'd only remove if we're sure that no BSW devices at all use these, otherwise may find ourselves reviewing a patch to add the code back and hook up the related UPD -- To view, visit https://review.coreboot.org/c/coreboot/+/29417 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iec2ca7520081d00bf7a53d58ee054aa6f23e5606 Gerrit-Change-Number: 29417 Gerrit-PatchSet: 3 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Thu, 04 Apr 2019 15:47:58 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: util/docker: work around toolchain autotools issue
by Martin Roth (Code Review) 04 Apr '19

04 Apr '19

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/28544 ) Change subject: util/docker: work around toolchain autotools issue ...................................................................... util/docker: work around toolchain autotools issue The patches added to `make` require that we use automake & aclocal to rebuild the configuration, but version 1.15 of autotools is expected. After debian sid updated to autotools 1.16, the tools can't be located. We'll just pretend to have version 1.15 with symbolic links. This doesn't seem to be a good solution but gets the job done. Change-Id: I9f616b96e728106e7adf321325caa06808e064c2 Signed-off-by: Martin Roth <martinr(a)coreboot.org> Signed-off-by: Nico Huber <nico.h(a)gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/28544 Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M util/docker/coreboot-sdk/Dockerfile 1 file changed, 3 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved Nico Huber: Looks good to me, approved Paul Menzel: Looks good to me, but someone else must approve diff --git a/util/docker/coreboot-sdk/Dockerfile b/util/docker/coreboot-sdk/Dockerfile index 739e0d1..3f39627 100644 --- a/util/docker/coreboot-sdk/Dockerfile +++ b/util/docker/coreboot-sdk/Dockerfile @@ -69,7 +69,9 @@ wget \ xz-utils \ zlib1g-dev \ - && apt-get clean + && apt-get clean \ + && ln -s /usr/bin/automake /usr/bin/automake-1.15 \ + && ln -s /usr/bin/aclocal /usr/bin/aclocal-1.15 RUN \ cd /root && \ -- To view, visit https://review.coreboot.org/c/coreboot/+/28544 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9f616b96e728106e7adf321325caa06808e064c2 Gerrit-Change-Number: 28544 Gerrit-PatchSet: 4 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: util/docker: work around toolchain autotools issue
by Martin Roth (Code Review) 04 Apr '19

04 Apr '19

Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/28544 ) Change subject: util/docker: work around toolchain autotools issue ...................................................................... Patch Set 3: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/28544 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9f616b96e728106e7adf321325caa06808e064c2 Gerrit-Change-Number: 28544 Gerrit-PatchSet: 3 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 04 Apr 2019 14:56:18 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: src/soc/intel/braswell/chip.c: Configure LPSS devices in correct mode
by Frans Hendriks (Code Review) 04 Apr '19

04 Apr '19

Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29284 ) Change subject: src/soc/intel/braswell/chip.c: Configure LPSS devices in correct mode ...................................................................... Patch Set 3: > Patch Set 3: > > > Patch Set 3: > > > > > Patch Set 3: > > > > > > is the default PCI mode? (since you're not explicitly setting it) > > > what are the consequences of not passing the correct mode to FSP? > > > > Default can be PCI or ACPI, depending on values devicetree.cb. > > The child devices need to operate ACPI mode when the LPSS is operating in ACPI mode. For this reason the patch is uploaded. > > > > FSP MR2 does a check for ACPI mode and change the device mode. Supplying incorrect configuration will be corrected by FSP, but to be futher proof supply correct configuration to FSP. > > By looking at the BSF file for Braswell FSP, the I2C and other LPSS devices are defined as Enable/Disable switches, so only binary configuration (0 or 1). Does it mean that that Intel did not document the ACPI mode as a 3rd option in the BSF and Integration Guide? In BSF only enable/disable is supported. In FSP code the mode will follow the DMA1Enabled. -- To view, visit https://review.coreboot.org/c/coreboot/+/29284 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie271d8cb9f30f0c0ba538f1530cfb82f1306fea8 Gerrit-Change-Number: 29284 Gerrit-PatchSet: 3 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Thu, 04 Apr 2019 13:52:53 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/google/hatch: Change the DEVSLP reset config to PLTRST
by Rizwan Qureshi (Code Review) 04 Apr '19

04 Apr '19

Rizwan Qureshi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32136 Change subject: mb/google/hatch: Change the DEVSLP reset config to PLTRST ...................................................................... mb/google/hatch: Change the DEVSLP reset config to PLTRST In S3 the PCH is driving the DEVSLP signal low, assuming that the SATA device is already powered off. However on hatch the SATA power is still enabled. And since DEVSLP is low, this causes the SATA device to not enter low power state. The fix here is to set the pad cofnig to be reset on PLTRST assertion which will cause the pin to be high impedance state anf will be pulled up by the SATA device. BUG=b:126611255 BRANCH=None TEST=Make sure that S3 and S0ix is working fine on hatch. And also make sure that DEVSLP is pulled high in S3. Change-Id: Ifb6a71a72244522c8dd8d48e9b9f8dc6feef8981 Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- M src/mainboard/google/hatch/variants/baseboard/gpio.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/32136/1 diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c index b974e49..2912875 100644 --- a/src/mainboard/google/hatch/variants/baseboard/gpio.c +++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c @@ -241,7 +241,7 @@ /* E4 : M2_SSD_PE_WAKE_ODL */ PAD_CFG_GPI(GPP_E4, NONE, DEEP), /* E5 : SATA_DEVSLP1 */ - PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E5, NONE, PLTRST, NF1), /* E6 : M2_SSD_RST_L */ PAD_NC(GPP_E6, NONE), /* E7 : GPP_E7 ==> NC */ -- To view, visit https://review.coreboot.org/c/coreboot/+/32136 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifb6a71a72244522c8dd8d48e9b9f8dc6feef8981 Gerrit-Change-Number: 32136 Gerrit-PatchSet: 1 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: siemens/mc_apl4: provide CLK on Pin PMU_SUSCLK SMARC module
by Uwe Poeche (Code Review) 04 Apr '19

04 Apr '19

Uwe Poeche has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32168 Change subject: siemens/mc_apl4: provide CLK on Pin PMU_SUSCLK SMARC module ...................................................................... siemens/mc_apl4: provide CLK on Pin PMU_SUSCLK SMARC module This patch provides an clock on Pin PMU_SUSCLK. This is necessary for correct function of the SMARC module. Test=mc_apl4 flashed, booted into Linux, ckecked CLK with scope Change-Id: Ieb1d66b5a09363c9bed2b19e7a204f206ee04158 Signed-off-by: Uwe Poeche <uwe.poeche(a)siemens.com> --- M src/mainboard/siemens/mc_apl1/variants/mc_apl4/gpio.c 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/32168/1 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/gpio.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/gpio.c index 40b2c93..2bd56b8 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/gpio.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/gpio.c @@ -131,7 +131,6 @@ PAD_CFG_GPI(PMU_SLP_S0_B, UP_20K, DEEP), PAD_CFG_GPI(PMU_SLP_S3_B, UP_20K, DEEP), PAD_CFG_GPI(PMU_SLP_S4_B, UP_20K, DEEP), - PAD_CFG_GPI(PMU_SUSCLK, DN_20K, DEEP), PAD_CFG_GPI(PMU_WAKE_B, DN_20K, DEEP), PAD_CFG_GPI(SUS_STAT_B, DN_20K, DEEP), PAD_CFG_GPI(SUSPWRDNACK, DN_20K, DEEP), @@ -380,6 +379,8 @@ PAD_CFG_NF(GPIO_43, UP_20K, DEEP, NF1), /* LPSS_UART1_TXD */ PAD_CFG_NF(GPIO_46, UP_20K, DEEP, NF1), /* LPSS_UART2_RXD */ PAD_CFG_NF(GPIO_47, UP_20K, DEEP, NF1), /* LPSS_UART2_TXD */ + + PAD_CFG_NF(PMU_SUSCLK, NONE, DEEP, NF1),/* 32,78 kHz used on SMARC */ }; const struct pad_config *variant_early_gpio_table(size_t *num) -- To view, visit https://review.coreboot.org/c/coreboot/+/32168 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieb1d66b5a09363c9bed2b19e7a204f206ee04158 Gerrit-Change-Number: 32168 Gerrit-PatchSet: 1 Gerrit-Owner: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/fizz/variants/karma: Clear GPP_B4 when entering S5
by Patrick Georgi (Code Review) 04 Apr '19

04 Apr '19

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/29796 ) Change subject: mb/google/fizz/variants/karma: Clear GPP_B4 when entering S5 ...................................................................... mb/google/fizz/variants/karma: Clear GPP_B4 when entering S5 Set GPP_B4 to low in S5 to meet touch panel power sequence BUG=b:124197348 BRANCH=master TEST=Verify GPP_B4 is low. Change-Id: I65deb33a45fdc0c0ce64deaa29c2790029dc1d12 Signed-off-by: David Wu <David_Wu(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29796 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao(a)chromium.org> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> Reviewed-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan(a)google.com> --- M src/mainboard/google/fizz/smihandler.c M src/mainboard/google/fizz/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/fizz/variants/karma/Makefile.inc A src/mainboard/google/fizz/variants/karma/smihandler.c 4 files changed, 36 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, but someone else must approve Furquan Shaikh: Looks good to me, approved David Wu: Looks good to me, but someone else must approve Zhuohao Lee: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/fizz/smihandler.c b/src/mainboard/google/fizz/smihandler.c index 3aa9ddb..2b7367a 100644 --- a/src/mainboard/google/fizz/smihandler.c +++ b/src/mainboard/google/fizz/smihandler.c @@ -17,6 +17,7 @@ #include <ec/google/chromeec/smm.h> #include <soc/smm.h> +#include <baseboard/variants.h> #include <variant/ec.h> void mainboard_smi_espi_handler(void) @@ -24,8 +25,11 @@ chromeec_smi_process_events(); } +void __weak variant_smi_sleep(u8 slp_typ) {} + void mainboard_smi_sleep(u8 slp_typ) { + variant_smi_sleep(slp_typ); chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS, MAINBOARD_EC_S5_WAKE_EVENTS); } diff --git a/src/mainboard/google/fizz/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/fizz/variants/baseboard/include/baseboard/variants.h index 50e7ee3..40dfeeb 100644 --- a/src/mainboard/google/fizz/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/fizz/variants/baseboard/include/baseboard/variants.h @@ -29,6 +29,8 @@ const struct cros_gpio *variant_cros_gpios(size_t *num); +void variant_smi_sleep(u8 slp_typ); + struct nhlt; void variant_nhlt_init(struct nhlt *nhlt); void variant_nhlt_oem_overrides(const char **oem_id, const char **oem_table_id, diff --git a/src/mainboard/google/fizz/variants/karma/Makefile.inc b/src/mainboard/google/fizz/variants/karma/Makefile.inc index 0ad298b..7475522 100644 --- a/src/mainboard/google/fizz/variants/karma/Makefile.inc +++ b/src/mainboard/google/fizz/variants/karma/Makefile.inc @@ -2,3 +2,5 @@ ramstage-y += gpio.c ramstage-y += nhlt.c + +smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c diff --git a/src/mainboard/google/fizz/variants/karma/smihandler.c b/src/mainboard/google/fizz/variants/karma/smihandler.c new file mode 100644 index 0000000..1bfae4d --- /dev/null +++ b/src/mainboard/google/fizz/variants/karma/smihandler.c @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +#include <baseboard/variants.h> +#include <gpio.h> + +#define TS_ENABLE GPP_B4 + +void variant_smi_sleep(u8 slp_typ) +{ + if (slp_typ == ACPI_S5) { + /* Set TS to disable */ + gpio_set(TS_ENABLE, 0); + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/29796 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I65deb33a45fdc0c0ce64deaa29c2790029dc1d12 Gerrit-Change-Number: 29796 Gerrit-PatchSet: 3 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in ...coreboot[master]: soc/intel/braswell: Correct serial IRQ support
by Patrick Georgi (Code Review) 04 Apr '19

04 Apr '19

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/29398 ) Change subject: soc/intel/braswell: Correct serial IRQ support ...................................................................... soc/intel/braswell: Correct serial IRQ support Serial IRQ was configured in quiet mode, but not enabled. Enable serial IRQ and use 'enum seriirq_mode' as a devicetree option. Function sc_enable_serial_irqs() is added to enabled serial IRQs. enable_serirq_quiet_mode() is renamed to sc_set_serial_irqs_mode(). This function use the 'serirq_mode' to set the mode. The call to this function is moved from finalize to init having serial IRQs enable in early stage. Serial IRQs must be enabled in continuous mode for at least one frame before switching into quiet mode. BUG=N/A TEST=Portwell PQ7-M107 Change-Id: I7844cad69dc0563fa6109d779d0afb7c2edd7245 Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29398 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> --- M src/soc/intel/braswell/chip.h M src/soc/intel/braswell/include/soc/lpc.h M src/soc/intel/braswell/southcluster.c 3 files changed, 38 insertions(+), 10 deletions(-) Approvals: build bot (Jenkins): Verified Michał Żygowski: Looks good to me, approved diff --git a/src/soc/intel/braswell/chip.h b/src/soc/intel/braswell/chip.h index 9fde4d1..4afaf44 100644 --- a/src/soc/intel/braswell/chip.h +++ b/src/soc/intel/braswell/chip.h @@ -3,6 +3,7 @@ * * Copyright (C) 2013 Google Inc. * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2019 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -24,6 +25,7 @@ #include <stdint.h> #include <fsp/util.h> +#include <intelblocks/lpc_lib.h> #include <soc/pci_devs.h> #define SVID_CONFIG1 1 @@ -54,6 +56,8 @@ uint8_t enable_xdp_tap; uint8_t clkreq_enable; + enum serirq_mode serirq_mode; + /* Disable SLP_X stretching after SUS power well loss. */ int disable_slp_x_stretch_sus_fail; diff --git a/src/soc/intel/braswell/include/soc/lpc.h b/src/soc/intel/braswell/include/soc/lpc.h index 7b1e3424..1a56f9e 100644 --- a/src/soc/intel/braswell/include/soc/lpc.h +++ b/src/soc/intel/braswell/include/soc/lpc.h @@ -31,6 +31,10 @@ #define UART_CONT 0x80 #define RCBA 0xf0 +/* iLB Memory Mapped IO */ +#define ILB_OIC 0x60 +#define SIRQEN (1 << 12) + /* Memory Mapped IO in LPC bridge */ #define SCNT 0x10 #define SCNT_MODE (1 << 7) /* When cleared, SERIRQ is in quiet mode */ diff --git a/src/soc/intel/braswell/southcluster.c b/src/soc/intel/braswell/southcluster.c index e79cb12..000790d 100644 --- a/src/soc/intel/braswell/southcluster.c +++ b/src/soc/intel/braswell/southcluster.c @@ -28,6 +28,7 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> +#include <intelblocks/lpc_lib.h> #include <pc80/isa-dma.h> #include <pc80/i8254.h> #include <pc80/i8259.h> @@ -41,17 +42,23 @@ #include <soc/spi.h> #include <spi-generic.h> #include <stdint.h> -#include <reg_script.h> -static const struct reg_script ops[] = { - REG_MMIO_RMW32(ILB_BASE_ADDRESS + SCNT, - ~SCNT_MODE, 0), /* put LPC SERIRQ in Quiet Mode */ - REG_SCRIPT_END -}; - -static void enable_serirq_quiet_mode(void) +static void sc_set_serial_irqs_mode(struct device *dev, enum serirq_mode mode) { - reg_script_run(ops); + u8 *ilb_base = (u8 *)(pci_read_config32(dev, IBASE) & ~0xF); + + switch (mode) { + case SERIRQ_CONTINUOUS: + break; + case SERIRQ_OFF: + write32(ilb_base + ILB_OIC, read32(ilb_base + ILB_OIC) & + ~SIRQEN); + break; + case SERIRQ_QUIET: + default: + write8(ilb_base + SCNT, read8(ilb_base + SCNT) & ~SCNT_MODE); + break; + } } static inline void @@ -85,6 +92,15 @@ #define LPC_DEFAULT_IO_RANGE_LOWER 0 #define LPC_DEFAULT_IO_RANGE_UPPER 0x1000 +static void sc_enable_serial_irqs(struct device *dev) +{ + u8 *ilb_base = (u8 *)(pci_read_config32(dev, IBASE) & ~0xF); + + printk(BIOS_SPEW, "Enable serial irq\n"); + write32(ilb_base + ILB_OIC, read32(ilb_base + ILB_OIC) | SIRQEN); + write8(ilb_base + SCNT, read8(ilb_base + SCNT) | SCNT_MODE); +} + /* * Write PCI config space IRQ assignments. PCI devices have the INT_LINE * (0x3C) and INT_PIN (0x3D) registers which report interrupt routing @@ -285,6 +301,8 @@ isa_dma_init(); + sc_enable_serial_irqs(dev); + /* Set up the PIRQ PIC routing based on static config. */ for (i = 0; i < NUM_PIRQS; i++) write8((void *)(pr_base + i*sizeof(ir->pic[i])), @@ -320,6 +338,9 @@ /* Initialize i8254 timers */ setup_i8254(); + + sc_set_serial_irqs_mode(dev, config->serirq_mode); + } /* @@ -630,7 +651,6 @@ write32(spi + LVSCC, cfg.lvscc | VCL); } spi_init(); - enable_serirq_quiet_mode(); printk(BIOS_DEBUG, "Finalizing SMM.\n"); outb(APM_CNT_FINALIZE, APM_CNT); -- To view, visit https://review.coreboot.org/c/coreboot/+/29398 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7844cad69dc0563fa6109d779d0afb7c2edd7245 Gerrit-Change-Number: 29398 Gerrit-PatchSet: 13 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: merged

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