coreboot-gerrit April 2019

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Change in ...coreboot[master]: [WIP] Nvidia Optimus support for ThinkPads
by Patrick Rudolph (Code Review) 06 Apr '19

06 Apr '19

Patrick Rudolph has uploaded a new patch set (#11) to the change originally created by Evgeny Zinoviev. ( https://review.coreboot.org/c/coreboot/+/28380 ) Change subject: [WIP] Nvidia Optimus support for ThinkPads ...................................................................... [WIP] Nvidia Optimus support for ThinkPads Based on siro's work #23041. Adds ACPI code for dGPU power management using the dGPU kernel module. With Nvidia Optimus active the idle power consumption drops from 22,8W to 13,8W with maximum screen brightness. Depends on: https://review.coreboot.org/#/c/coreboot/+/28392 https://review.coreboot.org/#/c/coreboot/+/28393 What works (tested on 4.16.13-gentoo kernel): - power management via _PS0 and _DSM + _PS3 ACPI calls - nouveau driver - bumblebee (from the "develop" branch) - bbswitch lspci turns on the dGPU, but that is expected, as otherwise it can't access the device's address space. The Nvidia Optimus driver needs to be enabled by setting CONFIG_NVIDIA_OPTIMUS=y Tested on ThinkPad W530 and Thinkpad T520. Known problems: - nvidia driver doens't work: [ 275.244113] NVRM: failed to copy vbios to system memory. [ 275.244345] NVRM: RmInitAdapter failed! (0x30:0xffff:663) [ 275.244433] NVRM: rm_init_adapter failed for device bearing minor number 0 [ 275.347956] NVRM: failed to copy vbios to system memory. [ 275.348140] NVRM: RmInitAdapter failed! (0x30:0xffff:663) [ 275.348163] NVRM: rm_init_adapter failed for device bearing minor number 0 - Random CPU core lockups TODO: - Disable PEG clock to decrease idle power by 1W. - Do longterm stability tests. - Document _DSM and code. Change-Id: I277808d6c1d8bd6e0a267a53f25471597698f8d5 Signed-off-by: Evgeny Zinoviev <me(a)ch1p.com> Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- A src/drivers/nvidia/optimus/Kconfig A src/drivers/nvidia/optimus/acpi/optimus.asl A src/ec/lenovo/pmh7/acpi/optimus_sandy_ivy.asl A src/ec/lenovo/pmh7/acpi/pmh7.asl M src/ec/lenovo/pmh7/pmh7.h M src/mainboard/lenovo/t420/Kconfig M src/mainboard/lenovo/t420/acpi/ec.asl M src/mainboard/lenovo/t420s/Kconfig M src/mainboard/lenovo/t420s/acpi/ec.asl M src/mainboard/lenovo/t430/Kconfig M src/mainboard/lenovo/t430/acpi/ec.asl M src/mainboard/lenovo/t430s/Kconfig M src/mainboard/lenovo/t430s/acpi/ec.asl M src/mainboard/lenovo/t520/Kconfig M src/mainboard/lenovo/t520/acpi/ec.asl M src/mainboard/lenovo/t520/cmos.default M src/mainboard/lenovo/t530/Kconfig M src/mainboard/lenovo/t530/acpi/ec.asl M src/northbridge/intel/sandybridge/acpi/hostbridge.asl M src/northbridge/intel/sandybridge/acpi/peg.asl 20 files changed, 672 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/28380/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/28380 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I277808d6c1d8bd6e0a267a53f25471597698f8d5 Gerrit-Change-Number: 28380 Gerrit-PatchSet: 11 Gerrit-Owner: Evgeny Zinoviev <me(a)ch1p.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Name of user not set #1002090 Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: mb/asrock/h110m: Add PEG Gen3 support
by Maxim Polyakov (Code Review) 06 Apr '19

06 Apr '19

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31948 Change subject: mb/asrock/h110m: Add PEG Gen3 support ...................................................................... mb/asrock/h110m: Add PEG Gen3 support This patch adds support PCIe Gen 3 with 8GT/s link speed for PEG x16 slot. All parameters for FSP are set during initialization in romstage. Now there is no need to additionally configure the FSP before building the ROM image. Tested on Intel Core i5-6600 processor with the following devices: - LP11000e Fibre Channel HBA (Gen2 x8); - PEX8734 PCIe Fabric/Switch (Gen3 x16); - NVIDIA GeForce GTX 1060 GPU (Gen3 x16). GPU works with an nouveau and proprietary driver under Ubuntu 18.04.2 (4.15.0-46-generic GNU/Linux kernel). Discrete graphic card is used as primary device for display output (if CONFIG_ONBOARD_VGA_IS_PRIMARY is not set). Dynamic switching is not yet supported. Tianocore (edk2-stable201811-216-g51be9d0) is used as the payload. Change-Id: Ia4f29df47d76de5069fe53120434cc7c2ab6f044 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/mainboard/asrock/h110m/devicetree.cb M src/mainboard/asrock/h110m/romstage.c 2 files changed, 27 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/31948/1 diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb index 9e2fca0..78e99f3 100644 --- a/src/mainboard/asrock/h110m/devicetree.cb +++ b/src/mainboard/asrock/h110m/devicetree.cb @@ -201,6 +201,13 @@ [PchSerialIoIndexUart2] = PchSerialIoDisabled, \ }" + # Use SRCCLKREQ0# and CLKSRC0 for PEG x16 root port + register "PcieRpClkReqSupport[0]" = "1" + register "PcieRpClkReqNumber[0]" = "0" + # Enable Latency Tolerance Reporting Mechanism + register "PcieRpLtrEnable[0]" = "1" + register "PcieRpClkSrcNumber[0]" = "0" + # Enable Root port 6(x1) for LAN. register "PcieRpEnable[5]" = "1" # Enable CLKREQ# diff --git a/src/mainboard/asrock/h110m/romstage.c b/src/mainboard/asrock/h110m/romstage.c index 4961a79..dacf47b 100644 --- a/src/mainboard/asrock/h110m/romstage.c +++ b/src/mainboard/asrock/h110m/romstage.c @@ -83,4 +83,24 @@ /* desktop type */ mem_cfg->UserBd = BOARD_TYPE_DESKTOP; + + /* initialize PEG 0:1:0 x16 Gen3 (8GT/s) root port */ + mupd->FspmConfig.Peg0Enable = 1; + mupd->FspmConfig.Peg0MaxLinkSpeed = 3; + + /* + * use Phase 2 Link Equalization for Gen3 Data Rate + * to minimize the BER (bit error rate) + */ + mupd->FspmTestConfig.Peg0Gen3EqPh2Enable = 1; + + /* + * Set primary display device + * default value: 3 (AUTO) + * 0: iGPU, 1: external GPU on PEG + */ + if(CONFIG(ONBOARD_VGA_IS_PRIMARY)) + mupd->FspmConfig.PrimaryDisplay = 0; + else + mupd->FspmConfig.PrimaryDisplay = 1; } -- To view, visit https://review.coreboot.org/c/coreboot/+/31948 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia4f29df47d76de5069fe53120434cc7c2ab6f044 Gerrit-Change-Number: 31948 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/skylake: Add devicetree options for PEG
by Maxim Polyakov (Code Review) 06 Apr '19

06 Apr '19

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32045 Change subject: soc/intel/skylake: Add devicetree options for PEG ...................................................................... soc/intel/skylake: Add devicetree options for PEG List of options for each port: - PegMaxLinkSpeed - PegMaxLinkWidth - PegPowerDownUnusedLanes - PegGen3EqPh2Enable To enable or disable the corresponding PEG root port you need to add to the devicetree.cb: device pci 01.0 on end # enable PEG0 root port device pci 01.1 off end # do not configure PEG1 If PEG port is not defined in the devicetree, it will be disabled in FSP. Change-Id: I23708f7060edf08739adf61fe61a419329907563 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/soc/intel/skylake/Kconfig M src/soc/intel/skylake/chip.h M src/soc/intel/skylake/include/soc/pci_devs.h M src/soc/intel/skylake/romstage/romstage_fsp20.c 4 files changed, 100 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/32045/1 diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 53094b1..de476ff 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -258,6 +258,10 @@ bool default n +config MAX_PEG_PORTS + int + default 3 + config MAX_ROOT_PORTS int default 24 if PLATFORM_USES_FSP2_0 diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index a8ee064..1f0e2f4 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -214,6 +214,42 @@ */ /* + * PEG max link speed + * 0: Maximum possible link speed, + * which is set in FSP. + * 1: Gen1 link speed + * 2: Gen2 link speed + * 3: Gen3 link speed + */ + u8 PegMaxLinkSpeed[CONFIG_MAX_PEG_PORTS]; + + /* + * PEG Max Link Width + * 0: Maximum possible link width: + * x16 for PEG0, + * x8 for PEG1, + * x4 for PEG2. + * 1: x1 + * 2: x4, only for PEG0 and PEG1 + * 3: x8, only for PEG0 + */ + u8 PegMaxLinkWidth[CONFIG_MAX_PEG_PORTS]; + + /* + * Power down unused lanes on PEG + * 0: No power saving + * 1: Power down unused lanes + */ + u8 PegPowerDownUnusedLanes[CONFIG_MAX_PEG_PORTS]; + + /* + * Phase2 EQ enable on the PEG + * 0: Disable phase 2 + * 1: Enable phase 2 + */ + u8 PegGen3EqPh2Enable[CONFIG_MAX_PEG_PORTS]; + + /* * Enable/Disable Root Port * 0: Disable Root Port * 1: Enable Root Port diff --git a/src/soc/intel/skylake/include/soc/pci_devs.h b/src/soc/intel/skylake/include/soc/pci_devs.h index f695794..d59c800 100644 --- a/src/soc/intel/skylake/include/soc/pci_devs.h +++ b/src/soc/intel/skylake/include/soc/pci_devs.h @@ -37,6 +37,13 @@ #define SA_DEVFN_ROOT _SA_DEVFN(ROOT) #define SA_DEV_ROOT _SA_DEV(ROOT) +#define SA_DEV_SLOT_PEG 0x01 +#define SA_DEVFN_PEG(func) PCI_DEVFN(SA_DEV_SLOT_PEG, func) +#define SA_DEV_PEG(func) dev_find_slot(0, SA_DEVFN_PEG(func)) +#define SA_DEV_PEG0 SA_DEV_PEG(0) +#define SA_DEV_PEG1 SA_DEV_PEG(1) +#define SA_DEV_PEG2 SA_DEV_PEG(2) + #define SA_DEV_SLOT_IGD 0x02 #define SA_DEVFN_IGD _SA_DEVFN(IGD) #define SA_DEV_IGD _SA_DEV(IGD) diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c index f38a775..b963d17 100644 --- a/src/soc/intel/skylake/romstage/romstage_fsp20.c +++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c @@ -202,6 +202,58 @@ m_cfg->CpuRatio = (flex_ratio.lo >> 8) & 0xff; } +static void soc_peg_init_params(FSP_M_CONFIG *m_cfg, + FSP_M_TEST_CONFIG *m_t_cfg, + const struct soc_intel_skylake_config *config) +{ + const struct device *dev; + /* + * To enable or disable the corresponding PEG root port you need to + * add to the devicetree.cb: + * + * device pci 01.0 on end # enable PEG0 root port + * device pci 01.1 off end # do not configure PEG1 + * + * If PEG port is not defined in the device tree, it will be disabled + * in FSP + */ + dev = SA_DEV_PEG0; /* PEG 0:1:0 */ + if (!dev || !dev->enabled) + m_cfg->Peg0Enable = 0; + else if (dev->enabled) { + m_cfg->Peg0Enable = dev->enabled; + m_cfg->Peg0MaxLinkSpeed = config->PegMaxLinkSpeed[0]; + m_cfg->Peg0MaxLinkWidth = config->PegMaxLinkWidth[0]; + m_cfg->Peg0PowerDownUnusedLanes = + config->PegPowerDownUnusedLanes[0]; + m_t_cfg->Peg0Gen3EqPh2Enable = config->PegGen3EqPh2Enable[0]; + } + + dev = SA_DEV_PEG1; /* PEG 0:1:1 */ + if (!dev || !dev->enabled) + m_cfg->Peg1Enable = 0; + else if (dev->enabled) { + m_cfg->Peg1Enable = dev->enabled; + m_cfg->Peg1MaxLinkSpeed = config->PegMaxLinkSpeed[1]; + m_cfg->Peg1MaxLinkWidth = config->PegMaxLinkWidth[1]; + m_cfg->Peg1PowerDownUnusedLanes = + config->PegPowerDownUnusedLanes[1]; + m_t_cfg->Peg1Gen3EqPh2Enable = config->PegGen3EqPh2Enable[1]; + } + + dev = SA_DEV_PEG0; /* PEG 0:1:2 */ + if (!dev || !dev->enabled) + m_cfg->Peg2Enable = 0; + else if (dev->enabled) { + m_cfg->Peg2Enable = dev->enabled; + m_cfg->Peg2MaxLinkSpeed = config->PegMaxLinkSpeed[2]; + m_cfg->Peg2MaxLinkWidth = config->PegMaxLinkWidth[2]; + m_cfg->Peg2PowerDownUnusedLanes = + config->PegPowerDownUnusedLanes[2]; + m_t_cfg->Peg2Gen3EqPh2Enable = config->PegGen3EqPh2Enable[2]; + } +} + static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const struct soc_intel_skylake_config *config) { @@ -254,6 +306,7 @@ config = dev->chip_info; soc_memory_init_params(m_cfg, config); + soc_peg_init_params(m_cfg, m_t_cfg, config); /* Skip creating Management Engine MBP HOB */ m_t_cfg->SkipMbpHob = 0x01; -- To view, visit https://review.coreboot.org/c/coreboot/+/32045 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I23708f7060edf08739adf61fe61a419329907563 Gerrit-Change-Number: 32045 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/asrock/h110m: Set PEG as primary GFX device
by Maxim Polyakov (Code Review) 06 Apr '19

06 Apr '19

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32172 Change subject: mb/asrock/h110m: Set PEG as primary GFX device ...................................................................... mb/asrock/h110m: Set PEG as primary GFX device If an external graphics card is inserted in the PEG, it will be used as the primary display device (as in the AMI BIOS) Change-Id: Iea846179fc309c2b98093de37c05ceb332081f4f Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/mainboard/asrock/h110m/devicetree.cb 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/32172/1 diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb index 397da37..b0756ca 100644 --- a/src/mainboard/asrock/h110m/devicetree.cb +++ b/src/mainboard/asrock/h110m/devicetree.cb @@ -46,6 +46,7 @@ register "ScsSdCardEnabled" = "0" register "HeciEnabled" = "0" register "SkipExtGfxScan" = "0" + register "PrimaryDisplay" = "Display_PEG" register "Device4Enable" = "1" register "SaGv" = "SaGv_Enabled" register "PmTimerDisabled" = "0" -- To view, visit https://review.coreboot.org/c/coreboot/+/32172 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iea846179fc309c2b98093de37c05ceb332081f4f Gerrit-Change-Number: 32172 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: {mb,soc/intel/skylake}: remove unused InternalGfx
by Maxim Polyakov (Code Review) 06 Apr '19

06 Apr '19

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32171 Change subject: {mb,soc/intel/skylake}: remove unused InternalGfx ...................................................................... {mb,soc/intel/skylake}: remove unused InternalGfx The InternalGfx option in devicetree.cb is not used to enable iGPU. The patch removes this option from chip.h and mb/*/devicetree.cb files for all boards with skl/kbl processor. Change-Id: I41ecca3fdfb1d4b20ee634a13263ff481dcf440e Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/mainboard/asrock/h110m/devicetree.cb M src/mainboard/google/eve/devicetree.cb M src/mainboard/google/fizz/variants/baseboard/devicetree.cb M src/mainboard/google/glados/variants/asuka/devicetree.cb M src/mainboard/google/glados/variants/caroline/devicetree.cb M src/mainboard/google/glados/variants/cave/devicetree.cb M src/mainboard/google/glados/variants/chell/devicetree.cb M src/mainboard/google/glados/variants/glados/devicetree.cb M src/mainboard/google/glados/variants/lars/devicetree.cb M src/mainboard/google/glados/variants/sentry/devicetree.cb M src/mainboard/google/poppy/variants/atlas/devicetree.cb M src/mainboard/google/poppy/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/nami/devicetree.cb M src/mainboard/google/poppy/variants/nautilus/devicetree.cb M src/mainboard/google/poppy/variants/nocturne/devicetree.cb M src/mainboard/google/poppy/variants/rammus/devicetree.cb M src/mainboard/google/poppy/variants/soraka/devicetree.cb M src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb M src/mainboard/intel/kunimitsu/devicetree.cb M src/mainboard/intel/saddlebrook/devicetree.cb M src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb M src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb M src/soc/intel/skylake/chip.h 23 files changed, 0 insertions(+), 23 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/32171/1 diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb index 9e2fca0..397da37 100644 --- a/src/mainboard/asrock/h110m/devicetree.cb +++ b/src/mainboard/asrock/h110m/devicetree.cb @@ -45,7 +45,6 @@ register "ScsEmmcHs400Enabled" = "0" register "ScsSdCardEnabled" = "0" register "HeciEnabled" = "0" - register "InternalGfx" = "1" register "SkipExtGfxScan" = "0" register "Device4Enable" = "1" register "SaGv" = "SaGv_Enabled" diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb index 2f275ac..bffcf84 100644 --- a/src/mainboard/google/eve/devicetree.cb +++ b/src/mainboard/google/eve/devicetree.cb @@ -41,7 +41,6 @@ register "ScsEmmcHs400Enabled" = "1" register "ScsSdCardEnabled" = "0" register "PttSwitch" = "0" - register "InternalGfx" = "1" register "SkipExtGfxScan" = "1" register "Device4Enable" = "1" register "HeciEnabled" = "0" diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb index bfabe29..f1c846e 100644 --- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb @@ -76,7 +76,6 @@ register "ScsEmmcHs400Enabled" = "0" register "ScsSdCardEnabled" = "2" register "PttSwitch" = "0" - register "InternalGfx" = "1" register "SkipExtGfxScan" = "1" register "Device4Enable" = "1" register "HeciEnabled" = "0" diff --git a/src/mainboard/google/glados/variants/asuka/devicetree.cb b/src/mainboard/google/glados/variants/asuka/devicetree.cb index e0a792d..13dfa29 100644 --- a/src/mainboard/google/glados/variants/asuka/devicetree.cb +++ b/src/mainboard/google/glados/variants/asuka/devicetree.cb @@ -33,7 +33,6 @@ register "ScsEmmcEnabled" = "1" register "ScsEmmcHs400Enabled" = "1" register "ScsSdCardEnabled" = "0" - register "InternalGfx" = "1" register "SkipExtGfxScan" = "1" register "Device4Enable" = "1" register "HeciEnabled" = "0" diff --git a/src/mainboard/google/glados/variants/caroline/devicetree.cb b/src/mainboard/google/glados/variants/caroline/devicetree.cb index 0f5a911..1a67cce 100644 --- a/src/mainboard/google/glados/variants/caroline/devicetree.cb +++ b/src/mainboard/google/glados/variants/caroline/devicetree.cb @@ -43,7 +43,6 @@ register "ScsEmmcHs400Enabled" = "1" register "ScsSdCardEnabled" = "2" register "PttSwitch" = "0" - register "InternalGfx" = "1" register "SkipExtGfxScan" = "1" register "Device4Enable" = "1" register "HeciEnabled" = "0" diff --git a/src/mainboard/google/glados/variants/cave/devicetree.cb b/src/mainboard/google/glados/variants/cave/devicetree.cb index a9b28a8..9a2fc12 100644 --- a/src/mainboard/google/glados/variants/cave/devicetree.cb +++ b/src/mainboard/google/glados/variants/cave/devicetree.cb @@ -43,7 +43,6 @@ register "ScsEmmcHs400Enabled" = "1" register "ScsSdCardEnabled" = "2" register "PttSwitch" = "0" - register "InternalGfx" = "1" register "SkipExtGfxScan" = "1" register "Device4Enable" = "1" register "HeciEnabled" = "0" diff --git a/src/mainboard/google/glados/variants/chell/devicetree.cb b/src/mainboard/google/glados/variants/chell/devicetree.cb index 07467b3..de8641c 100644 --- a/src/mainboard/google/glados/variants/chell/devicetree.cb +++ b/src/mainboard/google/glados/variants/chell/devicetree.cb @@ -43,7 +43,6 @@ register "ScsEmmcHs400Enabled" = "1" register "ScsSdCardEnabled" = "0" register "PttSwitch" = "0" - register "InternalGfx" = "1" register "SkipExtGfxScan" = "1" register "Device4Enable" = "1" register "HeciEnabled" = "0" diff --git a/src/mainboard/google/glados/variants/glados/devicetree.cb b/src/mainboard/google/glados/variants/glados/devicetree.cb index d4266cc..0d27a44 100644 --- a/src/mainboard/google/glados/variants/glados/devicetree.cb +++ b/src/mainboard/google/glados/variants/glados/devicetree.cb @@ -43,7 +43,6 @@ register "ScsEmmcHs400Enabled" = "1" register "ScsSdCardEnabled" = "2" register "PttSwitch" = "0" - register "InternalGfx" = "1" register "SkipExtGfxScan" = "1" register "Device4Enable" = "1" register "HeciEnabled" = "0" diff --git a/src/mainboard/google/glados/variants/lars/devicetree.cb b/src/mainboard/google/glados/variants/lars/devicetree.cb index f3f5eab..204ade2 100644 --- a/src/mainboard/google/glados/variants/lars/devicetree.cb +++ b/src/mainboard/google/glados/variants/lars/devicetree.cb @@ -31,7 +31,6 @@ register "ScsEmmcEnabled" = "1" register "ScsEmmcHs400Enabled" = "1" register "ScsSdCardEnabled" = "0" - register "InternalGfx" = "1" register "SkipExtGfxScan" = "1" register "Device4Enable" = "1" register "HeciEnabled" = "0" diff --git a/src/mainboard/google/glados/variants/sentry/devicetree.cb b/src/mainboard/google/glados/variants/sentry/devicetree.cb index 5cce0f0..89120a3 100644 --- a/src/mainboard/google/glados/variants/sentry/devicetree.cb +++ b/src/mainboard/google/glados/variants/sentry/devicetree.cb @@ -33,7 +33,6 @@ register "ScsEmmcEnabled" = "1" register "ScsEmmcHs400Enabled" = "1" register "ScsSdCardEnabled" = "2" - register "InternalGfx" = "1" register "SkipExtGfxScan" = "1" register "Device4Enable" = "1" register "HeciEnabled" = "0" diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb index 87d7348..53af87d 100644 --- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb +++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb @@ -49,7 +49,6 @@ register "ScsEmmcHs400Enabled" = "1" register "ScsSdCardEnabled" = "0" register "PttSwitch" = "0" - register "InternalGfx" = "1" register "SkipExtGfxScan" = "1" register "Device4Enable" = "1" register "HeciEnabled" = "0" diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb index 7335c0a..727a10f 100644 --- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb @@ -46,7 +46,6 @@ register "ScsEmmcHs400Enabled" = "1" register "ScsSdCardEnabled" = "2" register "PttSwitch" = "0" - register "InternalGfx" = "1" register "SkipExtGfxScan" = "1" register "Device4Enable" = "1" register "HeciEnabled" = "0" diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb index 59cca29..7c11ea1 100644 --- a/src/mainboard/google/poppy/variants/nami/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb @@ -45,7 +45,6 @@ register "ScsEmmcHs400Enabled" = "1" register "ScsSdCardEnabled" = "0" register "PttSwitch" = "0" - register "InternalGfx" = "1" register "SkipExtGfxScan" = "1" register "Device4Enable" = "1" register "HeciEnabled" = "0" diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb index fed85b6..1e4133b 100644 --- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb @@ -46,7 +46,6 @@ register "ScsEmmcHs400Enabled" = "1" register "ScsSdCardEnabled" = "2" register "PttSwitch" = "0" - register "InternalGfx" = "1" register "SkipExtGfxScan" = "1" register "Device4Enable" = "1" register "HeciEnabled" = "0" diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb index ac52208..bf1897c 100644 --- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb @@ -51,7 +51,6 @@ register "ScsEmmcHs400Enabled" = "1" register "ScsSdCardEnabled" = "0" register "PttSwitch" = "0" - register "InternalGfx" = "1" register "SkipExtGfxScan" = "1" register "Device4Enable" = "1" register "HeciEnabled" = "0" diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb index 4f58f40..1f73a59 100644 --- a/src/mainboard/google/poppy/variants/rammus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb @@ -49,7 +49,6 @@ register "ScsEmmcHs400Enabled" = "1" register "ScsSdCardEnabled" = "2" register "PttSwitch" = "0" - register "InternalGfx" = "1" register "SkipExtGfxScan" = "1" register "Device4Enable" = "1" register "HeciEnabled" = "0" diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb index d813cc1..872e2e5 100644 --- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb +++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb @@ -46,7 +46,6 @@ register "ScsEmmcHs400Enabled" = "1" register "ScsSdCardEnabled" = "2" register "PttSwitch" = "0" - register "InternalGfx" = "1" register "SkipExtGfxScan" = "1" register "Device4Enable" = "1" register "HeciEnabled" = "0" diff --git a/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb index fcd5aab..2a1cb8a 100644 --- a/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb @@ -27,7 +27,6 @@ register "ScsEmmcEnabled" = "1" register "ScsEmmcHs400Enabled" = "1" register "ScsSdCardEnabled" = "2" - register "InternalGfx" = "1" register "SkipExtGfxScan" = "1" register "Device4Enable" = "1" register "SaGv" = "SaGv_Enabled" diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb index ec1c11f..f2c9f43 100644 --- a/src/mainboard/intel/kunimitsu/devicetree.cb +++ b/src/mainboard/intel/kunimitsu/devicetree.cb @@ -31,7 +31,6 @@ register "ScsEmmcEnabled" = "1" register "ScsEmmcHs400Enabled" = "1" register "ScsSdCardEnabled" = "2" - register "InternalGfx" = "1" register "SkipExtGfxScan" = "1" register "Device4Enable" = "1" register "HeciEnabled" = "0" diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb index 2f84a5d..3322bf8 100644 --- a/src/mainboard/intel/saddlebrook/devicetree.cb +++ b/src/mainboard/intel/saddlebrook/devicetree.cb @@ -39,7 +39,6 @@ register "ScsEmmcEnabled" = "0" register "ScsEmmcHs400Enabled" = "0" register "ScsSdCardEnabled" = "0" - register "InternalGfx" = "1" register "SkipExtGfxScan" = "1" register "Device4Enable" = "0" register "Heci3Enabled" = "0" diff --git a/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb b/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb index 8d2a436..944a2dd 100644 --- a/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb +++ b/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb @@ -56,7 +56,6 @@ register "ScsEmmcHs400Enabled" = "0" register "ScsSdCardEnabled" = "0" register "PttSwitch" = "0" - register "InternalGfx" = "1" register "SkipExtGfxScan" = "1" register "Device4Enable" = "1" register "HeciEnabled" = "0" diff --git a/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb b/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb index 49af7b6..4ac0610 100644 --- a/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb +++ b/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb @@ -56,7 +56,6 @@ register "ScsEmmcHs400Enabled" = "0" register "ScsSdCardEnabled" = "0" register "PttSwitch" = "0" - register "InternalGfx" = "1" register "SkipExtGfxScan" = "1" register "Device4Enable" = "1" register "HeciEnabled" = "0" diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index f87a811..a9b8641 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -318,7 +318,6 @@ Display_Auto, Display_Switchable, } PrimaryDisplay; - u8 InternalGfx; u8 ApertureSize; u8 SkipExtGfxScan; u8 ScanExtGfxForLegacyOpRom; -- To view, visit https://review.coreboot.org/c/coreboot/+/32171 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I41ecca3fdfb1d4b20ee634a13263ff481dcf440e Gerrit-Change-Number: 32171 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

3 5

Change in ...coreboot[master]: payloads: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)
by Julius Werner (Code Review) 06 Apr '19

06 Apr '19

Hello Aaron Durbin, Patrick Georgi, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/31775 to review the following change. Change subject: payloads: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX) ...................................................................... payloads: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX) This patch is a raw application of find payloads/ -type f | \ xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g' Change-Id: I883b03b189f59b5d998a09a2596b0391a2d5cf33 Signed-off-by: Julius Werner <jwerner(a)chromium.org> --- M payloads/coreinfo/bootlog_module.c M payloads/coreinfo/cbfs_module.c M payloads/coreinfo/coreboot_module.c M payloads/coreinfo/coreinfo.c M payloads/coreinfo/cpuinfo_module.c M payloads/coreinfo/multiboot_module.c M payloads/coreinfo/nvram_module.c M payloads/coreinfo/pci_module.c M payloads/coreinfo/ramdump_module.c M payloads/coreinfo/timestamps_module.c M payloads/external/tint/libpayload_tint.patch M payloads/libpayload/arch/arm/main.c M payloads/libpayload/arch/arm64/main.c M payloads/libpayload/arch/mips/main.c M payloads/libpayload/arch/x86/delay.c M payloads/libpayload/arch/x86/exception.c M payloads/libpayload/arch/x86/main.c M payloads/libpayload/arch/x86/multiboot.c M payloads/libpayload/arch/x86/rom_media.c M payloads/libpayload/arch/x86/sysinfo.c M payloads/libpayload/crypto/sha1.c M payloads/libpayload/curses/keyboard.c M payloads/libpayload/curses/local.h M payloads/libpayload/curses/pdcurses-backend/pdcdisp.c M payloads/libpayload/curses/pdcurses-backend/pdckbd.c M payloads/libpayload/curses/pdcurses-backend/pdcscrn.c M payloads/libpayload/curses/pdcurses-backend/pdcsetsc.c M payloads/libpayload/curses/pdcurses-backend/pdcutil.c M payloads/libpayload/curses/tinycurses.c M payloads/libpayload/drivers/i8042/i8042.c M payloads/libpayload/drivers/i8042/keyboard.c M payloads/libpayload/drivers/mouse_cursor.c M payloads/libpayload/drivers/nvram.c M payloads/libpayload/drivers/serial/8250.c M payloads/libpayload/drivers/storage/ahci.c M payloads/libpayload/drivers/storage/ahci_ata.c M payloads/libpayload/drivers/storage/ata.c M payloads/libpayload/drivers/storage/storage.c M payloads/libpayload/drivers/usb/ehci.c M payloads/libpayload/drivers/usb/ehci_rh.c M payloads/libpayload/drivers/usb/ohci.c M payloads/libpayload/drivers/usb/usb.c M payloads/libpayload/drivers/usb/usbhid.c M payloads/libpayload/drivers/usb/usbinit.c M payloads/libpayload/drivers/usb/xhci.c M payloads/libpayload/drivers/usb/xhci_devconf.c M payloads/libpayload/drivers/usb/xhci_rh.c M payloads/libpayload/drivers/video/video.c M payloads/libpayload/include/endian.h M payloads/libpayload/include/stdlib.h M payloads/libpayload/include/storage/storage.h M payloads/libpayload/include/sysinfo.h M payloads/libpayload/libc/64bit_div.c M payloads/libpayload/libc/console.c M payloads/libpayload/libc/coreboot.c M payloads/libpayload/libc/exec.c M payloads/libpayload/libc/malloc.c M payloads/libpayload/libc/time.c M payloads/libpayload/libcbfs/cbfs.c M payloads/libpayload/libcbfs/cbfs_core.c M payloads/nvramcui/nvramcui.c 61 files changed, 176 insertions(+), 176 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/31775/1 diff --git a/payloads/coreinfo/bootlog_module.c b/payloads/coreinfo/bootlog_module.c index 1d00744..caf5d13 100644 --- a/payloads/coreinfo/bootlog_module.c +++ b/payloads/coreinfo/bootlog_module.c @@ -15,7 +15,7 @@ #include "coreinfo.h" -#if IS_ENABLED(CONFIG_MODULE_BOOTLOG) +#if CONFIG(MODULE_BOOTLOG) #define LINES_SHOWN 19 #define TAB_WIDTH 2 diff --git a/payloads/coreinfo/cbfs_module.c b/payloads/coreinfo/cbfs_module.c index 6a04879..e7cfc8c 100644 --- a/payloads/coreinfo/cbfs_module.c +++ b/payloads/coreinfo/cbfs_module.c @@ -16,7 +16,7 @@ #include "coreinfo.h" #include "endian.h" -#if IS_ENABLED(CONFIG_MODULE_CBFS) +#if CONFIG(MODULE_CBFS) #define FILES_VISIBLE 19 diff --git a/payloads/coreinfo/coreboot_module.c b/payloads/coreinfo/coreboot_module.c index adf8f14..d294288 100644 --- a/payloads/coreinfo/coreboot_module.c +++ b/payloads/coreinfo/coreboot_module.c @@ -16,7 +16,7 @@ #include "coreinfo.h" #include <coreboot_tables.h> -#if IS_ENABLED(CONFIG_MODULE_COREBOOT) +#if CONFIG(MODULE_COREBOOT) #define MAX_MEMORY_COUNT 5 diff --git a/payloads/coreinfo/coreinfo.c b/payloads/coreinfo/coreinfo.c index 718c589..649bfde 100644 --- a/payloads/coreinfo/coreinfo.c +++ b/payloads/coreinfo/coreinfo.c @@ -28,34 +28,34 @@ extern struct coreinfo_module timestamps_module; struct coreinfo_module *system_modules[] = { -#if IS_ENABLED(CONFIG_MODULE_CPUINFO) +#if CONFIG(MODULE_CPUINFO) &cpuinfo_module, #endif -#if IS_ENABLED(CONFIG_MODULE_PCI) +#if CONFIG(MODULE_PCI) &pci_module, #endif -#if IS_ENABLED(CONFIG_MODULE_NVRAM) +#if CONFIG(MODULE_NVRAM) &nvram_module, #endif -#if IS_ENABLED(CONFIG_MODULE_RAMDUMP) +#if CONFIG(MODULE_RAMDUMP) &ramdump_module, #endif }; struct coreinfo_module *firmware_modules[] = { -#if IS_ENABLED(CONFIG_MODULE_COREBOOT) +#if CONFIG(MODULE_COREBOOT) &coreboot_module, #endif -#if IS_ENABLED(CONFIG_MODULE_MULTIBOOT) +#if CONFIG(MODULE_MULTIBOOT) &multiboot_module, #endif -#if IS_ENABLED(CONFIG_MODULE_BOOTLOG) +#if CONFIG(MODULE_BOOTLOG) &bootlog_module, #endif -#if IS_ENABLED(CONFIG_MODULE_CBFS) +#if CONFIG(MODULE_CBFS) &cbfs_module, #endif -#if IS_ENABLED(CONFIG_MODULE_TIMESTAMPS) +#if CONFIG(MODULE_TIMESTAMPS) &timestamps_module, #endif }; @@ -114,7 +114,7 @@ mvwprintw(menuwin, 0, 0, menu); } -#if IS_ENABLED(CONFIG_SHOW_DATE_TIME) +#if CONFIG(SHOW_DATE_TIME) static void print_time_and_date(void) { struct tm tm; @@ -149,7 +149,7 @@ mvwprintw(menuwin, 1, 0, menu); -#if IS_ENABLED(CONFIG_SHOW_DATE_TIME) +#if CONFIG(SHOW_DATE_TIME) print_time_and_date(); #endif } @@ -253,7 +253,7 @@ while (1) { int ch = -1; -#if IS_ENABLED(CONFIG_SHOW_DATE_TIME) +#if CONFIG(SHOW_DATE_TIME) print_time_and_date(); wrefresh(menuwin); #endif @@ -291,7 +291,7 @@ { int i, j; - if (IS_ENABLED(CONFIG_LP_USB)) + if (CONFIG(LP_USB)) usb_initialize(); initscr(); diff --git a/payloads/coreinfo/cpuinfo_module.c b/payloads/coreinfo/cpuinfo_module.c index 72b941e..0ea2dfc 100644 --- a/payloads/coreinfo/cpuinfo_module.c +++ b/payloads/coreinfo/cpuinfo_module.c @@ -18,7 +18,7 @@ #include "coreinfo.h" -#if IS_ENABLED(CONFIG_MODULE_CPUINFO) +#if CONFIG(MODULE_CPUINFO) #include <arch/rdtsc.h> #define VENDOR_INTEL 0x756e6547 diff --git a/payloads/coreinfo/multiboot_module.c b/payloads/coreinfo/multiboot_module.c index 2fc60fa..e394dbd 100644 --- a/payloads/coreinfo/multiboot_module.c +++ b/payloads/coreinfo/multiboot_module.c @@ -16,7 +16,7 @@ #include <multiboot_tables.h> #include "coreinfo.h" -#if IS_ENABLED(CONFIG_MODULE_MULTIBOOT) +#if CONFIG(MODULE_MULTIBOOT) #define MAX_MEMORY_COUNT 10 diff --git a/payloads/coreinfo/nvram_module.c b/payloads/coreinfo/nvram_module.c index 7997911..45edfb3 100644 --- a/payloads/coreinfo/nvram_module.c +++ b/payloads/coreinfo/nvram_module.c @@ -15,7 +15,7 @@ #include "coreinfo.h" -#if IS_ENABLED(CONFIG_MODULE_NVRAM) +#if CONFIG(MODULE_NVRAM) /** * Dump 256 bytes of NVRAM. diff --git a/payloads/coreinfo/pci_module.c b/payloads/coreinfo/pci_module.c index 9f10b12..ff042af 100644 --- a/payloads/coreinfo/pci_module.c +++ b/payloads/coreinfo/pci_module.c @@ -18,7 +18,7 @@ #include <libpayload.h> #include "coreinfo.h" -#if IS_ENABLED(CONFIG_MODULE_PCI) +#if CONFIG(MODULE_PCI) struct pci_devices { pcidev_t device; diff --git a/payloads/coreinfo/ramdump_module.c b/payloads/coreinfo/ramdump_module.c index 8401a61..28d7a03 100644 --- a/payloads/coreinfo/ramdump_module.c +++ b/payloads/coreinfo/ramdump_module.c @@ -15,7 +15,7 @@ #include "coreinfo.h" -#if IS_ENABLED(CONFIG_MODULE_RAMDUMP) +#if CONFIG(MODULE_RAMDUMP) static s64 cursor = 0; static s64 cursor_max = (1 * 1024 * 1024 * 1024); /* Max. 1 GB RAM for now. */ diff --git a/payloads/coreinfo/timestamps_module.c b/payloads/coreinfo/timestamps_module.c index fda5a96..0978f31 100644 --- a/payloads/coreinfo/timestamps_module.c +++ b/payloads/coreinfo/timestamps_module.c @@ -14,7 +14,7 @@ #include "coreinfo.h" #include <commonlib/timestamp_serialized.h> -#if IS_ENABLED(CONFIG_MODULE_TIMESTAMPS) +#if CONFIG(MODULE_TIMESTAMPS) #define LINES_SHOWN 19 #define TAB_WIDTH 2 diff --git a/payloads/external/tint/libpayload_tint.patch b/payloads/external/tint/libpayload_tint.patch index bb19718..34246a6 100644 --- a/payloads/external/tint/libpayload_tint.patch +++ b/payloads/external/tint/libpayload_tint.patch @@ -371,7 +371,7 @@ int ch; engine_t engine; /* Initialize */ -+ if (IS_ENABLED(CONFIG_LP_USB)) ++ if (CONFIG(LP_USB)) + usb_initialize(); rand_init (); /* must be called before engine_init () */ engine_init (&engine,score_function); /* must be called before using engine.curshape */ diff --git a/payloads/libpayload/arch/arm/main.c b/payloads/libpayload/arch/arm/main.c index b63e0be..cb2d242 100644 --- a/payloads/libpayload/arch/arm/main.c +++ b/payloads/libpayload/arch/arm/main.c @@ -48,7 +48,7 @@ lib_get_sysinfo(); /* Optionally set up the consoles. */ -#if !IS_ENABLED(CONFIG_LP_SKIP_CONSOLE_INIT) +#if !CONFIG(LP_SKIP_CONSOLE_INIT) console_init(); #endif diff --git a/payloads/libpayload/arch/arm64/main.c b/payloads/libpayload/arch/arm64/main.c index aa2292f..593c40e 100644 --- a/payloads/libpayload/arch/arm64/main.c +++ b/payloads/libpayload/arch/arm64/main.c @@ -123,7 +123,7 @@ post_sysinfo_scan_mmu_setup(); -#if !IS_ENABLED(CONFIG_LP_SKIP_CONSOLE_INIT) +#if !CONFIG(LP_SKIP_CONSOLE_INIT) console_init(); #endif diff --git a/payloads/libpayload/arch/mips/main.c b/payloads/libpayload/arch/mips/main.c index 9f9326e..b8c0c4d 100644 --- a/payloads/libpayload/arch/mips/main.c +++ b/payloads/libpayload/arch/mips/main.c @@ -34,7 +34,7 @@ lib_get_sysinfo(); /* Optionally set up the consoles. */ -#if !IS_ENABLED(CONFIG_LP_SKIP_CONSOLE_INIT) +#if !CONFIG(LP_SKIP_CONSOLE_INIT) console_init(); #endif diff --git a/payloads/libpayload/arch/x86/delay.c b/payloads/libpayload/arch/x86/delay.c index a617ce6..14056dd 100644 --- a/payloads/libpayload/arch/x86/delay.c +++ b/payloads/libpayload/arch/x86/delay.c @@ -50,7 +50,7 @@ if (ns > APIC_INTERRUPT_LATENCY_NS) apic_us = (ns - APIC_INTERRUPT_LATENCY_NS) / NSECS_PER_USEC; - if (IS_ENABLED(CONFIG_LP_ENABLE_APIC) && apic_initialized() && apic_us) + if (CONFIG(LP_ENABLE_APIC) && apic_initialized() && apic_us) apic_delay(apic_us); if (delta > PAUSE_THRESHOLD_TICKS) diff --git a/payloads/libpayload/arch/x86/exception.c b/payloads/libpayload/arch/x86/exception.c index 983a9f3..13ff58c 100644 --- a/payloads/libpayload/arch/x86/exception.c +++ b/payloads/libpayload/arch/x86/exception.c @@ -173,10 +173,10 @@ handlers[vec](vec); goto success; } else if (vec >= EXC_COUNT - && IS_ENABLED(CONFIG_LP_IGNORE_UNKNOWN_INTERRUPTS)) { + && CONFIG(LP_IGNORE_UNKNOWN_INTERRUPTS)) { goto success; } else if (vec >= EXC_COUNT - && IS_ENABLED(CONFIG_LP_LOG_UNKNOWN_INTERRUPTS)) { + && CONFIG(LP_LOG_UNKNOWN_INTERRUPTS)) { printf("Ignoring interrupt vector %u\n", vec); goto success; } @@ -192,7 +192,7 @@ return; success: - if (IS_ENABLED(CONFIG_LP_ENABLE_APIC)) + if (CONFIG(LP_ENABLE_APIC)) apic_eoi(vec); } diff --git a/payloads/libpayload/arch/x86/main.c b/payloads/libpayload/arch/x86/main.c index 05ffa0d..4da0bba 100644 --- a/payloads/libpayload/arch/x86/main.c +++ b/payloads/libpayload/arch/x86/main.c @@ -52,13 +52,13 @@ lib_get_sysinfo(); /* Optionally set up the consoles. */ -#if !IS_ENABLED(CONFIG_LP_SKIP_CONSOLE_INIT) +#if !CONFIG(LP_SKIP_CONSOLE_INIT) console_init(); #endif exception_init(); - if (IS_ENABLED(CONFIG_LP_ENABLE_APIC)) { + if (CONFIG(LP_ENABLE_APIC)) { apic_init(); enable_interrupts(); diff --git a/payloads/libpayload/arch/x86/multiboot.c b/payloads/libpayload/arch/x86/multiboot.c index 1cd0295..76eeae3 100644 --- a/payloads/libpayload/arch/x86/multiboot.c +++ b/payloads/libpayload/arch/x86/multiboot.c @@ -40,7 +40,7 @@ if (info->n_memranges >= SYSINFO_MAX_MEM_RANGES) return -1; -#if IS_ENABLED(CONFIG_LP_MEMMAP_RAM_ONLY) +#if CONFIG(LP_MEMMAP_RAM_ONLY) /* 1 == normal RAM. Ignore everything else for now */ if (type != 1) return 0; diff --git a/payloads/libpayload/arch/x86/rom_media.c b/payloads/libpayload/arch/x86/rom_media.c index 0c6f521..d9c27fa 100644 --- a/payloads/libpayload/arch/x86/rom_media.c +++ b/payloads/libpayload/arch/x86/rom_media.c @@ -83,7 +83,7 @@ struct cbfs_header *header = (struct cbfs_header*) *(uint32_t*)(0xfffffffc); if (CBFS_HEADER_MAGIC != ntohl(header->magic)) { -#if IS_ENABLED(CONFIG_LP_ROM_SIZE) +#if CONFIG(LP_ROM_SIZE) printk(BIOS_ERR, "Invalid CBFS master header at %p\n", header); media->context = (void*)CONFIG_LP_ROM_SIZE; #else @@ -92,7 +92,7 @@ } else { uint32_t romsize = ntohl(header->romsize); media->context = (void*)romsize; -#if IS_ENABLED(CONFIG_LP_ROM_SIZE) +#if CONFIG(LP_ROM_SIZE) if (CONFIG_LP_ROM_SIZE != romsize) printk(BIOS_INFO, "Warning: rom size unmatch (%d/%d)\n", CONFIG_LP_ROM_SIZE, romsize); diff --git a/payloads/libpayload/arch/x86/sysinfo.c b/payloads/libpayload/arch/x86/sysinfo.c index ddd6550..4494f0b 100644 --- a/payloads/libpayload/arch/x86/sysinfo.c +++ b/payloads/libpayload/arch/x86/sysinfo.c @@ -40,7 +40,7 @@ */ struct sysinfo_t lib_sysinfo = { .cpu_khz = CPU_KHZ_DEFAULT, -#if IS_ENABLED(CONFIG_LP_SERIAL_CONSOLE) +#if CONFIG(LP_SERIAL_CONSOLE) .ser_ioport = CONFIG_LP_SERIAL_IOBASE, #else .ser_ioport = 0x3f8, @@ -51,7 +51,7 @@ { int ret; -#if IS_ENABLED(CONFIG_LP_MULTIBOOT) +#if CONFIG(LP_MULTIBOOT) /* Get the information from the multiboot tables, * if they exist */ get_multiboot_info(&lib_sysinfo); diff --git a/payloads/libpayload/crypto/sha1.c b/payloads/libpayload/crypto/sha1.c index 721d1a4..fc4a4f3 100644 --- a/payloads/libpayload/crypto/sha1.c +++ b/payloads/libpayload/crypto/sha1.c @@ -30,7 +30,7 @@ /* Moved from libpayload.h */ -#if IS_ENABLED(CONFIG_LP_LITTLE_ENDIAN) +#if CONFIG(LP_LITTLE_ENDIAN) #define BYTE_ORDER LITTLE_ENDIAN #else #define BYTE_ORDER BIG_ENDIAN diff --git a/payloads/libpayload/curses/keyboard.c b/payloads/libpayload/curses/keyboard.c index f571d56..fe9dc34 100644 --- a/payloads/libpayload/curses/keyboard.c +++ b/payloads/libpayload/curses/keyboard.c @@ -45,7 +45,7 @@ /* ============== Serial ==================== */ -#if IS_ENABLED(CONFIG_LP_SERIAL_CONSOLE) +#if CONFIG(LP_SERIAL_CONSOLE) /* We treat serial like a vt100 terminal. For now we do the cooking in here, but we should probably eventually pass it to dedicated vt100 code */ @@ -146,13 +146,13 @@ static int curses_getchar(int _delay) { -#if IS_ENABLED(CONFIG_LP_USB_HID) || IS_ENABLED(CONFIG_LP_PC_KEYBOARD) || \ - IS_ENABLED(CONFIG_LP_SERIAL_CONSOLE) +#if CONFIG(LP_USB_HID) || CONFIG(LP_PC_KEYBOARD) || \ + CONFIG(LP_SERIAL_CONSOLE) unsigned short c; #endif do { -#if IS_ENABLED(CONFIG_LP_USB_HID) +#if CONFIG(LP_USB_HID) usb_poll(); if ((curses_flags & F_ENABLE_CONSOLE) && usbhid_havechar()) { @@ -160,7 +160,7 @@ if (c != 0) return c; } #endif -#if IS_ENABLED(CONFIG_LP_PC_KEYBOARD) +#if CONFIG(LP_PC_KEYBOARD) if ((curses_flags & F_ENABLE_CONSOLE) && keyboard_havechar()) { c = keyboard_getchar(); @@ -168,7 +168,7 @@ } #endif -#if IS_ENABLED(CONFIG_LP_SERIAL_CONSOLE) +#if CONFIG(LP_SERIAL_CONSOLE) if ((curses_flags & F_ENABLE_SERIAL) && serial_havechar()) { c = serial_getchar(); @@ -226,7 +226,7 @@ return 0; } -#if IS_ENABLED(CONFIG_LP_VGA_VIDEO_CONSOLE) +#if CONFIG(LP_VGA_VIDEO_CONSOLE) void curses_enable_vga(int state) { if (state) @@ -244,7 +244,7 @@ int curses_vga_enabled(void) { return 0; } #endif -#if IS_ENABLED(CONFIG_LP_SERIAL_CONSOLE) +#if CONFIG(LP_SERIAL_CONSOLE) void curses_enable_serial(int state) { if (state) diff --git a/payloads/libpayload/curses/local.h b/payloads/libpayload/curses/local.h index 660f5db..274c389 100644 --- a/payloads/libpayload/curses/local.h +++ b/payloads/libpayload/curses/local.h @@ -70,13 +70,13 @@ /* Flags used to determine what output methods are available */ -#if IS_ENABLED(CONFIG_LP_VIDEO_CONSOLE) +#if CONFIG(LP_VIDEO_CONSOLE) #define F_ENABLE_CONSOLE 0x01 #else #define F_ENABLE_CONSOLE 0x00 #endif -#if IS_ENABLED(CONFIG_LP_SERIAL_CONSOLE) +#if CONFIG(LP_SERIAL_CONSOLE) #define F_ENABLE_SERIAL 0x02 #else #define F_ENABLE_SERIAL 0x00 diff --git a/payloads/libpayload/curses/pdcurses-backend/pdcdisp.c b/payloads/libpayload/curses/pdcurses-backend/pdcdisp.c index af1b50a..234d62a 100644 --- a/payloads/libpayload/curses/pdcurses-backend/pdcdisp.c +++ b/payloads/libpayload/curses/pdcurses-backend/pdcdisp.c @@ -66,8 +66,8 @@ '|', '<', '>', '*', '!', 'f', 'o', ' ', }; -#if IS_ENABLED(CONFIG_LP_SERIAL_CONSOLE) -#if IS_ENABLED(CONFIG_LP_SERIAL_ACS_FALLBACK) +#if CONFIG(LP_SERIAL_CONSOLE) +#if CONFIG(LP_SERIAL_ACS_FALLBACK) chtype serial_acs_map[128]; #else /* See acsc of vt100. */ @@ -93,7 +93,7 @@ #endif #endif -#if IS_ENABLED(CONFIG_LP_VIDEO_CONSOLE) +#if CONFIG(LP_VIDEO_CONSOLE) /* See acsc of linux. */ chtype console_acs_map[128] = { @@ -122,10 +122,10 @@ { PDC_LOG(("PDC_gotoyx() - called: row %d col %d\n", row, col)); -#if IS_ENABLED(CONFIG_LP_SERIAL_CONSOLE) +#if CONFIG(LP_SERIAL_CONSOLE) serial_set_cursor(col, row); #endif -#if IS_ENABLED(CONFIG_LP_VIDEO_CONSOLE) +#if CONFIG(LP_VIDEO_CONSOLE) video_console_set_cursor(col, row); #endif } @@ -139,7 +139,7 @@ PDC_LOG(("PDC_transform_line() - called: line %d, len %d, curses_flags %d\n", lineno, len, curses_flags)); -#if IS_ENABLED(CONFIG_LP_SERIAL_CONSOLE) +#if CONFIG(LP_SERIAL_CONSOLE) int serial_is_bold = 0; int serial_is_reverse = 0; int serial_is_altcharset = 0; @@ -157,7 +157,7 @@ { ch = srcp[j]; attr = ch; -#if IS_ENABLED(CONFIG_LP_SERIAL_CONSOLE) +#if CONFIG(LP_SERIAL_CONSOLE) if (curses_flags & F_ENABLE_SERIAL) { if (attr & A_BOLD) { if (!serial_is_bold) { @@ -222,7 +222,7 @@ } #endif -#if IS_ENABLED(CONFIG_LP_VIDEO_CONSOLE) +#if CONFIG(LP_VIDEO_CONSOLE) unsigned char c = pdc_atrtab[srcp[j] >> PDC_ATTR_SHIFT]; if (curses_flags & F_ENABLE_CONSOLE) { diff --git a/payloads/libpayload/curses/pdcurses-backend/pdckbd.c b/payloads/libpayload/curses/pdcurses-backend/pdckbd.c index 6b5b7ea..2d8a55b 100644 --- a/payloads/libpayload/curses/pdcurses-backend/pdckbd.c +++ b/payloads/libpayload/curses/pdcurses-backend/pdckbd.c @@ -5,7 +5,7 @@ unsigned long pdc_key_modifiers = 0L; -#if IS_ENABLED(CONFIG_LP_SERIAL_CONSOLE) +#if CONFIG(LP_SERIAL_CONSOLE) /* We treat serial like a vt100 terminal. For now we do the cooking in here, but we should probably eventually pass it to dedicated vt100 code */ @@ -108,7 +108,7 @@ bool PDC_check_key(void) { -#if IS_ENABLED(CONFIG_LP_USB_HID) +#if CONFIG(LP_USB_HID) usb_poll(); if ((curses_flags & F_ENABLE_CONSOLE) && usbhid_havechar()) { @@ -116,14 +116,14 @@ } #endif -#if IS_ENABLED(CONFIG_LP_PC_KEYBOARD) +#if CONFIG(LP_PC_KEYBOARD) if ((curses_flags & F_ENABLE_CONSOLE) && keyboard_havechar()) { return TRUE; } #endif -#if IS_ENABLED(CONFIG_LP_SERIAL_CONSOLE) +#if CONFIG(LP_SERIAL_CONSOLE) if ((curses_flags & F_ENABLE_SERIAL) && serial_havechar()) { return TRUE; @@ -139,7 +139,7 @@ { int c = 0; -#if IS_ENABLED(CONFIG_LP_USB_HID) +#if CONFIG(LP_USB_HID) usb_poll(); if ((curses_flags & F_ENABLE_CONSOLE) && usbhid_havechar()) { @@ -147,14 +147,14 @@ } #endif -#if IS_ENABLED(CONFIG_LP_PC_KEYBOARD) +#if CONFIG(LP_PC_KEYBOARD) if ((curses_flags & F_ENABLE_CONSOLE) && keyboard_havechar() && (c == 0)) { c = keyboard_getchar(); } #endif -#if IS_ENABLED(CONFIG_LP_SERIAL_CONSOLE) +#if CONFIG(LP_SERIAL_CONSOLE) if ((curses_flags & F_ENABLE_SERIAL) && serial_havechar() && (c == 0)) { c = cook_serial(serial_getchar()); diff --git a/payloads/libpayload/curses/pdcurses-backend/pdcscrn.c b/payloads/libpayload/curses/pdcurses-backend/pdcscrn.c index e33edc2..6286b7f 100644 --- a/payloads/libpayload/curses/pdcurses-backend/pdcscrn.c +++ b/payloads/libpayload/curses/pdcurses-backend/pdcscrn.c @@ -72,7 +72,7 @@ SP->lines = PDC_get_rows(); SP->cols = PDC_get_columns(); -#if IS_ENABLED(CONFIG_LP_SPEAKER) +#if CONFIG(LP_SPEAKER) SP->audible = TRUE; #endif diff --git a/payloads/libpayload/curses/pdcurses-backend/pdcsetsc.c b/payloads/libpayload/curses/pdcurses-backend/pdcsetsc.c index ba230c6..adcf069 100644 --- a/payloads/libpayload/curses/pdcurses-backend/pdcsetsc.c +++ b/payloads/libpayload/curses/pdcurses-backend/pdcsetsc.c @@ -13,12 +13,12 @@ ret_vis = SP->visibility; SP->visibility = visibility; -#if IS_ENABLED(CONFIG_LP_SERIAL_CONSOLE) +#if CONFIG(LP_SERIAL_CONSOLE) if (curses_flags & F_ENABLE_SERIAL) { serial_cursor_enable(visibility); } #endif -#if IS_ENABLED(CONFIG_LP_VIDEO_CONSOLE) +#if CONFIG(LP_VIDEO_CONSOLE) if (curses_flags & F_ENABLE_CONSOLE) { video_console_cursor_enable(visibility); } diff --git a/payloads/libpayload/curses/pdcurses-backend/pdcutil.c b/payloads/libpayload/curses/pdcurses-backend/pdcutil.c index d423f0c..f3f131f 100644 --- a/payloads/libpayload/curses/pdcurses-backend/pdcutil.c +++ b/payloads/libpayload/curses/pdcurses-backend/pdcutil.c @@ -11,7 +11,7 @@ { PDC_LOG(("PDC_beep() - called\n")); -#if IS_ENABLED(CONFIG_LP_SPEAKER) +#if CONFIG(LP_SPEAKER) speaker_tone(1760, 500); /* 1760 == note A6 */ #endif } diff --git a/payloads/libpayload/curses/tinycurses.c b/payloads/libpayload/curses/tinycurses.c index 789accb..c50f10b 100644 --- a/payloads/libpayload/curses/tinycurses.c +++ b/payloads/libpayload/curses/tinycurses.c @@ -111,8 +111,8 @@ '|', '<', '>', '*', '!', 'f', 'o', ' ', }; -#if IS_ENABLED(CONFIG_LP_SERIAL_CONSOLE) -#if IS_ENABLED(CONFIG_LP_SERIAL_ACS_FALLBACK) +#if CONFIG(LP_SERIAL_CONSOLE) +#if CONFIG(LP_SERIAL_ACS_FALLBACK) chtype serial_acs_map[128]; #else /* See acsc of vt100. */ @@ -138,7 +138,7 @@ #endif #endif -#if IS_ENABLED(CONFIG_LP_VIDEO_CONSOLE) +#if CONFIG(LP_VIDEO_CONSOLE) /* See acsc of linux. */ chtype console_acs_map[128] = { @@ -191,7 +191,7 @@ int beep(void) { /* TODO: Flash the screen if beeping fails? */ -#if IS_ENABLED(CONFIG_LP_SPEAKER) +#if CONFIG(LP_SPEAKER) speaker_tone(1760, 500); /* 1760 == note A6 */ #endif return OK; @@ -202,12 +202,12 @@ // int color_content(short color, short *r, short *g, short *b) {} int curs_set(int on) { -#if IS_ENABLED(CONFIG_LP_SERIAL_CONSOLE) +#if CONFIG(LP_SERIAL_CONSOLE) if (curses_flags & F_ENABLE_SERIAL) { serial_cursor_enable(on); } #endif -#if IS_ENABLED(CONFIG_LP_VIDEO_CONSOLE) +#if CONFIG(LP_VIDEO_CONSOLE) if (curses_flags & F_ENABLE_CONSOLE) { video_console_cursor_enable(on); } @@ -315,12 +315,12 @@ for (i = 0; i < 128; i++) acs_map[i] = (chtype) i | A_ALTCHARSET; -#if IS_ENABLED(CONFIG_LP_SERIAL_CONSOLE) +#if CONFIG(LP_SERIAL_CONSOLE) if (curses_flags & F_ENABLE_SERIAL) { serial_clear(); } #endif -#if IS_ENABLED(CONFIG_LP_VIDEO_CONSOLE) +#if CONFIG(LP_VIDEO_CONSOLE) if (curses_flags & F_ENABLE_CONSOLE) { /* Clear the screen and kill the cursor */ @@ -724,7 +724,7 @@ (((c) & 0x4400) >> 2) | ((c) & 0xAA00) | (((c) & 0x1100) << 2) int wnoutrefresh(WINDOW *win) { -#if IS_ENABLED(CONFIG_LP_SERIAL_CONSOLE) +#if CONFIG(LP_SERIAL_CONSOLE) // FIXME. int serial_is_bold = 0; int serial_is_reverse = 0; @@ -737,7 +737,7 @@ int x, y; chtype ch; -#if IS_ENABLED(CONFIG_LP_SERIAL_CONSOLE) +#if CONFIG(LP_SERIAL_CONSOLE) serial_end_bold(); serial_end_altcharset(); #endif @@ -749,7 +749,7 @@ /* Position the serial cursor */ -#if IS_ENABLED(CONFIG_LP_SERIAL_CONSOLE) +#if CONFIG(LP_SERIAL_CONSOLE) if (curses_flags & F_ENABLE_SERIAL) serial_set_cursor(win->_begy + y, win->_begx + win->_line[y].firstchar); @@ -758,7 +758,7 @@ for (x = win->_line[y].firstchar; x <= win->_line[y].lastchar; x++) { attr_t attr = win->_line[y].text[x].attr; -#if IS_ENABLED(CONFIG_LP_SERIAL_CONSOLE) +#if CONFIG(LP_SERIAL_CONSOLE) if (curses_flags & F_ENABLE_SERIAL) { ch = win->_line[y].text[x].chars[0]; @@ -824,7 +824,7 @@ } #endif -#if IS_ENABLED(CONFIG_LP_VIDEO_CONSOLE) +#if CONFIG(LP_VIDEO_CONSOLE) unsigned int c = ((int)color_pairs[PAIR_NUMBER(attr)]) << 8; @@ -865,12 +865,12 @@ win->_line[y].lastchar = _NOCHANGE; } -#if IS_ENABLED(CONFIG_LP_SERIAL_CONSOLE) +#if CONFIG(LP_SERIAL_CONSOLE) if (curses_flags & F_ENABLE_SERIAL) serial_set_cursor(win->_begy + win->_cury, win->_begx + win->_curx); #endif -#if IS_ENABLED(CONFIG_LP_VIDEO_CONSOLE) +#if CONFIG(LP_VIDEO_CONSOLE) if (curses_flags & F_ENABLE_CONSOLE) video_console_set_cursor(win->_begx + win->_curx, win->_begy + win->_cury); #endif diff --git a/payloads/libpayload/drivers/i8042/i8042.c b/payloads/libpayload/drivers/i8042/i8042.c index 4cdd0be..e97fab8 100644 --- a/payloads/libpayload/drivers/i8042/i8042.c +++ b/payloads/libpayload/drivers/i8042/i8042.c @@ -229,7 +229,7 @@ } /* Test secondary port */ - if (IS_ENABLED(CONFIG_LP_PC_MOUSE)) { + if (CONFIG(LP_PC_MOUSE)) { if (i8042_cmd_with_response(I8042_CMD_AUX_TEST) == 0) aux_fifo = fifo_init(4 * 32); } diff --git a/payloads/libpayload/drivers/i8042/keyboard.c b/payloads/libpayload/drivers/i8042/keyboard.c index a0d5b63..be22497 100644 --- a/payloads/libpayload/drivers/i8042/keyboard.c +++ b/payloads/libpayload/drivers/i8042/keyboard.c @@ -45,7 +45,7 @@ static int modifier = 0; static struct layout_maps keyboard_layouts[] = { -#if IS_ENABLED(CONFIG_LP_PC_KEYBOARD_LAYOUT_US) +#if CONFIG(LP_PC_KEYBOARD_LAYOUT_US) { .country = "us", .map = { { /* No modifier */ 0x00, 0x1B, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, @@ -101,7 +101,7 @@ } }}, #endif -#if IS_ENABLED(CONFIG_LP_PC_KEYBOARD_LAYOUT_DE) +#if CONFIG(LP_PC_KEYBOARD_LAYOUT_DE) { .country = "de", .map = { { /* No modifier */ 0x00, 0x1B, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, @@ -309,16 +309,16 @@ /* Set scancode set 1 */ ret = keyboard_cmd(I8042_KBCMD_SET_SCANCODE); - if (!ret && !IS_ENABLED(CONFIG_LP_PC_KEYBOARD_IGNORE_INIT_FAILURE)) + if (!ret && !CONFIG(LP_PC_KEYBOARD_IGNORE_INIT_FAILURE)) return; ret = keyboard_cmd(I8042_SCANCODE_SET_1); - if (!ret && !IS_ENABLED(CONFIG_LP_PC_KEYBOARD_IGNORE_INIT_FAILURE)) + if (!ret && !CONFIG(LP_PC_KEYBOARD_IGNORE_INIT_FAILURE)) return; /* Enable scanning */ ret = keyboard_cmd(I8042_KBCMD_EN); - if (!ret && !IS_ENABLED(CONFIG_LP_PC_KEYBOARD_IGNORE_INIT_FAILURE)) + if (!ret && !CONFIG(LP_PC_KEYBOARD_IGNORE_INIT_FAILURE)) return; console_add_input_driver(&cons); diff --git a/payloads/libpayload/drivers/mouse_cursor.c b/payloads/libpayload/drivers/mouse_cursor.c index 40c8934..7006b4d 100644 --- a/payloads/libpayload/drivers/mouse_cursor.c +++ b/payloads/libpayload/drivers/mouse_cursor.c @@ -60,7 +60,7 @@ /** Init enabled mouse cursor drivers */ void mouse_cursor_init(void) { -#if IS_ENABLED(CONFIG_LP_PC_MOUSE) +#if CONFIG(LP_PC_MOUSE) i8042_mouse_init(); #endif } diff --git a/payloads/libpayload/drivers/nvram.c b/payloads/libpayload/drivers/nvram.c index c825331..a116d1b 100644 --- a/payloads/libpayload/drivers/nvram.c +++ b/payloads/libpayload/drivers/nvram.c @@ -60,7 +60,7 @@ * doesn't try to do this on its own. */ #define RTC_PORT_STANDARD 0x70 -#if IS_ENABLED(CONFIG_LP_RTC_PORT_EXTENDED_VIA) +#if CONFIG(LP_RTC_PORT_EXTENDED_VIA) #define RTC_PORT_EXTENDED 0x74 #else #define RTC_PORT_EXTENDED 0x72 diff --git a/payloads/libpayload/drivers/serial/8250.c b/payloads/libpayload/drivers/serial/8250.c index 9327304..f503bdb 100644 --- a/payloads/libpayload/drivers/serial/8250.c +++ b/payloads/libpayload/drivers/serial/8250.c @@ -41,7 +41,7 @@ { offset *= lib_sysinfo.serial->regwidth; -#if IS_ENABLED(CONFIG_LP_IO_ADDRESS_SPACE) +#if CONFIG(LP_IO_ADDRESS_SPACE) if (!serial_is_mem_mapped) return inb(IOBASE + offset); else @@ -56,7 +56,7 @@ { offset *= lib_sysinfo.serial->regwidth; -#if IS_ENABLED(CONFIG_LP_IO_ADDRESS_SPACE) +#if CONFIG(LP_IO_ADDRESS_SPACE) if (!serial_is_mem_mapped) outb(val, IOBASE + offset); else @@ -67,13 +67,13 @@ writeb(val, MEMBASE + offset); } -#if IS_ENABLED(CONFIG_LP_SERIAL_SET_SPEED) +#if CONFIG(LP_SERIAL_SET_SPEED) static void serial_hardware_init(int speed, int word_bits, int parity, int stop_bits) { unsigned char reg; -#if !IS_ENABLED(CONFIG_LP_PL011_SERIAL_CONSOLE) +#if !CONFIG(LP_PL011_SERIAL_CONSOLE) /* Disable interrupts. */ serial_write_reg(0, 0x01); @@ -114,7 +114,7 @@ (lib_sysinfo.serial->type == CB_SERIAL_TYPE_MEMORY_MAPPED); if (!serial_is_mem_mapped) { -#if IS_ENABLED(CONFIG_LP_IO_ADDRESS_SPACE) +#if CONFIG(LP_IO_ADDRESS_SPACE) if ((inb(IOBASE + 0x05) == 0xFF) && (inb(IOBASE + 0x06) == 0xFF)) { printf("IO space mapped serial not present."); @@ -126,7 +126,7 @@ #endif } -#if IS_ENABLED(CONFIG_LP_SERIAL_SET_SPEED) +#if CONFIG(LP_SERIAL_SET_SPEED) serial_hardware_init(CONFIG_LP_SERIAL_BAUD_RATE, 8, 0, 1); #endif } @@ -147,7 +147,7 @@ { if (!serial_hardware_is_present) return; -#if !IS_ENABLED(CONFIG_LP_PL011_SERIAL_CONSOLE) +#if !CONFIG(LP_PL011_SERIAL_CONSOLE) while ((serial_read_reg(0x05) & 0x20) == 0) ; #endif serial_write_reg(c, 0x00); diff --git a/payloads/libpayload/drivers/storage/ahci.c b/payloads/libpayload/drivers/storage/ahci.c index bb0d37e..fbfcf97 100644 --- a/payloads/libpayload/drivers/storage/ahci.c +++ b/payloads/libpayload/drivers/storage/ahci.c @@ -153,7 +153,7 @@ switch (port->signature) { case HBA_PxSIG_ATA: printf("ahci: ATA drive on port #%d.\n", portnum); -#if IS_ENABLED(CONFIG_LP_STORAGE_ATA) +#if CONFIG(LP_STORAGE_ATA) dev->ata_dev.identify = ahci_identify_device; dev->ata_dev.read_sectors = ahci_ata_read_sectors; return ata_attach_device(&dev->ata_dev, PORT_TYPE_SATA); @@ -161,7 +161,7 @@ break; case HBA_PxSIG_ATAPI: printf("ahci: ATAPI drive on port #%d.\n", portnum); -#if IS_ENABLED(CONFIG_LP_STORAGE_ATAPI) +#if CONFIG(LP_STORAGE_ATAPI) dev->atapi_dev.identify = ahci_identify_device; dev->atapi_dev.packet_read_cmd = ahci_packet_read_cmd; return atapi_attach_device(&dev->atapi_dev, PORT_TYPE_SATA); @@ -218,7 +218,7 @@ ahci_dev_init(ctrl, port, portnum); } -#if IS_ENABLED(CONFIG_LP_STORAGE_AHCI_ONLY_TESTED) +#if CONFIG(LP_STORAGE_AHCI_ONLY_TESTED) static u32 working_controllers[] = { 0x8086 | 0x2929 << 16, /* Mobile ICH9 */ 0x8086 | 0x1c03 << 16, /* Mobile Cougar Point PCH */ @@ -236,7 +236,7 @@ const u16 vendor = pci_read_config16(dev, 0x00); const u16 device = pci_read_config16(dev, 0x02); -#if IS_ENABLED(CONFIG_LP_STORAGE_AHCI_ONLY_TESTED) +#if CONFIG(LP_STORAGE_AHCI_ONLY_TESTED) const u32 vendor_device = pci_read_config32(dev, 0x0); for (i = 0; i < ARRAY_SIZE(working_controllers); ++i) if (vendor_device == working_controllers[i]) diff --git a/payloads/libpayload/drivers/storage/ahci_ata.c b/payloads/libpayload/drivers/storage/ahci_ata.c index 2c916fd..94c13e0 100644 --- a/payloads/libpayload/drivers/storage/ahci_ata.c +++ b/payloads/libpayload/drivers/storage/ahci_ata.c @@ -56,7 +56,7 @@ printf("ahci: Sector count too high (max. 256).\n"); count = 256; } -#if IS_ENABLED(CONFIG_LP_STORAGE_64BIT_LBA) +#if CONFIG(LP_STORAGE_64BIT_LBA) } else if (ata_dev->read_cmd == ATA_READ_DMA_EXT) { if (start >= (1ULL << 48)) { printf("ahci: Sector is not 48-bit addressable.\n"); @@ -84,7 +84,7 @@ dev->cmdtable->fis[ 6] = (start >> 16) & 0xff; dev->cmdtable->fis[ 7] = FIS_H2D_DEV_LBA; dev->cmdtable->fis[ 8] = (start >> 24) & 0xff; -#if IS_ENABLED(CONFIG_LP_STORAGE_64BIT_LBA) +#if CONFIG(LP_STORAGE_64BIT_LBA) if (ata_dev->read_cmd == ATA_READ_DMA_EXT) { dev->cmdtable->fis[ 9] = (start >> 32) & 0xff; dev->cmdtable->fis[10] = (start >> 40) & 0xff; diff --git a/payloads/libpayload/drivers/storage/ata.c b/payloads/libpayload/drivers/storage/ata.c index 80178c3..91ddf59 100644 --- a/payloads/libpayload/drivers/storage/ata.c +++ b/payloads/libpayload/drivers/storage/ata.c @@ -212,7 +212,7 @@ ata_strncpy(model, id + 27, sizeof(model)); printf("ata: Identified %s [%s]\n", model, fw); -#if IS_ENABLED(CONFIG_LP_STORAGE_64BIT_LBA) +#if CONFIG(LP_STORAGE_64BIT_LBA) if (id[ATA_CMDS_AND_FEATURE_SETS + 1] & (1 << 10)) { printf("ata: Support for LBA-48 enabled.\n"); dev->read_cmd = ATA_READ_DMA_EXT; diff --git a/payloads/libpayload/drivers/storage/storage.c b/payloads/libpayload/drivers/storage/storage.c index c4cfd40..a7141ee 100644 --- a/payloads/libpayload/drivers/storage/storage.c +++ b/payloads/libpayload/drivers/storage/storage.c @@ -28,7 +28,7 @@ */ #include <libpayload.h> -#if IS_ENABLED(CONFIG_LP_STORAGE_AHCI) +#if CONFIG(LP_STORAGE_AHCI) # include <storage/ahci.h> #endif #include <storage/storage.h> @@ -110,7 +110,7 @@ */ void storage_initialize(void) { -#if IS_ENABLED(CONFIG_LP_STORAGE_AHCI) +#if CONFIG(LP_STORAGE_AHCI) ahci_initialize(); #endif } diff --git a/payloads/libpayload/drivers/usb/ehci.c b/payloads/libpayload/drivers/usb/ehci.c index eb59d97..30cf191 100644 --- a/payloads/libpayload/drivers/usb/ehci.c +++ b/payloads/libpayload/drivers/usb/ehci.c @@ -850,7 +850,7 @@ return controller; } -#if IS_ENABLED(CONFIG_LP_USB_PCI) +#if CONFIG(LP_USB_PCI) hci_t * ehci_pci_init (pcidev_t addr) { diff --git a/payloads/libpayload/drivers/usb/ehci_rh.c b/payloads/libpayload/drivers/usb/ehci_rh.c index da8d8af..d3fc979 100644 --- a/payloads/libpayload/drivers/usb/ehci_rh.c +++ b/payloads/libpayload/drivers/usb/ehci_rh.c @@ -102,7 +102,7 @@ /* device connected, handle */ if (RH_INST(dev)->ports[port] & P_CURR_CONN_STATUS) { mdelay(100); // usb20 spec 9.1.2 - if (!IS_ENABLED(CONFIG_LP_USB_EHCI_HOSTPC_ROOT_HUB_TT) && + if (!CONFIG(LP_USB_EHCI_HOSTPC_ROOT_HUB_TT) && (RH_INST(dev)->ports[port] & P_LINE_STATUS) == P_LINE_STATUS_LOWSPEED) { ehci_rh_hand_over_port(dev, port); @@ -138,7 +138,7 @@ ehci_rh_hand_over_port(dev, port); return; } - if (IS_ENABLED(CONFIG_LP_USB_EHCI_HOSTPC_ROOT_HUB_TT)) { + if (CONFIG(LP_USB_EHCI_HOSTPC_ROOT_HUB_TT)) { port_speed = (usb_speed) ((EHCI_INST(dev->controller)->operation->hostpc >> 25) & 0x03); diff --git a/payloads/libpayload/drivers/usb/ohci.c b/payloads/libpayload/drivers/usb/ohci.c index dcf7169..1964689 100644 --- a/payloads/libpayload/drivers/usb/ohci.c +++ b/payloads/libpayload/drivers/usb/ohci.c @@ -247,7 +247,7 @@ return controller; } -#if IS_ENABLED(CONFIG_LP_USB_PCI) +#if CONFIG(LP_USB_PCI) hci_t * ohci_pci_init (pcidev_t addr) { diff --git a/payloads/libpayload/drivers/usb/usb.c b/payloads/libpayload/drivers/usb/usb.c index 62604a2..9c9854d 100644 --- a/payloads/libpayload/drivers/usb/usb.c +++ b/payloads/libpayload/drivers/usb/usb.c @@ -563,7 +563,7 @@ break; case hid_device: usb_debug ("HID\n"); -#if IS_ENABLED(CONFIG_LP_USB_HID) +#if CONFIG(LP_USB_HID) dev->init = usb_hid_init; return dev->address; #else @@ -581,7 +581,7 @@ break; case msc_device: usb_debug ("MSC\n"); -#if IS_ENABLED(CONFIG_LP_USB_MSC) +#if CONFIG(LP_USB_MSC) dev->init = usb_msc_init; return dev->address; #else @@ -590,7 +590,7 @@ break; case hub_device: usb_debug ("hub\n"); -#if IS_ENABLED(CONFIG_LP_USB_HUB) +#if CONFIG(LP_USB_HUB) dev->init = usb_hub_init; return dev->address; #else diff --git a/payloads/libpayload/drivers/usb/usbhid.c b/payloads/libpayload/drivers/usb/usbhid.c index 22ed8e7..072530c 100644 --- a/payloads/libpayload/drivers/usb/usbhid.c +++ b/payloads/libpayload/drivers/usb/usbhid.c @@ -142,7 +142,7 @@ static const struct layout_maps *map; static const struct layout_maps keyboard_layouts[] = { -// #if IS_ENABLED(CONFIG_LP_PC_KEYBOARD_LAYOUT_US) +// #if CONFIG(LP_PC_KEYBOARD_LAYOUT_US) { .country = "us", .map = { { /* No modifier */ -1, -1, -1, -1, 'a', 'b', 'c', 'd', diff --git a/payloads/libpayload/drivers/usb/usbinit.c b/payloads/libpayload/drivers/usb/usbinit.c index 721fde8..0ac27e4 100644 --- a/payloads/libpayload/drivers/usb/usbinit.c +++ b/payloads/libpayload/drivers/usb/usbinit.c @@ -37,7 +37,7 @@ #include "dwc2.h" #include <usb/usbdisk.h> -#if IS_ENABLED(CONFIG_LP_USB_PCI) +#if CONFIG(LP_USB_PCI) /** * Initializes USB controller attached to PCI * @@ -72,7 +72,7 @@ pciid >> 16, pciid & 0xFFFF, func); switch (prog_if) { case 0x00: -#if IS_ENABLED(CONFIG_LP_USB_UHCI) +#if CONFIG(LP_USB_UHCI) usb_debug("UHCI controller\n"); uhci_pci_init (pci_device); #else @@ -81,7 +81,7 @@ break; case 0x10: -#if IS_ENABLED(CONFIG_LP_USB_OHCI) +#if CONFIG(LP_USB_OHCI) usb_debug("OHCI controller\n"); ohci_pci_init(pci_device); #else @@ -90,7 +90,7 @@ break; case 0x20: -#if IS_ENABLED(CONFIG_LP_USB_EHCI) +#if CONFIG(LP_USB_EHCI) usb_debug("EHCI controller\n"); ehci_pci_init(pci_device); #else @@ -99,7 +99,7 @@ break; case 0x30: -#if IS_ENABLED(CONFIG_LP_USB_XHCI) +#if CONFIG(LP_USB_XHCI) usb_debug("xHCI controller\n"); xhci_pci_init(pci_device); #else @@ -166,7 +166,7 @@ */ int usb_initialize(void) { -#if IS_ENABLED(CONFIG_LP_USB_PCI) +#if CONFIG(LP_USB_PCI) usb_scan_pci_bus(0); #endif return 0; @@ -175,19 +175,19 @@ hci_t *usb_add_mmio_hc(hc_type type, void *bar) { switch (type) { -#if IS_ENABLED(CONFIG_LP_USB_OHCI) +#if CONFIG(LP_USB_OHCI) case OHCI: return ohci_init((unsigned long)bar); #endif -#if IS_ENABLED(CONFIG_LP_USB_EHCI) +#if CONFIG(LP_USB_EHCI) case EHCI: return ehci_init((unsigned long)bar); #endif -#if IS_ENABLED(CONFIG_LP_USB_DWC2) +#if CONFIG(LP_USB_DWC2) case DWC2: return dwc2_init(bar); #endif -#if IS_ENABLED(CONFIG_LP_USB_XHCI) +#if CONFIG(LP_USB_XHCI) case XHCI: return xhci_init((unsigned long)bar); #endif diff --git a/payloads/libpayload/drivers/usb/xhci.c b/payloads/libpayload/drivers/usb/xhci.c index 3f1064a..0a69c51 100644 --- a/payloads/libpayload/drivers/usb/xhci.c +++ b/payloads/libpayload/drivers/usb/xhci.c @@ -88,7 +88,7 @@ } /* On Panther Point: switch ports shared with EHCI to xHCI */ -#if IS_ENABLED(CONFIG_LP_USB_PCI) +#if CONFIG(LP_USB_PCI) static void xhci_switch_ppt_ports(pcidev_t addr) { @@ -112,7 +112,7 @@ } #endif -#if IS_ENABLED(CONFIG_LP_USB_PCI) +#if CONFIG(LP_USB_PCI) /* On Panther Point: switch all ports back to EHCI */ static void xhci_switchback_ppt_ports(pcidev_t addr) @@ -297,7 +297,7 @@ return NULL; } -#if IS_ENABLED(CONFIG_LP_USB_PCI) +#if CONFIG(LP_USB_PCI) hci_t * xhci_pci_init (pcidev_t addr) { @@ -336,7 +336,7 @@ * Without this delay, the subsequent HC register access, * may result in a system hang very rarely. */ - if (IS_ENABLED(CONFIG_LP_ARCH_X86)) + if (CONFIG(LP_ARCH_X86)) mdelay(1); xhci_debug("Resetting controller... "); @@ -426,7 +426,7 @@ xhci_t *const xhci = XHCI_INST(controller); xhci_stop(controller); -#if IS_ENABLED(CONFIG_LP_USB_PCI) +#if CONFIG(LP_USB_PCI) if (controller->pcidev) xhci_switchback_ppt_ports(controller->pcidev); #endif @@ -563,7 +563,7 @@ cur_length = length; packets = 0; length = 0; - } else if (!IS_ENABLED(CONFIG_LP_USB_XHCI_MTK_QUIRK)) { + } else if (!CONFIG(LP_USB_XHCI_MTK_QUIRK)) { packets -= (residue + cur_length) / mps; residue = (residue + cur_length) % mps; length -= cur_length; @@ -576,7 +576,7 @@ TRB_SET(TDS, trb, MIN(TRB_MAX_TD_SIZE, packets)); TRB_SET(CH, trb, 1); - if (length && IS_ENABLED(CONFIG_LP_USB_XHCI_MTK_QUIRK)) { + if (length && CONFIG(LP_USB_XHCI_MTK_QUIRK)) { /* * For MTK's xHCI controller, TDS defines a number of * packets that remain to be transferred for a TD after diff --git a/payloads/libpayload/drivers/usb/xhci_devconf.c b/payloads/libpayload/drivers/usb/xhci_devconf.c index b697b0f..99e3037 100644 --- a/payloads/libpayload/drivers/usb/xhci_devconf.c +++ b/payloads/libpayload/drivers/usb/xhci_devconf.c @@ -353,7 +353,7 @@ EC_SET(AVRTRB, epctx, avrtrb); EC_SET(MXESIT, epctx, EC_GET(MPS, epctx) * EC_GET(MBS, epctx)); - if (IS_ENABLED(CONFIG_LP_USB_XHCI_MTK_QUIRK)) { + if (CONFIG(LP_USB_XHCI_MTK_QUIRK)) { /* The MTK xHCI defines some extra SW parameters which are * put into reserved DWs in Slot and Endpoint Contexts for * synchronous endpoints. But for non-isochronous transfers, diff --git a/payloads/libpayload/drivers/usb/xhci_rh.c b/payloads/libpayload/drivers/usb/xhci_rh.c index ddf6ce8..453fa5b 100644 --- a/payloads/libpayload/drivers/usb/xhci_rh.c +++ b/payloads/libpayload/drivers/usb/xhci_rh.c @@ -122,7 +122,7 @@ static int xhci_rh_enable_port(usbdev_t *const dev, int port) { - if (IS_ENABLED(CONFIG_LP_USB_XHCI_MTK_QUIRK)) { + if (CONFIG(LP_USB_XHCI_MTK_QUIRK)) { xhci_t *const xhci = XHCI_INST(dev->controller); volatile u32 *const portsc = &xhci->opreg->prs[port - 1].portsc; diff --git a/payloads/libpayload/drivers/video/video.c b/payloads/libpayload/drivers/video/video.c index b932a63..9ab7ba2 100644 --- a/payloads/libpayload/drivers/video/video.c +++ b/payloads/libpayload/drivers/video/video.c @@ -31,27 +31,27 @@ #include <libpayload.h> #include <video_console.h> -#if IS_ENABLED(CONFIG_LP_GEODELX_VIDEO_CONSOLE) +#if CONFIG(LP_GEODELX_VIDEO_CONSOLE) extern struct video_console geodelx_video_console; #endif -#if IS_ENABLED(CONFIG_LP_COREBOOT_VIDEO_CONSOLE) +#if CONFIG(LP_COREBOOT_VIDEO_CONSOLE) extern struct video_console coreboot_video_console; #endif -#if IS_ENABLED(CONFIG_LP_VGA_VIDEO_CONSOLE) +#if CONFIG(LP_VGA_VIDEO_CONSOLE) extern struct video_console vga_video_console; #endif static struct video_console *console_list[] = { -#if IS_ENABLED(CONFIG_LP_GEODELX_VIDEO_CONSOLE) +#if CONFIG(LP_GEODELX_VIDEO_CONSOLE) &geodelx_video_console, #endif -#if IS_ENABLED(CONFIG_LP_COREBOOT_VIDEO_CONSOLE) +#if CONFIG(LP_COREBOOT_VIDEO_CONSOLE) &coreboot_video_console, #endif -#if IS_ENABLED(CONFIG_LP_VGA_VIDEO_CONSOLE) +#if CONFIG(LP_VGA_VIDEO_CONSOLE) &vga_video_console, #endif }; diff --git a/payloads/libpayload/include/endian.h b/payloads/libpayload/include/endian.h index 2dcfa1f..b387e66 100644 --- a/payloads/libpayload/include/endian.h +++ b/payloads/libpayload/include/endian.h @@ -53,7 +53,7 @@ /* Endian functions from glibc 2.9 / BSD "endian.h" */ -#if IS_ENABLED(CONFIG_LP_BIG_ENDIAN) +#if CONFIG(LP_BIG_ENDIAN) #define htobe16(in) (in) #define htobe32(in) (in) @@ -63,7 +63,7 @@ #define htole32(in) swap_bytes32(in) #define htole64(in) swap_bytes64(in) -#elif IS_ENABLED(CONFIG_LP_LITTLE_ENDIAN) +#elif CONFIG(LP_LITTLE_ENDIAN) #define htobe16(in) swap_bytes16(in) #define htobe32(in) swap_bytes32(in) diff --git a/payloads/libpayload/include/stdlib.h b/payloads/libpayload/include/stdlib.h index a2e612d..aaacc87 100644 --- a/payloads/libpayload/include/stdlib.h +++ b/payloads/libpayload/include/stdlib.h @@ -45,7 +45,7 @@ * @defgroup malloc Memory allocation functions * @{ */ -#if IS_ENABLED(CONFIG_LP_DEBUG_MALLOC) && !defined(IN_MALLOC_C) +#if CONFIG(LP_DEBUG_MALLOC) && !defined(IN_MALLOC_C) #define free(p) \ ({ \ extern void print_malloc_map(void); \ @@ -222,7 +222,7 @@ void halt(void) __attribute__((noreturn)); void exit(int status) __attribute__((noreturn)); #define abort() halt() /**< Alias for the halt() function */ -#if IS_ENABLED(CONFIG_LP_REMOTEGDB) +#if CONFIG(LP_REMOTEGDB) /* Override abort()/halt() to trap into GDB if it is enabled. */ #define halt() do { gdb_enter(); halt(); } while (0) #endif diff --git a/payloads/libpayload/include/storage/storage.h b/payloads/libpayload/include/storage/storage.h index f2e6f29..2dc70b0 100644 --- a/payloads/libpayload/include/storage/storage.h +++ b/payloads/libpayload/include/storage/storage.h @@ -34,7 +34,7 @@ #include <unistd.h> -#if !IS_ENABLED(CONFIG_LP_STORAGE_64BIT_LBA) +#if !CONFIG(LP_STORAGE_64BIT_LBA) typedef u32 lba_t; #else typedef u64 lba_t; diff --git a/payloads/libpayload/include/sysinfo.h b/payloads/libpayload/include/sysinfo.h index bd64cdb..845b7c4 100644 --- a/payloads/libpayload/include/sysinfo.h +++ b/payloads/libpayload/include/sysinfo.h @@ -98,7 +98,7 @@ void *vboot_handoff; u32 vboot_handoff_size; -#if IS_ENABLED(CONFIG_LP_ARCH_X86) +#if CONFIG(LP_ARCH_X86) int x86_rom_var_mtrr_index; #endif diff --git a/payloads/libpayload/libc/64bit_div.c b/payloads/libpayload/libc/64bit_div.c index 877cef2..5cd5bc5 100644 --- a/payloads/libpayload/libc/64bit_div.c +++ b/payloads/libpayload/libc/64bit_div.c @@ -30,7 +30,7 @@ #include <libpayload-config.h> #include <stdlib.h> -#if !IS_ENABLED(CONFIG_LP_LITTLE_ENDIAN) +#if !CONFIG(LP_LITTLE_ENDIAN) #error this code is for little endian only #endif diff --git a/payloads/libpayload/libc/console.c b/payloads/libpayload/libc/console.c index b57fc47..8d7d62d 100644 --- a/payloads/libpayload/libc/console.c +++ b/payloads/libpayload/libc/console.c @@ -102,16 +102,16 @@ void console_init(void) { -#if IS_ENABLED(CONFIG_LP_VIDEO_CONSOLE) +#if CONFIG(LP_VIDEO_CONSOLE) video_console_init(); #endif -#if IS_ENABLED(CONFIG_LP_SERIAL_CONSOLE) +#if CONFIG(LP_SERIAL_CONSOLE) serial_console_init(); #endif -#if IS_ENABLED(CONFIG_LP_PC_KEYBOARD) +#if CONFIG(LP_PC_KEYBOARD) keyboard_init(); #endif -#if IS_ENABLED(CONFIG_LP_CBMEM_CONSOLE) +#if CONFIG(LP_CBMEM_CONSOLE) cbmem_console_init(); #endif } @@ -147,7 +147,7 @@ int havekey(void) { -#if IS_ENABLED(CONFIG_LP_USB) +#if CONFIG(LP_USB) usb_poll(); #endif struct console_input_driver *in; @@ -164,7 +164,7 @@ int getchar(void) { while (1) { -#if IS_ENABLED(CONFIG_LP_USB) +#if CONFIG(LP_USB) usb_poll(); #endif struct console_input_driver *in; diff --git a/payloads/libpayload/libc/coreboot.c b/payloads/libpayload/libc/coreboot.c index 2189161..ba5bb27 100644 --- a/payloads/libpayload/libc/coreboot.c +++ b/payloads/libpayload/libc/coreboot.c @@ -56,7 +56,7 @@ for (i = 0; i < count; i++) { struct cb_memory_range *range = MEM_RANGE_PTR(mem, i); -#if IS_ENABLED(CONFIG_LP_MEMMAP_RAM_ONLY) +#if CONFIG(LP_MEMMAP_RAM_ONLY) if (range->type != CB_MEM_RAM) continue; #endif @@ -155,7 +155,7 @@ info->sku_id = sku_id->id_code; } -#if IS_ENABLED(CONFIG_LP_NVRAM) +#if CONFIG(LP_NVRAM) static void cb_parse_optiontable(void *ptr, struct sysinfo_t *info) { /* ptr points to a coreboot table entry and is already virtual */ @@ -171,7 +171,7 @@ } #endif -#if IS_ENABLED(CONFIG_LP_COREBOOT_VIDEO_CONSOLE) +#if CONFIG(LP_COREBOOT_VIDEO_CONSOLE) static void cb_parse_framebuffer(void *ptr, struct sysinfo_t *info) { /* ptr points to a coreboot table entry and is already virtual */ @@ -232,7 +232,7 @@ info->chromeos_vpd = phys_to_virt(cbmem->cbmem_tab); } -#if IS_ENABLED(CONFIG_LP_TIMER_RDTSC) +#if CONFIG(LP_TIMER_RDTSC) static void cb_parse_tsc_info(void *ptr, struct sysinfo_t *info) { const struct cb_tsc_info *tsc_info = ptr; @@ -328,7 +328,7 @@ case CB_TAG_ASSEMBLER: cb_parse_string(ptr, &info->assembler); break; -#if IS_ENABLED(CONFIG_LP_NVRAM) +#if CONFIG(LP_NVRAM) case CB_TAG_CMOS_OPTION_TABLE: cb_parse_optiontable(ptr, info); break; @@ -336,7 +336,7 @@ cb_parse_checksum(ptr, info); break; #endif -#if IS_ENABLED(CONFIG_LP_COREBOOT_VIDEO_CONSOLE) +#if CONFIG(LP_COREBOOT_VIDEO_CONSOLE) // FIXME we should warn on serial if coreboot set up a // framebuffer buf the payload does not know about it. case CB_TAG_FRAMEBUFFER: @@ -394,7 +394,7 @@ case CB_TAG_BOOT_MEDIA_PARAMS: cb_parse_boot_media_params(ptr, info); break; -#if IS_ENABLED(CONFIG_LP_TIMER_RDTSC) +#if CONFIG(LP_TIMER_RDTSC) case CB_TAG_TSC_INFO: cb_parse_tsc_info(ptr, info); break; diff --git a/payloads/libpayload/libc/exec.c b/payloads/libpayload/libc/exec.c index d48d213..533600d 100644 --- a/payloads/libpayload/libc/exec.c +++ b/payloads/libpayload/libc/exec.c @@ -30,7 +30,7 @@ #include <libpayload-config.h> #include <libpayload.h> -#if IS_ENABLED(CONFIG_LP_ARCH_X86) +#if CONFIG(LP_ARCH_X86) extern void i386_do_exec(long addr, int argc, char **argv, int *ret); #endif @@ -46,7 +46,7 @@ { int val = -1; -#if IS_ENABLED(CONFIG_LP_ARCH_X86) +#if CONFIG(LP_ARCH_X86) i386_do_exec(addr, argc, argv, &val); #endif return val; diff --git a/payloads/libpayload/libc/malloc.c b/payloads/libpayload/libc/malloc.c index 595af63..957f0e0 100644 --- a/payloads/libpayload/libc/malloc.c +++ b/payloads/libpayload/libc/malloc.c @@ -47,7 +47,7 @@ void *start; void *end; struct align_region_t* align_regions; -#if IS_ENABLED(CONFIG_LP_DEBUG_MALLOC) +#if CONFIG(LP_DEBUG_MALLOC) int magic_initialized; size_t minimal_free; const char *name; @@ -58,7 +58,7 @@ static struct memory_type default_type = { (void *)&_heap, (void *)&_eheap, NULL -#if IS_ENABLED(CONFIG_LP_DEBUG_MALLOC) +#if CONFIG(LP_DEBUG_MALLOC) , 0, 0, "HEAP" #endif }; @@ -104,7 +104,7 @@ dma->end = start + size; dma->align_regions = NULL; -#if IS_ENABLED(CONFIG_LP_DEBUG_MALLOC) +#if CONFIG(LP_DEBUG_MALLOC) dma->minimal_free = 0; dma->magic_initialized = 0; dma->name = "DMA"; @@ -139,7 +139,7 @@ if (!HAS_MAGIC(*ptr)) { size_t size = (type->end - type->start) - HDRSIZE; *ptr = FREE_BLOCK(size); -#if IS_ENABLED(CONFIG_LP_DEBUG_MALLOC) +#if CONFIG(LP_DEBUG_MALLOC) type->magic_initialized = 1; type->minimal_free = size; #endif @@ -356,7 +356,7 @@ struct align_region_t *r; size_t extra_space; -#if IS_ENABLED(CONFIG_LP_DEBUG_MALLOC) +#if CONFIG(LP_DEBUG_MALLOC) printf("%s(old align_regions=%p, alignment=%u, num_elements=%u, size=%zu)\n", __func__, type->align_regions, alignment, num_elements, size); #endif @@ -479,7 +479,7 @@ { if ((reg->alignment == align) && (reg->free >= (size + align - 1)/align)) { -#if IS_ENABLED(CONFIG_LP_DEBUG_MALLOC) +#if CONFIG(LP_DEBUG_MALLOC) printf(" found memalign region. %x free, %x required\n", reg->free, (size + align - 1)/align); #endif break; @@ -488,12 +488,12 @@ } if (reg == 0) { -#if IS_ENABLED(CONFIG_LP_DEBUG_MALLOC) +#if CONFIG(LP_DEBUG_MALLOC) printf(" need to allocate a new memalign region\n"); #endif /* get align regions */ reg = allocate_region(align, large_request/align, size, type); -#if IS_ENABLED(CONFIG_LP_DEBUG_MALLOC) +#if CONFIG(LP_DEBUG_MALLOC) printf(" ... returned %p\n", reg); #endif } @@ -539,7 +539,7 @@ } /* This is for debugging purposes. */ -#if IS_ENABLED(CONFIG_LP_DEBUG_MALLOC) +#if CONFIG(LP_DEBUG_MALLOC) void print_malloc_map(void) { struct memory_type *type = heap; diff --git a/payloads/libpayload/libc/time.c b/payloads/libpayload/libc/time.c index f891346..7583448 100644 --- a/payloads/libpayload/libc/time.c +++ b/payloads/libpayload/libc/time.c @@ -34,7 +34,7 @@ #include <libpayload-config.h> #include <libpayload.h> -#if IS_ENABLED(CONFIG_LP_ARCH_X86) && IS_ENABLED(CONFIG_LP_NVRAM) +#if CONFIG(LP_ARCH_X86) && CONFIG(LP_NVRAM) #include <arch/rdtsc.h> #endif @@ -70,7 +70,7 @@ } } -#if IS_ENABLED(CONFIG_LP_NVRAM) +#if CONFIG(LP_NVRAM) static unsigned int day_of_year(int mon, int day, int year) { diff --git a/payloads/libpayload/libcbfs/cbfs.c b/payloads/libpayload/libcbfs/cbfs.c index d679e67..d2d13ea 100644 --- a/payloads/libpayload/libcbfs/cbfs.c +++ b/payloads/libpayload/libcbfs/cbfs.c @@ -31,11 +31,11 @@ #ifdef LIBPAYLOAD # include <libpayload-config.h> -# if IS_ENABLED(CONFIG_LP_LZMA) +# if CONFIG(LP_LZMA) # include <lzma.h> # define CBFS_CORE_WITH_LZMA # endif -# if IS_ENABLED(CONFIG_LP_LZ4) +# if CONFIG(LP_LZ4) # include <lz4.h> # define CBFS_CORE_WITH_LZ4 # endif diff --git a/payloads/libpayload/libcbfs/cbfs_core.c b/payloads/libpayload/libcbfs/cbfs_core.c index 39bbdb5..e94e1e7 100644 --- a/payloads/libpayload/libcbfs/cbfs_core.c +++ b/payloads/libpayload/libcbfs/cbfs_core.c @@ -119,7 +119,7 @@ // Logical offset (for source media) of first file. *offset = ntohl(header->offset); *cbfs_end = ntohl(header->romsize); -#if IS_ENABLED(CONFIG_LP_ARCH_X86) +#if CONFIG(LP_ARCH_X86) // resolve actual length of ROM used for CBFS components // the bootblock size was not taken into account *cbfs_end -= ntohl(header->bootblocksize); diff --git a/payloads/nvramcui/nvramcui.c b/payloads/nvramcui/nvramcui.c index 675e002..453b9aa 100644 --- a/payloads/nvramcui/nvramcui.c +++ b/payloads/nvramcui/nvramcui.c @@ -176,7 +176,7 @@ int ch, done; int i; - if (IS_ENABLED(CONFIG_LP_USB)) + if (CONFIG(LP_USB)) usb_initialize(); /* coreboot data structures */ -- To view, visit https://review.coreboot.org/c/coreboot/+/31775 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I883b03b189f59b5d998a09a2596b0391a2d5cf33 Gerrit-Change-Number: 31775 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: [WIP] Nvidia Optimus support for ThinkPads
by Patrick Rudolph (Code Review) 06 Apr '19

06 Apr '19

Patrick Rudolph has uploaded a new patch set (#10) to the change originally created by Evgeny Zinoviev. ( https://review.coreboot.org/c/coreboot/+/28380 ) Change subject: [WIP] Nvidia Optimus support for ThinkPads ...................................................................... [WIP] Nvidia Optimus support for ThinkPads Based on siro's work #23041. Tested on ThinkPad W530 and Thinkpad T520. Adds ACPI code for dGPU power management. Depends on: https://review.coreboot.org/#/c/coreboot/+/28392 https://review.coreboot.org/#/c/coreboot/+/28393 What works (tested on 4.16.13-gentoo kernel): - power management via _PS0 and _DSM + _PS3 ACPI calls - nouveau driver - bumblebee (from the "develop" branch) - bbswitch - VGA ROM loading lspci turns on the dGPU, but that is expected, as otherwise it can't access the device's address space. The Nvidia Optimus driver needs to be enabled by setting CONFIG_NVIDIA_OPTIMUS=y Known problems: - nvidia driver doens't work: [ 275.244113] NVRM: failed to copy vbios to system memory. [ 275.244345] NVRM: RmInitAdapter failed! (0x30:0xffff:663) [ 275.244433] NVRM: rm_init_adapter failed for device bearing minor number 0 [ 275.347956] NVRM: failed to copy vbios to system memory. [ 275.348140] NVRM: RmInitAdapter failed! (0x30:0xffff:663) [ 275.348163] NVRM: rm_init_adapter failed for device bearing minor number 0 - Random CPU core lockups Change-Id: I277808d6c1d8bd6e0a267a53f25471597698f8d5 Signed-off-by: Evgeny Zinoviev <me(a)ch1p.com> Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- A src/drivers/nvidia/optimus/acpi/optimus.asl A src/ec/lenovo/pmh7/acpi/optimus_sandy_ivy.asl A src/ec/lenovo/pmh7/acpi/pmh7.asl M src/ec/lenovo/pmh7/pmh7.h M src/mainboard/lenovo/t420/Kconfig M src/mainboard/lenovo/t420/acpi/ec.asl M src/mainboard/lenovo/t420s/Kconfig M src/mainboard/lenovo/t420s/acpi/ec.asl M src/mainboard/lenovo/t430/Kconfig M src/mainboard/lenovo/t430/acpi/ec.asl M src/mainboard/lenovo/t430s/Kconfig M src/mainboard/lenovo/t430s/acpi/ec.asl M src/mainboard/lenovo/t520/Kconfig M src/mainboard/lenovo/t520/acpi/ec.asl M src/mainboard/lenovo/t520/cmos.default M src/mainboard/lenovo/t530/Kconfig M src/mainboard/lenovo/t530/acpi/ec.asl M src/northbridge/intel/sandybridge/acpi/hostbridge.asl M src/northbridge/intel/sandybridge/acpi/peg.asl 19 files changed, 661 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/28380/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/28380 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I277808d6c1d8bd6e0a267a53f25471597698f8d5 Gerrit-Change-Number: 28380 Gerrit-PatchSet: 10 Gerrit-Owner: Evgeny Zinoviev <me(a)ch1p.com> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Name of user not set #1002090 Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: mainboard/lenovo/t410: Add new port
by Okashi Odayakana (Code Review) 06 Apr '19

06 Apr '19

Okashi Odayakana has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/11791 ) Change subject: mainboard/lenovo/t410: Add new port ...................................................................... Patch Set 12: Any new progress on this? Seems like a very interesting port potential. -- To view, visit https://review.coreboot.org/c/coreboot/+/11791 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id9d872e643dd242e925bfb46d18076e6ad100995 Gerrit-Change-Number: 11791 Gerrit-PatchSet: 12 Gerrit-Owner: Nicolas Reinecke <nr(a)das-labor.org> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nicolas Reinecke <nr(a)das-labor.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eloy Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Okashi Odayakana <brianblevins316(a)gmail.com> Gerrit-CC: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Comment-Date: Sat, 06 Apr 2019 00:56:32 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: device/dram: Remove set but unused variable
by Jacob Garber (Code Review) 06 Apr '19

06 Apr '19

Jacob Garber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32190 Change subject: device/dram: Remove set but unused variable ...................................................................... device/dram: Remove set but unused variable The `printram` function only expands to a value when a certain debug macro is defined. This isn't done in default builds, and so Clang (being ever so fastidious) flags `param` with -Werror=unused-but-set-variable. This inlines the value of `param` into the function call to prevent the error. Signed-off-by: Jacob Garber <jgarber1(a)ualberta.ca> Change-Id: I3da657e74723e7443c2ea9e7bd4142baa262d751 --- M src/device/dram/ddr3.c 1 file changed, 2 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/32190/1 diff --git a/src/device/dram/ddr3.c b/src/device/dram/ddr3.c index f27fdcb..e545b4d 100644 --- a/src/device/dram/ddr3.c +++ b/src/device/dram/ddr3.c @@ -136,7 +136,7 @@ u8 reg8; u32 mtb; /* medium time base */ u32 ftb; /* fine time base */ - unsigned int val, param; + unsigned int val; ret = SPD_STATUS_OK; @@ -173,8 +173,7 @@ printram(" Invalid number of memory banks\n"); ret = SPD_STATUS_INVALID_FIELD; } - param = 1 << (val + 3); - printram(" Banks : %u\n", param); + printram(" Banks : %u\n", 1 << (val + 3)); /* SDRAM capacity */ capacity_shift = reg8 & 0x0f; if (capacity_shift > 0x06) { -- To view, visit https://review.coreboot.org/c/coreboot/+/32190 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3da657e74723e7443c2ea9e7bd4142baa262d751 Gerrit-Change-Number: 32190 Gerrit-PatchSet: 1 Gerrit-Owner: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: libpayload: Align main() data types
by Patrick Georgi (Code Review) 06 Apr '19

06 Apr '19

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32183 Change subject: libpayload: Align main() data types ...................................................................... libpayload: Align main() data types One of many steps to compile with -Wconversion, as unsigned int and int aren't the same thing. BUG=b:111443775 BRANCH=none TEST=make junit.xml shows fewer warnings with -Wconversion enabled Change-Id: I9673ca70da32a1e5117b27fa89167e03379af9c1 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M payloads/libpayload/arch/arm/main.c M payloads/libpayload/arch/arm64/main.c M payloads/libpayload/arch/mips/main.c M payloads/libpayload/arch/x86/main.c 4 files changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/32183/1 diff --git a/payloads/libpayload/arch/arm/main.c b/payloads/libpayload/arch/arm/main.c index cb2d242..52c6162 100644 --- a/payloads/libpayload/arch/arm/main.c +++ b/payloads/libpayload/arch/arm/main.c @@ -30,7 +30,7 @@ #include <exception.h> #include <libpayload.h> -unsigned int main_argc; /**< The argc value to pass to main() */ +int main_argc; /**< The argc value to pass to main() */ /** The argv value to pass to main() */ char *main_argv[MAX_ARGC_COUNT]; diff --git a/payloads/libpayload/arch/arm64/main.c b/payloads/libpayload/arch/arm64/main.c index 593c40e..9a9ae96 100644 --- a/payloads/libpayload/arch/arm64/main.c +++ b/payloads/libpayload/arch/arm64/main.c @@ -31,7 +31,7 @@ #include <libpayload.h> #include <arch/mmu.h> -unsigned int main_argc; /**< The argc value to pass to main() */ +int main_argc; /**< The argc value to pass to main() */ /** The argv value to pass to main() */ char *main_argv[MAX_ARGC_COUNT]; diff --git a/payloads/libpayload/arch/mips/main.c b/payloads/libpayload/arch/mips/main.c index b8c0c4d..7a71f90 100644 --- a/payloads/libpayload/arch/mips/main.c +++ b/payloads/libpayload/arch/mips/main.c @@ -17,7 +17,7 @@ #include <libpayload.h> /* The argc value to pass to main() */ -unsigned int main_argc; +int main_argc; /* The argv value to pass to main() */ char *main_argv[MAX_ARGC_COUNT]; diff --git a/payloads/libpayload/arch/x86/main.c b/payloads/libpayload/arch/x86/main.c index 4da0bba..2e876f2 100644 --- a/payloads/libpayload/arch/x86/main.c +++ b/payloads/libpayload/arch/x86/main.c @@ -34,7 +34,7 @@ unsigned long loader_eax; /**< The value of EAX passed from the loader */ unsigned long loader_ebx; /**< The value of EBX passed from the loader */ -unsigned int main_argc; /**< The argc value to pass to main() */ +int main_argc; /**< The argc value to pass to main() */ /** The argv value to pass to main() */ char *main_argv[MAX_ARGC_COUNT]; -- To view, visit https://review.coreboot.org/c/coreboot/+/32183 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9673ca70da32a1e5117b27fa89167e03379af9c1 Gerrit-Change-Number: 32183 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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