Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31948
Change subject: mb/asrock/h110m: Add PEG Gen3 support ......................................................................
mb/asrock/h110m: Add PEG Gen3 support
This patch adds support PCIe Gen 3 with 8GT/s link speed for PEG x16 slot. All parameters for FSP are set during initialization in romstage. Now there is no need to additionally configure the FSP before building the ROM image.
Tested on Intel Core i5-6600 processor with the following devices: - LP11000e Fibre Channel HBA (Gen2 x8); - PEX8734 PCIe Fabric/Switch (Gen3 x16); - NVIDIA GeForce GTX 1060 GPU (Gen3 x16).
GPU works with an nouveau and proprietary driver under Ubuntu 18.04.2 (4.15.0-46-generic GNU/Linux kernel). Discrete graphic card is used as primary device for display output (if CONFIG_ONBOARD_VGA_IS_PRIMARY is not set). Dynamic switching is not yet supported.
Tianocore (edk2-stable201811-216-g51be9d0) is used as the payload.
Change-Id: Ia4f29df47d76de5069fe53120434cc7c2ab6f044 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/mainboard/asrock/h110m/devicetree.cb M src/mainboard/asrock/h110m/romstage.c 2 files changed, 27 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/31948/1
diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb index 9e2fca0..78e99f3 100644 --- a/src/mainboard/asrock/h110m/devicetree.cb +++ b/src/mainboard/asrock/h110m/devicetree.cb @@ -201,6 +201,13 @@ [PchSerialIoIndexUart2] = PchSerialIoDisabled, \ }"
+ # Use SRCCLKREQ0# and CLKSRC0 for PEG x16 root port + register "PcieRpClkReqSupport[0]" = "1" + register "PcieRpClkReqNumber[0]" = "0" + # Enable Latency Tolerance Reporting Mechanism + register "PcieRpLtrEnable[0]" = "1" + register "PcieRpClkSrcNumber[0]" = "0" + # Enable Root port 6(x1) for LAN. register "PcieRpEnable[5]" = "1" # Enable CLKREQ# diff --git a/src/mainboard/asrock/h110m/romstage.c b/src/mainboard/asrock/h110m/romstage.c index 4961a79..dacf47b 100644 --- a/src/mainboard/asrock/h110m/romstage.c +++ b/src/mainboard/asrock/h110m/romstage.c @@ -83,4 +83,24 @@
/* desktop type */ mem_cfg->UserBd = BOARD_TYPE_DESKTOP; + + /* initialize PEG 0:1:0 x16 Gen3 (8GT/s) root port */ + mupd->FspmConfig.Peg0Enable = 1; + mupd->FspmConfig.Peg0MaxLinkSpeed = 3; + + /* + * use Phase 2 Link Equalization for Gen3 Data Rate + * to minimize the BER (bit error rate) + */ + mupd->FspmTestConfig.Peg0Gen3EqPh2Enable = 1; + + /* + * Set primary display device + * default value: 3 (AUTO) + * 0: iGPU, 1: external GPU on PEG + */ + if(CONFIG(ONBOARD_VGA_IS_PRIMARY)) + mupd->FspmConfig.PrimaryDisplay = 0; + else + mupd->FspmConfig.PrimaryDisplay = 1; }
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31948 )
Change subject: mb/asrock/h110m: Add PEG Gen3 support ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/#/c/31948/1/src/mainboard/asrock/h110m/romstage.... File src/mainboard/asrock/h110m/romstage.c:
https://review.coreboot.org/#/c/31948/1/src/mainboard/asrock/h110m/romstage.... PS1, Line 102: if(CONFIG(ONBOARD_VGA_IS_PRIMARY)) space required before the open parenthesis '('
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31948 )
Change subject: mb/asrock/h110m: Add PEG Gen3 support ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/#/c/31948/2/src/mainboard/asrock/h110m/romstage.... File src/mainboard/asrock/h110m/romstage.c:
https://review.coreboot.org/#/c/31948/2/src/mainboard/asrock/h110m/romstage.... PS2, Line 102: if(CONFIG(ONBOARD_VGA_IS_PRIMARY)) space required before the open parenthesis '('
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/31948
to look at the new patch set (#3).
Change subject: mb/asrock/h110m: Add PEG Gen3 support ......................................................................
mb/asrock/h110m: Add PEG Gen3 support
This patch adds support PCIe Gen 3 with 8GT/s link speed for PEG x16 slot. All parameters for FSP are set during initialization in romstage. Now there is no need to additionally configure the FSP before building the ROM image.
Tested on Intel Core i5-6600 processor with the following devices: - LP11000e Fibre Channel HBA (Gen2 x8); - PEX8734 PCIe Fabric/Switch (Gen3 x16); - NVIDIA GeForce GTX 1060 GPU (Gen3 x16).
GPU works with an nouveau and proprietary driver under Ubuntu 18.04.2 (4.15.0-46-generic GNU/Linux kernel). Discrete graphic card is used as primary device for display output (if CONFIG_ONBOARD_VGA_IS_PRIMARY is not set). Dynamic switching is not yet supported.
Tianocore (edk2-stable201811-216-g51be9d0) is used as the payload.
Change-Id: Ia4f29df47d76de5069fe53120434cc7c2ab6f044 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/mainboard/asrock/h110m/devicetree.cb M src/mainboard/asrock/h110m/romstage.c 2 files changed, 27 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/31948/3
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31948 )
Change subject: mb/asrock/h110m: Add PEG Gen3 support ......................................................................
Patch Set 3:
(3 comments)
https://review.coreboot.org/#/c/31948/3/src/mainboard/asrock/h110m/romstage.... File src/mainboard/asrock/h110m/romstage.c:
https://review.coreboot.org/#/c/31948/3/src/mainboard/asrock/h110m/romstage.... PS3, Line 88: P that should be moved to soc/intel/... and check if the PCI device is enabled in devicetree.cb.
https://review.coreboot.org/#/c/31948/3/src/mainboard/asrock/h110m/romstage.... PS3, Line 89: mupd->FspmConfig.Peg0MaxLinkSpeed = 3; that could be read from devicetree.cb, too
https://review.coreboot.org/#/c/31948/3/src/mainboard/asrock/h110m/romstage.... PS3, Line 95: mupd->FspmTestConfig.Peg0Gen3EqPh2Enable = 1; that could be read from devicetree.cb, too
Hello Patrick Rudolph, Angel Pons, Paul Menzel, build bot (Jenkins), Patrick Georgi,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/31948
to look at the new patch set (#5).
Change subject: mb/asrock/h110m: Add PEG Gen3 support ......................................................................
mb/asrock/h110m: Add PEG Gen3 support
This patch adds support PCIe Gen 3 with 8GT/s link speed for PEG x16 slot. All parameters for FSP are set during initialization in romstage. Now there is no need to additionally configure the FSP before building the ROM image.
Tested on Intel Core i5-6600 processor with the following devices: - LP11000e Fibre Channel HBA (Gen2 x8); - PEX8734 PCIe Fabric/Switch (Gen3 x16); - NVIDIA GeForce GTX 1060 GPU (Gen3 x16).
GPU works with an nouveau and proprietary driver under Ubuntu 18.04.2 (4.15.0-46-generic GNU/Linux kernel). Discrete graphic card is used as primary device for display output (if CONFIG_ONBOARD_VGA_IS_PRIMARY is not set). Dynamic switching is not yet supported.
Tianocore (edk2-stable201811-216-g51be9d0) is used as the payload.
Change-Id: Ia4f29df47d76de5069fe53120434cc7c2ab6f044 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/mainboard/asrock/h110m/devicetree.cb 1 file changed, 13 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/31948/5
Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31948 )
Change subject: mb/asrock/h110m: Add PEG Gen3 support ......................................................................
Patch Set 5:
(3 comments)
https://review.coreboot.org/#/c/31948/3/src/mainboard/asrock/h110m/romstage.... File src/mainboard/asrock/h110m/romstage.c:
https://review.coreboot.org/#/c/31948/3/src/mainboard/asrock/h110m/romstage.... PS3, Line 88: P
that should be moved to soc/intel/... and check if the PCI device is enabled in devicetree.cb.
Done Change-Id: I23708f7060edf08739adf61fe61a419329907563
https://review.coreboot.org/#/c/31948/3/src/mainboard/asrock/h110m/romstage.... PS3, Line 89: mupd->FspmConfig.Peg0MaxLinkSpeed = 3;
that could be read from devicetree. […]
Done
https://review.coreboot.org/#/c/31948/3/src/mainboard/asrock/h110m/romstage.... PS3, Line 95: mupd->FspmTestConfig.Peg0Gen3EqPh2Enable = 1;
that could be read from devicetree. […]
Done
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31948 )
Change subject: mb/asrock/h110m: Add PEG Gen3 support ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/#/c/31948/5//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/31948/5//COMMIT_MSG@7 PS5, Line 7: mb/asrock/h110m: Add PEG Gen3 support Why is the primary display configuration changed in this change-set?
Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31948 )
Change subject: mb/asrock/h110m: Add PEG Gen3 support ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/#/c/31948/5//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/31948/5//COMMIT_MSG@7 PS5, Line 7: mb/asrock/h110m: Add PEG Gen3 support
Why is the primary display configuration changed in this change-set?
This is needed to use an external PEG graphics card. Otherwise,only iGPU will be used and I cannot test the NVIDIA card.
Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31948 )
Change subject: mb/asrock/h110m: Add PEG Gen3 support ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/#/c/31948/5//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/31948/5//COMMIT_MSG@7 PS5, Line 7: mb/asrock/h110m: Add PEG Gen3 support
This is needed to use an external PEG graphics card. […]
... use the NVIDIA card.
Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31948 )
Change subject: mb/asrock/h110m: Add PEG Gen3 support ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/#/c/31948/5//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/31948/5//COMMIT_MSG@7 PS5, Line 7: mb/asrock/h110m: Add PEG Gen3 support
... use the NVIDIA card.
I think that in this case a separate commit is not required.
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31948 )
Change subject: mb/asrock/h110m: Add PEG Gen3 support ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/#/c/31948/5//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/31948/5//COMMIT_MSG@7 PS5, Line 7: mb/asrock/h110m: Add PEG Gen3 support
I think that in this case a separate commit is not required.
So, if discrete card is not plugged in, the internal graphics card will still be used?
Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31948 )
Change subject: mb/asrock/h110m: Add PEG Gen3 support ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/#/c/31948/5//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/31948/5//COMMIT_MSG@7 PS5, Line 7: mb/asrock/h110m: Add PEG Gen3 support
So, if discrete card is not plugged in, the internal graphics card will still be used?
No If PrimaryDisplay = 1, the PEG GPU has a higher priority. However, if it is not plugged in, the FSP uses iGPU to display.
FSP initializes both devices. In theory, dynamic switching from linux should work (https://wiki.archlinux.org/index.php/PRIME). But I still can not use this feature. I need more time to research.
Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31948 )
Change subject: mb/asrock/h110m: Add PEG Gen3 support ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/#/c/31948/5//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/31948/5//COMMIT_MSG@7 PS5, Line 7: mb/asrock/h110m: Add PEG Gen3 support
No […]
I'm sorry, I did not understand the question. Yes, iGPU will be used.
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31948 )
Change subject: mb/asrock/h110m: Add PEG Gen3 support ......................................................................
Patch Set 5: Code-Review+1
(1 comment)
https://review.coreboot.org/#/c/31948/5//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/31948/5//COMMIT_MSG@7 PS5, Line 7: mb/asrock/h110m: Add PEG Gen3 support
I'm sorry, I did not understand the question. […]
Thank you for the clarification. That was not clear to me, and changing the primary display configuration won’t affect users without a discrete graphics card.
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31948 )
Change subject: mb/asrock/h110m: Add PEG Gen3 support ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/#/c/31948/5/src/mainboard/asrock/h110m/devicetre... File src/mainboard/asrock/h110m/devicetree.cb:
https://review.coreboot.org/#/c/31948/5/src/mainboard/asrock/h110m/devicetre... PS5, Line 210: # Use SRCCLKREQ0# and CLKSRC0 for PEG x16 root port : register "PcieRpClkReqSupport[0]" = "1" : register "PcieRpClkReqNumber[0]" = "0" : # Enable Latency Tolerance Reporting Mechanism : register "PcieRpLtrEnable[0]" = "1" : register "PcieRpClkSrcNumber[0]" = "0" : These settings are for the root ports at the PCH, AIUI.
Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31948 )
Change subject: mb/asrock/h110m: Add PEG Gen3 support ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/#/c/31948/5/src/mainboard/asrock/h110m/devicetre... File src/mainboard/asrock/h110m/devicetree.cb:
https://review.coreboot.org/#/c/31948/5/src/mainboard/asrock/h110m/devicetre... PS5, Line 210: # Use SRCCLKREQ0# and CLKSRC0 for PEG x16 root port : register "PcieRpClkReqSupport[0]" = "1" : register "PcieRpClkReqNumber[0]" = "0" : # Enable Latency Tolerance Reporting Mechanism : register "PcieRpLtrEnable[0]" = "1" : register "PcieRpClkSrcNumber[0]" = "0" :
These settings are for the root ports at the PCH, AIUI.
Yes you are right. Usually these parameters are used to configure PCH. But if we look at the description of these options:
https://github.com/IntelFsp/FSP/blob/master/KabylakeFspBinPkg/Include/FspsUp... https://github.com/IntelFsp/FSP/blob/master/KabylakeFspBinPkg/Include/FspsUp...
It says nothing about PCH. In addition, there are no similar parameters for PEG ports. I think FSP uses these options to initialize the PEG. In the case of this board, the PEG port uses the signals CLKOUT0 and CLKREQ0 from PCH. If I do not do these steps, then the PEG port training will be successful only by Gen1.
Hello Patrick Rudolph, Angel Pons, Paul Menzel, build bot (Jenkins), Patrick Georgi,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/31948
to look at the new patch set (#6).
Change subject: mb/asrock/h110m: Add PEG Gen3 support ......................................................................
mb/asrock/h110m: Add PEG Gen3 support
This patch adds support PCIe Gen 3 with 8GT/s link speed for PEG x16 slot. All parameters for FSP are set during initialization in romstage. Now there is no need to additionally configure the FSP before building the ROM image.
Tested on Intel Core i5-6600 processor with the following devices: - LP11000e Fibre Channel HBA (Gen2 x8); - PEX8734 PCIe Fabric/Switch (Gen3 x16); - NVIDIA GeForce GTX 1060 GPU (Gen3 x16).
GPU works with an nouveau and proprietary driver under Ubuntu 18.04.2 (4.15.0-46-generic GNU/Linux kernel). Discrete graphic card is used as primary device for display output (if CONFIG_ONBOARD_VGA_IS_PRIMARY is not set). Dynamic switching is not yet supported.
Tianocore (edk2-stable201811-216-g51be9d0) is used as the payload.
Change-Id: Ia4f29df47d76de5069fe53120434cc7c2ab6f044 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/mainboard/asrock/h110m/devicetree.cb 1 file changed, 8 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/31948/6
Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31948 )
Change subject: mb/asrock/h110m: Add PEG Gen3 support ......................................................................
Patch Set 8:
(2 comments)
https://review.coreboot.org/#/c/31948/5//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/31948/5//COMMIT_MSG@7 PS5, Line 7: mb/asrock/h110m: Add PEG Gen3 support
Thank you for the clarification. […]
I moved the setting of "PrimaryDisplay" to Change-Id: Ibed05fc9171e2bd73654f0da6273a8534746913d
https://review.coreboot.org/#/c/31948/5/src/mainboard/asrock/h110m/devicetre... File src/mainboard/asrock/h110m/devicetree.cb:
https://review.coreboot.org/#/c/31948/5/src/mainboard/asrock/h110m/devicetre... PS5, Line 210: # Use SRCCLKREQ0# and CLKSRC0 for PEG x16 root port : register "PcieRpClkReqSupport[0]" = "1" : register "PcieRpClkReqNumber[0]" = "0" : # Enable Latency Tolerance Reporting Mechanism : register "PcieRpLtrEnable[0]" = "1" : register "PcieRpClkSrcNumber[0]" = "0" :
Yes you are right. Usually these parameters are used to configure PCH. […]
Sorry, I did not notice the wrong strings:
# Enable Latency Tolerance Reporting Mechanism register "PcieRpLtrEnable[0]" = "1"
This should not be here. Removed it in the last patch.
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31948 )
Change subject: mb/asrock/h110m: Add PEG Gen3 support ......................................................................
Patch Set 8: Code-Review+2
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31948 )
Change subject: mb/asrock/h110m: Add PEG Gen3 support ......................................................................
Patch Set 9:
(1 comment)
https://review.coreboot.org/#/c/31948/5/src/mainboard/asrock/h110m/devicetre... File src/mainboard/asrock/h110m/devicetree.cb:
https://review.coreboot.org/#/c/31948/5/src/mainboard/asrock/h110m/devicetre... PS5, Line 210: # Use SRCCLKREQ0# and CLKSRC0 for PEG x16 root port : register "PcieRpClkReqSupport[0]" = "1" : register "PcieRpClkReqNumber[0]" = "0" : # Enable Latency Tolerance Reporting Mechanism : register "PcieRpLtrEnable[0]" = "1" : register "PcieRpClkSrcNumber[0]" = "0" :
Sorry, I did not notice the wrong strings: […]
I'm still convinced that this configures the PCH. 24 entries for 24 PCIe ports? I've no idea how to configure the clock source for the PEG... maybe they just missed it? FSP used to have only the options customers asked for.
Though, it's possible that this has side effects that make your PEG work, e.g. the PEG might use the PCH's clock source 0. I think it's worth a comment at least that this looks odd but makes it work.
Hello Patrick Rudolph, Angel Pons, Paul Menzel, build bot (Jenkins), Patrick Georgi,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/31948
to look at the new patch set (#10).
Change subject: mb/asrock/h110m: Add PEG Gen3 support ......................................................................
mb/asrock/h110m: Add PEG Gen3 support
This patch adds support PCIe Gen 3 with 8GT/s link speed for PEG x16 slot. All parameters for FSP are set during initialization in romstage. Now there is no need to additionally configure the FSP before building the ROM image.
Tested on Intel Core i5-6600 processor with the following devices: - LP11000e Fibre Channel HBA (Gen2 x8); - PEX8734 PCIe Fabric/Switch (Gen3 x16); - NVIDIA GeForce GTX 1060 GPU (Gen3 x16).
GPU works with an nouveau and proprietary driver under Ubuntu 18.04.2 (4.15.0-46-generic GNU/Linux kernel). Discrete graphic card is used as primary device for display output. Dynamic switching is not yet supported.
Tianocore (edk2-stable201811-216-g51be9d0) is used as the payload.
Change-Id: Ia4f29df47d76de5069fe53120434cc7c2ab6f044 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/mainboard/asrock/h110m/devicetree.cb 1 file changed, 8 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/31948/10
Hello Patrick Rudolph, Angel Pons, Paul Menzel, build bot (Jenkins), Patrick Georgi,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/31948
to look at the new patch set (#11).
Change subject: mb/asrock/h110m: Add PEG Gen3 support ......................................................................
mb/asrock/h110m: Add PEG Gen3 support
This patch adds support PCIe Gen 3 with 8GT/s link speed for PEG x16 slot. All parameters for FSP are set during initialization in romstage. Now there is no need to additionally configure the FSP before building the ROM image.
Tested on Intel Core i5-6600 processor with the following devices: - LP11000e Fibre Channel HBA (Gen2 x8); - PEX8734 PCIe Fabric/Switch (Gen3 x16); - NVIDIA GeForce GTX 1060 GPU (Gen3 x16).
GPU works with an nouveau and proprietary driver under Ubuntu 18.04.2 (4.15.0-46-generic GNU/Linux kernel). Discrete graphic card is used as primary device for display output. Dynamic switching is not yet supported.
Tianocore (edk2-stable201811-216-g51be9d0) is used as the payload.
Change-Id: Ia4f29df47d76de5069fe53120434cc7c2ab6f044 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/mainboard/asrock/h110m/devicetree.cb 1 file changed, 11 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/31948/11
Hello Patrick Rudolph, Angel Pons, Paul Menzel, build bot (Jenkins), Patrick Georgi,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/31948
to look at the new patch set (#12).
Change subject: mb/asrock/h110m: Add PEG Gen3 support ......................................................................
mb/asrock/h110m: Add PEG Gen3 support
This patch adds support PCIe Gen 3 with 8GT/s link speed for PEG x16 slot. All parameters for FSP are set during initialization in romstage. Now there is no need to additionally configure the FSP before building the ROM image.
Tested on Intel Core i5-6600 processor with the following devices: - LP11000e Fibre Channel HBA (Gen2 x8); - PEX8734 PCIe Fabric/Switch (Gen3 x16); - NVIDIA GeForce GTX 1060 GPU (Gen3 x16).
GPU works with an nouveau and proprietary driver under Ubuntu 18.04.2 (4.15.0-46-generic GNU/Linux kernel). Discrete graphic card is used as primary device for display output. Dynamic switching is not yet supported.
Tianocore (edk2-stable201811-216-g51be9d0) is used as the payload.
Change-Id: Ia4f29df47d76de5069fe53120434cc7c2ab6f044 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/mainboard/asrock/h110m/devicetree.cb 1 file changed, 11 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/31948/12
Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31948 )
Change subject: mb/asrock/h110m: Add PEG Gen3 support ......................................................................
Patch Set 12:
(1 comment)
https://review.coreboot.org/#/c/31948/5/src/mainboard/asrock/h110m/devicetre... File src/mainboard/asrock/h110m/devicetree.cb:
https://review.coreboot.org/#/c/31948/5/src/mainboard/asrock/h110m/devicetre... PS5, Line 210: # Use SRCCLKREQ0# and CLKSRC0 for PEG x16 root port : register "PcieRpClkReqSupport[0]" = "1" : register "PcieRpClkReqNumber[0]" = "0" : # Enable Latency Tolerance Reporting Mechanism : register "PcieRpLtrEnable[0]" = "1" : register "PcieRpClkSrcNumber[0]" = "0" :
I'm still convinced that this configures the PCH. 24 entries for 24 […]
I'm not sure, but fsp has the PegPhysicalSlotNumber[3] option for each PEG port. https://github.com/IntelFsp/FSP/blob/c0ec3d793facec1930b0ca227dbfe7943e1cad7...
Maybe this option overrides the PEG port number. By default, it has a value of 0. Maybe this means that PEG0 is used as PCH_PCIe[0] in "soc".
+ And I added a comment to this code.
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31948 )
Change subject: mb/asrock/h110m: Add PEG Gen3 support ......................................................................
Patch Set 12: Code-Review+1
(1 comment)
https://review.coreboot.org/#/c/31948/5/src/mainboard/asrock/h110m/devicetre... File src/mainboard/asrock/h110m/devicetree.cb:
https://review.coreboot.org/#/c/31948/5/src/mainboard/asrock/h110m/devicetre... PS5, Line 210: # Use SRCCLKREQ0# and CLKSRC0 for PEG x16 root port : register "PcieRpClkReqSupport[0]" = "1" : register "PcieRpClkReqNumber[0]" = "0" : # Enable Latency Tolerance Reporting Mechanism : register "PcieRpLtrEnable[0]" = "1" : register "PcieRpClkSrcNumber[0]" = "0" :
I'm not sure, but fsp has the PegPhysicalSlotNumber[3] option for each PEG port. […]
PegPhysicalSlotNumber is likely only used for SLOTCAP register.
PcieRpClkSrcNumber, PcieRpClkReqNumber and PcieRpClkReqSupport configure the PCIe clockgen, which is inside PCH. It's not directly related to PCIe ports on PCH.
Hello Patrick Rudolph, Angel Pons, Paul Menzel, build bot (Jenkins), Patrick Georgi,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/31948
to look at the new patch set (#13).
Change subject: mb/asrock/h110m: Add PEG Gen3 support ......................................................................
mb/asrock/h110m: Add PEG Gen3 support
This patch adds support PCIe Gen 3 with 8GT/s link speed for PEG x16 slot. All parameters for FSP are set during initialization in romstage. Now there is no need to additionally configure the FSP before building the ROM image.
Tested on Intel Core i5-6600 processor with the following devices: - LP11000e Fibre Channel HBA (Gen2 x8); - PEX8734 PCIe Fabric/Switch (Gen3 x16); - NVIDIA GeForce GTX 1060 GPU (Gen3 x16).
GPU works with an nouveau and proprietary driver under Ubuntu 18.04.2 (4.15.0-46-generic GNU/Linux kernel). Discrete graphic card is used as primary device for display output. Dynamic switching is not yet supported.
Tianocore (edk2-stable201811-216-g51be9d0) is used as the payload.
Change-Id: Ia4f29df47d76de5069fe53120434cc7c2ab6f044 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/mainboard/asrock/h110m/devicetree.cb 1 file changed, 8 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/31948/13
Hello Patrick Rudolph, Angel Pons, Paul Menzel, build bot (Jenkins), Patrick Georgi,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/31948
to look at the new patch set (#14).
Change subject: mb/asrock/h110m: Add PEG Gen3 support ......................................................................
mb/asrock/h110m: Add PEG Gen3 support
This patch adds support PCIe Gen 3 with 8GT/s link speed for PEG x16 slot. All parameters for FSP are set during initialization in romstage. Now there is no need to additionally configure the FSP before building the ROM image.
Tested on Intel Core i5-6600 processor with the following devices: - LP11000e Fibre Channel HBA (Gen2 x8); - PEX8734 PCIe Fabric/Switch (Gen3 x16); - NVIDIA GeForce GTX 1060 GPU (Gen3 x16).
GPU works with an nouveau and proprietary driver under Ubuntu 18.04.2 (4.15.0-46-generic GNU/Linux kernel). Discrete graphic card is used as primary device for display output. Dynamic switching is not yet supported.
Tianocore (edk2-stable201811-216-g51be9d0) is used as the payload.
Change-Id: Ia4f29df47d76de5069fe53120434cc7c2ab6f044 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/mainboard/asrock/h110m/devicetree.cb 1 file changed, 8 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/31948/14
Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31948 )
Change subject: mb/asrock/h110m: Add PEG Gen3 support ......................................................................
Patch Set 14:
(1 comment)
https://review.coreboot.org/#/c/31948/5/src/mainboard/asrock/h110m/devicetre... File src/mainboard/asrock/h110m/devicetree.cb:
https://review.coreboot.org/#/c/31948/5/src/mainboard/asrock/h110m/devicetre... PS5, Line 210: # Use SRCCLKREQ0# and CLKSRC0 for PEG x16 root port : register "PcieRpClkReqSupport[0]" = "1" : register "PcieRpClkReqNumber[0]" = "0" : # Enable Latency Tolerance Reporting Mechanism : register "PcieRpLtrEnable[0]" = "1" : register "PcieRpClkSrcNumber[0]" = "0" :
PegPhysicalSlotNumber is likely only used for SLOTCAP register. […]
Thank you for helping me understand this. + I updated the comment about this.
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31948 )
Change subject: mb/asrock/h110m: Add PEG Gen3 support ......................................................................
Patch Set 15: Code-Review+2
Nico Huber has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/31948 )
Change subject: mb/asrock/h110m: Add PEG Gen3 support ......................................................................
mb/asrock/h110m: Add PEG Gen3 support
This patch adds support PCIe Gen 3 with 8GT/s link speed for PEG x16 slot. All parameters for FSP are set during initialization in romstage. Now there is no need to additionally configure the FSP before building the ROM image.
Tested on Intel Core i5-6600 processor with the following devices: - LP11000e Fibre Channel HBA (Gen2 x8); - PEX8734 PCIe Fabric/Switch (Gen3 x16); - NVIDIA GeForce GTX 1060 GPU (Gen3 x16).
GPU works with an nouveau and proprietary driver under Ubuntu 18.04.2 (4.15.0-46-generic GNU/Linux kernel). Discrete graphic card is used as primary device for display output. Dynamic switching is not yet supported.
Tianocore (edk2-stable201811-216-g51be9d0) is used as the payload.
Change-Id: Ia4f29df47d76de5069fe53120434cc7c2ab6f044 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/31948 Reviewed-by: Nico Huber nico.h@gmx.de Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/asrock/h110m/devicetree.cb 1 file changed, 8 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved
diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb index b0756ca..e13076e 100644 --- a/src/mainboard/asrock/h110m/devicetree.cb +++ b/src/mainboard/asrock/h110m/devicetree.cb @@ -201,6 +201,14 @@ [PchSerialIoIndexUart2] = PchSerialIoDisabled, \ }"
+ # Set params for PEG 0:1:0 + register "Peg0MaxLinkWidth" = "Peg0_x16" + # Configure PCIe clockgen in PCH + # PEG0 uses SRCCLKREQ0 and CLKSRC0 + register "PcieRpClkReqSupport[0]" = "1" + register "PcieRpClkReqNumber[0]" = "0" + register "PcieRpClkSrcNumber[0]" = "0" + # Enable Root port 6(x1) for LAN. register "PcieRpEnable[5]" = "1" # Enable CLKREQ#