Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32045
Change subject: soc/intel/skylake: Add devicetree options for PEG ......................................................................
soc/intel/skylake: Add devicetree options for PEG
List of options for each port: - PegMaxLinkSpeed - PegMaxLinkWidth - PegPowerDownUnusedLanes - PegGen3EqPh2Enable
To enable or disable the corresponding PEG root port you need to add to the devicetree.cb:
device pci 01.0 on end # enable PEG0 root port device pci 01.1 off end # do not configure PEG1
If PEG port is not defined in the devicetree, it will be disabled in FSP.
Change-Id: I23708f7060edf08739adf61fe61a419329907563 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/soc/intel/skylake/Kconfig M src/soc/intel/skylake/chip.h M src/soc/intel/skylake/include/soc/pci_devs.h M src/soc/intel/skylake/romstage/romstage_fsp20.c 4 files changed, 100 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/32045/1
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 53094b1..de476ff 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -258,6 +258,10 @@ bool default n
+config MAX_PEG_PORTS + int + default 3 + config MAX_ROOT_PORTS int default 24 if PLATFORM_USES_FSP2_0 diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index a8ee064..1f0e2f4 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -214,6 +214,42 @@ */
/* + * PEG max link speed + * 0: Maximum possible link speed, + * which is set in FSP. + * 1: Gen1 link speed + * 2: Gen2 link speed + * 3: Gen3 link speed + */ + u8 PegMaxLinkSpeed[CONFIG_MAX_PEG_PORTS]; + + /* + * PEG Max Link Width + * 0: Maximum possible link width: + * x16 for PEG0, + * x8 for PEG1, + * x4 for PEG2. + * 1: x1 + * 2: x4, only for PEG0 and PEG1 + * 3: x8, only for PEG0 + */ + u8 PegMaxLinkWidth[CONFIG_MAX_PEG_PORTS]; + + /* + * Power down unused lanes on PEG + * 0: No power saving + * 1: Power down unused lanes + */ + u8 PegPowerDownUnusedLanes[CONFIG_MAX_PEG_PORTS]; + + /* + * Phase2 EQ enable on the PEG + * 0: Disable phase 2 + * 1: Enable phase 2 + */ + u8 PegGen3EqPh2Enable[CONFIG_MAX_PEG_PORTS]; + + /* * Enable/Disable Root Port * 0: Disable Root Port * 1: Enable Root Port diff --git a/src/soc/intel/skylake/include/soc/pci_devs.h b/src/soc/intel/skylake/include/soc/pci_devs.h index f695794..d59c800 100644 --- a/src/soc/intel/skylake/include/soc/pci_devs.h +++ b/src/soc/intel/skylake/include/soc/pci_devs.h @@ -37,6 +37,13 @@ #define SA_DEVFN_ROOT _SA_DEVFN(ROOT) #define SA_DEV_ROOT _SA_DEV(ROOT)
+#define SA_DEV_SLOT_PEG 0x01 +#define SA_DEVFN_PEG(func) PCI_DEVFN(SA_DEV_SLOT_PEG, func) +#define SA_DEV_PEG(func) dev_find_slot(0, SA_DEVFN_PEG(func)) +#define SA_DEV_PEG0 SA_DEV_PEG(0) +#define SA_DEV_PEG1 SA_DEV_PEG(1) +#define SA_DEV_PEG2 SA_DEV_PEG(2) + #define SA_DEV_SLOT_IGD 0x02 #define SA_DEVFN_IGD _SA_DEVFN(IGD) #define SA_DEV_IGD _SA_DEV(IGD) diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c index f38a775..b963d17 100644 --- a/src/soc/intel/skylake/romstage/romstage_fsp20.c +++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c @@ -202,6 +202,58 @@ m_cfg->CpuRatio = (flex_ratio.lo >> 8) & 0xff; }
+static void soc_peg_init_params(FSP_M_CONFIG *m_cfg, + FSP_M_TEST_CONFIG *m_t_cfg, + const struct soc_intel_skylake_config *config) +{ + const struct device *dev; + /* + * To enable or disable the corresponding PEG root port you need to + * add to the devicetree.cb: + * + * device pci 01.0 on end # enable PEG0 root port + * device pci 01.1 off end # do not configure PEG1 + * + * If PEG port is not defined in the device tree, it will be disabled + * in FSP + */ + dev = SA_DEV_PEG0; /* PEG 0:1:0 */ + if (!dev || !dev->enabled) + m_cfg->Peg0Enable = 0; + else if (dev->enabled) { + m_cfg->Peg0Enable = dev->enabled; + m_cfg->Peg0MaxLinkSpeed = config->PegMaxLinkSpeed[0]; + m_cfg->Peg0MaxLinkWidth = config->PegMaxLinkWidth[0]; + m_cfg->Peg0PowerDownUnusedLanes = + config->PegPowerDownUnusedLanes[0]; + m_t_cfg->Peg0Gen3EqPh2Enable = config->PegGen3EqPh2Enable[0]; + } + + dev = SA_DEV_PEG1; /* PEG 0:1:1 */ + if (!dev || !dev->enabled) + m_cfg->Peg1Enable = 0; + else if (dev->enabled) { + m_cfg->Peg1Enable = dev->enabled; + m_cfg->Peg1MaxLinkSpeed = config->PegMaxLinkSpeed[1]; + m_cfg->Peg1MaxLinkWidth = config->PegMaxLinkWidth[1]; + m_cfg->Peg1PowerDownUnusedLanes = + config->PegPowerDownUnusedLanes[1]; + m_t_cfg->Peg1Gen3EqPh2Enable = config->PegGen3EqPh2Enable[1]; + } + + dev = SA_DEV_PEG0; /* PEG 0:1:2 */ + if (!dev || !dev->enabled) + m_cfg->Peg2Enable = 0; + else if (dev->enabled) { + m_cfg->Peg2Enable = dev->enabled; + m_cfg->Peg2MaxLinkSpeed = config->PegMaxLinkSpeed[2]; + m_cfg->Peg2MaxLinkWidth = config->PegMaxLinkWidth[2]; + m_cfg->Peg2PowerDownUnusedLanes = + config->PegPowerDownUnusedLanes[2]; + m_t_cfg->Peg2Gen3EqPh2Enable = config->PegGen3EqPh2Enable[2]; + } +} + static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const struct soc_intel_skylake_config *config) { @@ -254,6 +306,7 @@ config = dev->chip_info;
soc_memory_init_params(m_cfg, config); + soc_peg_init_params(m_cfg, m_t_cfg, config);
/* Skip creating Management Engine MBP HOB */ m_t_cfg->SkipMbpHob = 0x01;
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32045 )
Change subject: soc/intel/skylake: Add devicetree options for PEG ......................................................................
Patch Set 1:
(3 comments)
Thanks for taking care of this.
https://review.coreboot.org/#/c/32045/1/src/soc/intel/skylake/Kconfig File src/soc/intel/skylake/Kconfig:
https://review.coreboot.org/#/c/32045/1/src/soc/intel/skylake/Kconfig@263 PS1, Line 263: default 3 Would this ever be something else? If not it could be a constant in the code.
https://review.coreboot.org/#/c/32045/1/src/soc/intel/skylake/romstage/romst... File src/soc/intel/skylake/romstage/romstage_fsp20.c:
https://review.coreboot.org/#/c/32045/1/src/soc/intel/skylake/romstage/romst... PS1, Line 253: m_t_cfg->Peg2Gen3EqPh2Enable = config->PegGen3EqPh2Enable[2]; What about `PegGen3EqPh3Method`? I wouldn't mind hard- coding it to `0` here. That's still better than not knowing what it's set to.
https://review.coreboot.org/#/c/32045/1/src/soc/intel/skylake/romstage/romst... PS1, Line 254: } Until somebody tells me something else, I consider every setting that differs from "Auto" as a workaround for a bug. So I wonder, why would we ever want the same overrides on all three ports?
Please elaborate what settings you need and what the defaults in the binary are. I would prefer as many reasonable hard-coded defaults as possible. Only when we really need a non-default, I'd add settings to `chip.h`.
Hello Patrick Rudolph, Angel Pons, Paul Menzel, build bot (Jenkins), Patrick Georgi,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32045
to look at the new patch set (#2).
Change subject: soc/intel/skylake: Set FSP options for PEG port ......................................................................
soc/intel/skylake: Set FSP options for PEG port
FSP options list (for each PEG port): - PegXEnable, - PegXMaxLinkWidth, - PegXMaxLinkSpeed, - PegXPowerDownUnusedLanes, - PegXGen3EqPh2Enable, - PegXGen3EqPh3Method.
Add PegMaxLinkWidth to chip.h. This option overrides the number of active lines from the devicetree.cb for each enabled PEG port (for example for boards that use x4 instead of x16 lines in PEG0). If the PegMaxLinkWidth is not defined, the port uses the maximum possible number of lines.
To enable or disable the corresponding PEG root port you need to add to the devicetree.cb:
device pci 01.0 on end # enable PEG0 root port device pci 01.1 off end # do not configure PEG1
If PEG port is not defined in the devicetree, it will be disabled in FSP.
It has been tested on ASRock H110M-DVS motherboard (Skylake i5-6600 CPU).
Change-Id: I23708f7060edf08739adf61fe61a419329907563 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/soc/intel/skylake/chip.h M src/soc/intel/skylake/include/soc/pci_devs.h M src/soc/intel/skylake/romstage/romstage_fsp20.c 3 files changed, 77 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/32045/2
Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32045 )
Change subject: soc/intel/skylake: Set FSP options for PEG port ......................................................................
Patch Set 4:
(4 comments)
https://review.coreboot.org/#/c/32045/1/src/soc/intel/skylake/Kconfig File src/soc/intel/skylake/Kconfig:
https://review.coreboot.org/#/c/32045/1/src/soc/intel/skylake/Kconfig@263 PS1, Line 263: default 3
Would this ever be something else? If not it could be a constant […]
I moved it to chip.h
https://review.coreboot.org/#/c/32045/1/src/soc/intel/skylake/romstage/romst... File src/soc/intel/skylake/romstage/romstage_fsp20.c:
https://review.coreboot.org/#/c/32045/1/src/soc/intel/skylake/romstage/romst... PS1, Line 244: dev = SA_DEV_PEG0; /* PEG 0:1:2 */ Fixed. SA_DEV_PEG2
https://review.coreboot.org/#/c/32045/1/src/soc/intel/skylake/romstage/romst... PS1, Line 253: m_t_cfg->Peg2Gen3EqPh2Enable = config->PegGen3EqPh2Enable[2];
What about `PegGen3EqPh3Method`? I wouldn't mind hard- […]
Added in the last patch-set as: m_t_cfg->Peg0Gen3EqPh3Method = 0; This is the default value for this parameter.
https://review.coreboot.org/#/c/32045/1/src/soc/intel/skylake/romstage/romst... PS1, Line 254: }
Until somebody tells me something else, I consider every […]
By default, PegEnable is set to 0x2 (Auto). in this case, the PEG port is not initialized. To enable it, you need PegEnable = 1 (Enable).
I don't know what "Auto" means. But I tested the board again with default parameters and it works well. The pcie eye diagram has not changed for PEG port.
Now I set form devicetree.cd only one option "Peg0MaxLinkWidth" to limit the number of active lines. This is used on boards to initialize PEG with a limited width of port, for example, from x16 to x4 for ASROCK-H110M-STX https://www.asrock.com/mb/Intel/H110M-STX/index.asp
"So I wonder, why would we ever want the same overrides on all three ports?" Some boards use all 3 ports (https://www.supermicro.com/products/motherboard/Xeon/C236_C232/X11SSH-F.cfm). The processor allows multiple PEGs to be used. See "PCI Express Configurations (Up to 1x16, 2x8, 1x8+2x4)" in https://ark.intel.com/content/www/us/en/ark/products/88188/intel-core-i5-660...
I think, in this case, it is also necessary to use the option "Peg0MaxLinkWidth" to limit PEG0 and give these lines PEG1.
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32045 )
Change subject: soc/intel/skylake: Set FSP options for PEG port ......................................................................
Patch Set 4: Code-Review+2
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32045 )
Change subject: soc/intel/skylake: Set FSP options for PEG port ......................................................................
Patch Set 5: Code-Review+2
(1 comment)
https://review.coreboot.org/#/c/32045/1/src/soc/intel/skylake/romstage/romst... File src/soc/intel/skylake/romstage/romstage_fsp20.c:
https://review.coreboot.org/#/c/32045/1/src/soc/intel/skylake/romstage/romst... PS1, Line 254: }
By default, PegEnable is set to 0x2 (Auto). in this case, the PEG port is not initialized. […]
Sorry, I misread the code. Got confused by the arrays.
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32045 )
Change subject: soc/intel/skylake: Set FSP options for PEG port ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/#/c/32045/5/src/soc/intel/skylake/chip.h File src/soc/intel/skylake/chip.h:
https://review.coreboot.org/#/c/32045/5/src/soc/intel/skylake/chip.h@226 PS5, Line 226: * 3: x8, only for PEG0 Though, you could turn the comment into an enum :)
Hello Patrick Rudolph, Angel Pons, Paul Menzel, build bot (Jenkins), Nico Huber, Patrick Georgi,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32045
to look at the new patch set (#7).
Change subject: soc/intel/skylake: Set FSP options for PEG port ......................................................................
soc/intel/skylake: Set FSP options for PEG port
FSP options list (for each PEG port): - PegXEnable, - PegXMaxLinkWidth, - PegXMaxLinkSpeed, - PegXPowerDownUnusedLanes, - PegXGen3EqPh2Enable, - PegXGen3EqPh3Method.
Add PegMaxLinkWidth to chip.h. This option overrides the number of active lines from the devicetree.cb for each enabled PEG port (for example for boards that use x4 instead of x16 lines in PEG0). If the PegMaxLinkWidth is not defined, the port uses the maximum possible number of lines.
To enable or disable the corresponding PEG root port you need to add to the devicetree.cb:
device pci 01.0 on end # enable PEG0 root port device pci 01.1 off end # do not configure PEG1
If PEG port is not defined in the devicetree, it will be disabled in FSP.
It has been tested on ASRock H110M-DVS motherboard (Skylake i5-6600 CPU).
Change-Id: I23708f7060edf08739adf61fe61a419329907563 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/soc/intel/skylake/chip.h M src/soc/intel/skylake/include/soc/pci_devs.h M src/soc/intel/skylake/romstage/romstage_fsp20.c 3 files changed, 84 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/32045/7
Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32045 )
Change subject: soc/intel/skylake: Set FSP options for PEG port ......................................................................
Patch Set 7:
(1 comment)
https://review.coreboot.org/#/c/32045/5/src/soc/intel/skylake/chip.h File src/soc/intel/skylake/chip.h:
https://review.coreboot.org/#/c/32045/5/src/soc/intel/skylake/chip.h@226 PS5, Line 226: * 3: x8, only for PEG0
Though, you could turn the comment into an enum :)
I added enum. Thanks :)
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32045 )
Change subject: soc/intel/skylake: Set FSP options for PEG port ......................................................................
Patch Set 7: Code-Review+2
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32045 )
Change subject: soc/intel/skylake: Set FSP options for PEG port ......................................................................
Patch Set 9:
(1 comment)
https://review.coreboot.org/#/c/32045/9/src/soc/intel/skylake/chip.h File src/soc/intel/skylake/chip.h:
https://review.coreboot.org/#/c/32045/9/src/soc/intel/skylake/chip.h@235 PS9, Line 235: } Peg2MaxLinkWidth; Maybe I'm looking at the wrong header file, but I see the same mapping for all ports only that the latter have less options. e.g.
PEG_Max, PEG_x1, PEG_x2, PEG_x4, PEG_x8,
Ah, well, I realize now that's about the same, just x2 seems to be missing here?
Hello Patrick Rudolph, Angel Pons, Paul Menzel, build bot (Jenkins), Nico Huber, Patrick Georgi,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32045
to look at the new patch set (#10).
Change subject: soc/intel/skylake: Set FSP options for PEG port ......................................................................
soc/intel/skylake: Set FSP options for PEG port
FSP options list (for each PEG port): - PegXEnable, - PegXMaxLinkWidth, - PegXMaxLinkSpeed, - PegXPowerDownUnusedLanes, - PegXGen3EqPh2Enable, - PegXGen3EqPh3Method.
Add PegMaxLinkWidth to chip.h. This option overrides the number of active lines from the devicetree.cb for each enabled PEG port (for example for boards that use x4 instead of x16 lines in PEG0). If the PegMaxLinkWidth is not defined, the port uses the maximum possible number of lines.
To enable or disable the corresponding PEG root port you need to add to the devicetree.cb:
device pci 01.0 on end # enable PEG0 root port device pci 01.1 off end # do not configure PEG1
If PEG port is not defined in the devicetree, it will be disabled in FSP.
It has been tested on ASRock H110M-DVS motherboard (Skylake i5-6600 CPU).
Change-Id: I23708f7060edf08739adf61fe61a419329907563 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/soc/intel/skylake/chip.h M src/soc/intel/skylake/include/soc/pci_devs.h M src/soc/intel/skylake/romstage/romstage_fsp20.c 3 files changed, 87 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/32045/10
Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32045 )
Change subject: soc/intel/skylake: Set FSP options for PEG port ......................................................................
Patch Set 10:
(1 comment)
https://review.coreboot.org/#/c/32045/9/src/soc/intel/skylake/chip.h File src/soc/intel/skylake/chip.h:
https://review.coreboot.org/#/c/32045/9/src/soc/intel/skylake/chip.h@235 PS9, Line 235: } Peg2MaxLinkWidth;
Maybe I'm looking at the wrong header file, but I see the same mapping […]
Sorry. Add x2. Fixed
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32045 )
Change subject: soc/intel/skylake: Set FSP options for PEG port ......................................................................
Patch Set 10: Code-Review+2
Nico Huber has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/32045 )
Change subject: soc/intel/skylake: Set FSP options for PEG port ......................................................................
soc/intel/skylake: Set FSP options for PEG port
FSP options list (for each PEG port): - PegXEnable, - PegXMaxLinkWidth, - PegXMaxLinkSpeed, - PegXPowerDownUnusedLanes, - PegXGen3EqPh2Enable, - PegXGen3EqPh3Method.
Add PegMaxLinkWidth to chip.h. This option overrides the number of active lines from the devicetree.cb for each enabled PEG port (for example for boards that use x4 instead of x16 lines in PEG0). If the PegMaxLinkWidth is not defined, the port uses the maximum possible number of lines.
To enable or disable the corresponding PEG root port you need to add to the devicetree.cb:
device pci 01.0 on end # enable PEG0 root port device pci 01.1 off end # do not configure PEG1
If PEG port is not defined in the devicetree, it will be disabled in FSP.
It has been tested on ASRock H110M-DVS motherboard (Skylake i5-6600 CPU).
Change-Id: I23708f7060edf08739adf61fe61a419329907563 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/32045 Reviewed-by: Nico Huber nico.h@gmx.de Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/skylake/chip.h M src/soc/intel/skylake/include/soc/pci_devs.h M src/soc/intel/skylake/romstage/romstage_fsp20.c 3 files changed, 87 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index a9b8641..57d51e7 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -35,6 +35,8 @@ #include <soc/usb.h> #include <soc/vr_config.h>
+#define MAX_PEG_PORTS 3 + enum skylake_i2c_voltage { I2C_VOLTAGE_3V3, I2C_VOLTAGE_1V8 @@ -213,6 +215,28 @@ * respective PCIe root port. */
+ /* PEG Max Link Width */ + enum { + Peg0_x16, + Peg0_x1, + Peg0_x2, + Peg0_x4, + Peg0_x8, + } Peg0MaxLinkWidth; + + enum { + Peg1_x8, + Peg1_x1, + Peg1_x2, + Peg1_x4, + } Peg1MaxLinkWidth; + + enum { + Peg2_x4, + Peg2_x1, + Peg2_x2, + } Peg2MaxLinkWidth; + /* * Enable/Disable Root Port * 0: Disable Root Port diff --git a/src/soc/intel/skylake/include/soc/pci_devs.h b/src/soc/intel/skylake/include/soc/pci_devs.h index f695794..d59c800 100644 --- a/src/soc/intel/skylake/include/soc/pci_devs.h +++ b/src/soc/intel/skylake/include/soc/pci_devs.h @@ -37,6 +37,13 @@ #define SA_DEVFN_ROOT _SA_DEVFN(ROOT) #define SA_DEV_ROOT _SA_DEV(ROOT)
+#define SA_DEV_SLOT_PEG 0x01 +#define SA_DEVFN_PEG(func) PCI_DEVFN(SA_DEV_SLOT_PEG, func) +#define SA_DEV_PEG(func) dev_find_slot(0, SA_DEVFN_PEG(func)) +#define SA_DEV_PEG0 SA_DEV_PEG(0) +#define SA_DEV_PEG1 SA_DEV_PEG(1) +#define SA_DEV_PEG2 SA_DEV_PEG(2) + #define SA_DEV_SLOT_IGD 0x02 #define SA_DEVFN_IGD _SA_DEVFN(IGD) #define SA_DEV_IGD _SA_DEV(IGD) diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c index b65c9ff..d9b2706 100644 --- a/src/soc/intel/skylake/romstage/romstage_fsp20.c +++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c @@ -202,6 +202,61 @@ m_cfg->CpuRatio = (flex_ratio.lo >> 8) & 0xff; }
+static void soc_peg_init_params(FSP_M_CONFIG *m_cfg, + FSP_M_TEST_CONFIG *m_t_cfg, + const struct soc_intel_skylake_config *config) +{ + const struct device *dev; + /* + * To enable or disable the corresponding PEG root port you need to + * add to the devicetree.cb: + * + * device pci 01.0 on end # enable PEG0 root port + * device pci 01.1 off end # do not configure PEG1 + * + * If PEG port is not defined in the device tree, it will be disabled + * in FSP + */ + dev = SA_DEV_PEG0; /* PEG 0:1:0 */ + if (!dev || !dev->enabled) + m_cfg->Peg0Enable = 0; + else if (dev->enabled) { + m_cfg->Peg0Enable = dev->enabled; + m_cfg->Peg0MaxLinkWidth = config->Peg0MaxLinkWidth; + /* Use maximum possible link speed */ + m_cfg->Peg0MaxLinkSpeed = 0; + /* Power down unused lanes based on the max possible width */ + m_cfg->Peg0PowerDownUnusedLanes = 1; + /* Set [Auto] for options to enable equalization methods */ + m_t_cfg->Peg0Gen3EqPh2Enable = 2; + m_t_cfg->Peg0Gen3EqPh3Method = 0; + } + + dev = SA_DEV_PEG1; /* PEG 0:1:1 */ + if (!dev || !dev->enabled) + m_cfg->Peg1Enable = 0; + else if (dev->enabled) { + m_cfg->Peg1Enable = dev->enabled; + m_cfg->Peg1MaxLinkWidth = config->Peg1MaxLinkWidth; + m_cfg->Peg1MaxLinkSpeed = 0; + m_cfg->Peg1PowerDownUnusedLanes = 1; + m_t_cfg->Peg1Gen3EqPh2Enable = 2; + m_t_cfg->Peg1Gen3EqPh3Method = 0; + } + + dev = SA_DEV_PEG2; /* PEG 0:1:2 */ + if (!dev || !dev->enabled) + m_cfg->Peg2Enable = 0; + else if (dev->enabled) { + m_cfg->Peg2Enable = dev->enabled; + m_cfg->Peg2MaxLinkWidth = config->Peg2MaxLinkWidth; + m_cfg->Peg2MaxLinkSpeed = 0; + m_cfg->Peg2PowerDownUnusedLanes = 1; + m_t_cfg->Peg2Gen3EqPh2Enable = 2; + m_t_cfg->Peg2Gen3EqPh3Method = 0; + } +} + static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const struct soc_intel_skylake_config *config) { @@ -276,6 +331,7 @@ config = dev->chip_info;
soc_memory_init_params(m_cfg, config); + soc_peg_init_params(m_cfg, m_t_cfg, config);
/* Skip creating Management Engine MBP HOB */ m_t_cfg->SkipMbpHob = 0x01;
-
Maxim Polyakov (Code Review) -
Nico Huber (Code Review)
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Patrick Rudolph (Code Review)