4 comments:
File src/soc/intel/skylake/Kconfig:
Patch Set #1, Line 263: default 3
Would this ever be something else? If not it could be a constant […]
I moved it to chip.h
File src/soc/intel/skylake/romstage/romstage_fsp20.c:
Patch Set #1, Line 244: dev = SA_DEV_PEG0; /* PEG 0:1:2 */
Fixed.
SA_DEV_PEG2
Patch Set #1, Line 253: m_t_cfg->Peg2Gen3EqPh2Enable = config->PegGen3EqPh2Enable[2];
What about `PegGen3EqPh3Method`? I wouldn't mind hard- […]
Added in the last patch-set as:
m_t_cfg->Peg0Gen3EqPh3Method = 0;
This is the default value for this parameter.
Until somebody tells me something else, I consider every […]
By default, PegEnable is set to 0x2 (Auto). in this case, the PEG port is not initialized. To enable it, you need PegEnable = 1 (Enable).
I don't know what "Auto" means. But I tested the board again with default parameters and it works well. The pcie eye diagram has not changed for PEG port.
Now I set form devicetree.cd only one option "Peg0MaxLinkWidth" to limit the number of active lines. This is used on boards to initialize PEG with a limited width of port, for example, from x16 to x4 for ASROCK-H110M-STX https://www.asrock.com/mb/Intel/H110M-STX/index.asp
"So I wonder, why would we ever want the same overrides on all three ports?"
Some boards use all 3 ports (https://www.supermicro.com/products/motherboard/Xeon/C236_C232/X11SSH-F.cfm). The processor allows multiple PEGs to be used. See "PCI Express Configurations (Up to 1x16, 2x8, 1x8+2x4)" in https://ark.intel.com/content/www/us/en/ark/products/88188/intel-core-i5-6600-processor-6m-cache-up-to-3-90-ghz.html
I think, in this case, it is also necessary to use the option "Peg0MaxLinkWidth" to limit PEG0 and give these lines PEG1.
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