Nico Huber merged this change.
soc/intel/skylake: Set FSP options for PEG port
FSP options list (for each PEG port):
- PegXEnable,
- PegXMaxLinkWidth,
- PegXMaxLinkSpeed,
- PegXPowerDownUnusedLanes,
- PegXGen3EqPh2Enable,
- PegXGen3EqPh3Method.
Add PegMaxLinkWidth to chip.h. This option overrides the number of
active lines from the devicetree.cb for each enabled PEG port (for
example for boards that use x4 instead of x16 lines in PEG0). If the
PegMaxLinkWidth is not defined, the port uses the maximum possible
number of lines.
To enable or disable the corresponding PEG root port you need to add
to the devicetree.cb:
device pci 01.0 on end # enable PEG0 root port
device pci 01.1 off end # do not configure PEG1
If PEG port is not defined in the devicetree, it will be disabled in
FSP.
It has been tested on ASRock H110M-DVS motherboard (Skylake i5-6600
CPU).
Change-Id: I23708f7060edf08739adf61fe61a419329907563
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32045
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
M src/soc/intel/skylake/chip.h
M src/soc/intel/skylake/include/soc/pci_devs.h
M src/soc/intel/skylake/romstage/romstage_fsp20.c
3 files changed, 87 insertions(+), 0 deletions(-)
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h
index a9b8641..57d51e7 100644
--- a/src/soc/intel/skylake/chip.h
+++ b/src/soc/intel/skylake/chip.h
@@ -35,6 +35,8 @@
#include <soc/usb.h>
#include <soc/vr_config.h>
+#define MAX_PEG_PORTS 3
+
enum skylake_i2c_voltage {
I2C_VOLTAGE_3V3,
I2C_VOLTAGE_1V8
@@ -213,6 +215,28 @@
* respective PCIe root port.
*/
+ /* PEG Max Link Width */
+ enum {
+ Peg0_x16,
+ Peg0_x1,
+ Peg0_x2,
+ Peg0_x4,
+ Peg0_x8,
+ } Peg0MaxLinkWidth;
+
+ enum {
+ Peg1_x8,
+ Peg1_x1,
+ Peg1_x2,
+ Peg1_x4,
+ } Peg1MaxLinkWidth;
+
+ enum {
+ Peg2_x4,
+ Peg2_x1,
+ Peg2_x2,
+ } Peg2MaxLinkWidth;
+
/*
* Enable/Disable Root Port
* 0: Disable Root Port
diff --git a/src/soc/intel/skylake/include/soc/pci_devs.h b/src/soc/intel/skylake/include/soc/pci_devs.h
index f695794..d59c800 100644
--- a/src/soc/intel/skylake/include/soc/pci_devs.h
+++ b/src/soc/intel/skylake/include/soc/pci_devs.h
@@ -37,6 +37,13 @@
#define SA_DEVFN_ROOT _SA_DEVFN(ROOT)
#define SA_DEV_ROOT _SA_DEV(ROOT)
+#define SA_DEV_SLOT_PEG 0x01
+#define SA_DEVFN_PEG(func) PCI_DEVFN(SA_DEV_SLOT_PEG, func)
+#define SA_DEV_PEG(func) dev_find_slot(0, SA_DEVFN_PEG(func))
+#define SA_DEV_PEG0 SA_DEV_PEG(0)
+#define SA_DEV_PEG1 SA_DEV_PEG(1)
+#define SA_DEV_PEG2 SA_DEV_PEG(2)
+
#define SA_DEV_SLOT_IGD 0x02
#define SA_DEVFN_IGD _SA_DEVFN(IGD)
#define SA_DEV_IGD _SA_DEV(IGD)
diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c
index b65c9ff..d9b2706 100644
--- a/src/soc/intel/skylake/romstage/romstage_fsp20.c
+++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c
@@ -202,6 +202,61 @@
m_cfg->CpuRatio = (flex_ratio.lo >> 8) & 0xff;
}
+static void soc_peg_init_params(FSP_M_CONFIG *m_cfg,
+ FSP_M_TEST_CONFIG *m_t_cfg,
+ const struct soc_intel_skylake_config *config)
+{
+ const struct device *dev;
+ /*
+ * To enable or disable the corresponding PEG root port you need to
+ * add to the devicetree.cb:
+ *
+ * device pci 01.0 on end # enable PEG0 root port
+ * device pci 01.1 off end # do not configure PEG1
+ *
+ * If PEG port is not defined in the device tree, it will be disabled
+ * in FSP
+ */
+ dev = SA_DEV_PEG0; /* PEG 0:1:0 */
+ if (!dev || !dev->enabled)
+ m_cfg->Peg0Enable = 0;
+ else if (dev->enabled) {
+ m_cfg->Peg0Enable = dev->enabled;
+ m_cfg->Peg0MaxLinkWidth = config->Peg0MaxLinkWidth;
+ /* Use maximum possible link speed */
+ m_cfg->Peg0MaxLinkSpeed = 0;
+ /* Power down unused lanes based on the max possible width */
+ m_cfg->Peg0PowerDownUnusedLanes = 1;
+ /* Set [Auto] for options to enable equalization methods */
+ m_t_cfg->Peg0Gen3EqPh2Enable = 2;
+ m_t_cfg->Peg0Gen3EqPh3Method = 0;
+ }
+
+ dev = SA_DEV_PEG1; /* PEG 0:1:1 */
+ if (!dev || !dev->enabled)
+ m_cfg->Peg1Enable = 0;
+ else if (dev->enabled) {
+ m_cfg->Peg1Enable = dev->enabled;
+ m_cfg->Peg1MaxLinkWidth = config->Peg1MaxLinkWidth;
+ m_cfg->Peg1MaxLinkSpeed = 0;
+ m_cfg->Peg1PowerDownUnusedLanes = 1;
+ m_t_cfg->Peg1Gen3EqPh2Enable = 2;
+ m_t_cfg->Peg1Gen3EqPh3Method = 0;
+ }
+
+ dev = SA_DEV_PEG2; /* PEG 0:1:2 */
+ if (!dev || !dev->enabled)
+ m_cfg->Peg2Enable = 0;
+ else if (dev->enabled) {
+ m_cfg->Peg2Enable = dev->enabled;
+ m_cfg->Peg2MaxLinkWidth = config->Peg2MaxLinkWidth;
+ m_cfg->Peg2MaxLinkSpeed = 0;
+ m_cfg->Peg2PowerDownUnusedLanes = 1;
+ m_t_cfg->Peg2Gen3EqPh2Enable = 2;
+ m_t_cfg->Peg2Gen3EqPh3Method = 0;
+ }
+}
+
static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
const struct soc_intel_skylake_config *config)
{
@@ -276,6 +331,7 @@
config = dev->chip_info;
soc_memory_init_params(m_cfg, config);
+ soc_peg_init_params(m_cfg, m_t_cfg, config);
/* Skip creating Management Engine MBP HOB */
m_t_cfg->SkipMbpHob = 0x01;
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