Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32045 )
Change subject: soc/intel/skylake: Set FSP options for PEG port
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Patch Set 5: Code-Review+2
(1 comment)
https://review.coreboot.org/#/c/32045/1/src/soc/intel/skylake/romstage/romst...
File src/soc/intel/skylake/romstage/romstage_fsp20.c:
https://review.coreboot.org/#/c/32045/1/src/soc/intel/skylake/romstage/romst...
PS1, Line 254: }
By default, PegEnable is set to 0x2 (Auto). in this case, the PEG port is not initialized. […]
Sorry, I misread the code. Got confused by the arrays.
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