Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32045 )
Change subject: soc/intel/skylake: Set FSP options for PEG port
......................................................................
Patch Set 9:
(1 comment)
https://review.coreboot.org/#/c/32045/9/src/soc/intel/skylake/chip.h
File src/soc/intel/skylake/chip.h:
https://review.coreboot.org/#/c/32045/9/src/soc/intel/skylake/chip.h@235
PS9, Line 235: } Peg2MaxLinkWidth;
Maybe I'm looking at the wrong header file, but I see the same mapping
for all ports only that the latter have less options. e.g.
PEG_Max,
PEG_x1,
PEG_x2,
PEG_x4,
PEG_x8,
Ah, well, I realize now that's about the same, just x2 seems to be
missing here?
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