Patch set 12:Code-Review +1
1 comment:
File src/mainboard/asrock/h110m/devicetree.cb:
# Use SRCCLKREQ0# and CLKSRC0 for PEG x16 root port
register "PcieRpClkReqSupport[0]" = "1"
register "PcieRpClkReqNumber[0]" = "0"
# Enable Latency Tolerance Reporting Mechanism
register "PcieRpLtrEnable[0]" = "1"
register "PcieRpClkSrcNumber[0]" = "0"
I'm not sure, but fsp has the PegPhysicalSlotNumber[3] option for each PEG port. […]
PegPhysicalSlotNumber is likely only used for SLOTCAP register.
PcieRpClkSrcNumber, PcieRpClkReqNumber and PcieRpClkReqSupport configure the PCIe clockgen, which is inside PCH. It's not directly related to PCIe ports on PCH.
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