Maxim Polyakov has uploaded this change for review.
mb/asrock/h110m: Add PEG Gen3 support
This patch adds support PCIe Gen 3 with 8GT/s link speed for PEG x16
slot. All parameters for FSP are set during initialization in
romstage. Now there is no need to additionally configure the FSP
before building the ROM image.
Tested on Intel Core i5-6600 processor with the following devices:
- LP11000e Fibre Channel HBA (Gen2 x8);
- PEX8734 PCIe Fabric/Switch (Gen3 x16);
- NVIDIA GeForce GTX 1060 GPU (Gen3 x16).
GPU works with an nouveau and proprietary driver under Ubuntu 18.04.2
(4.15.0-46-generic GNU/Linux kernel). Discrete graphic card is used as
primary device for display output (if CONFIG_ONBOARD_VGA_IS_PRIMARY is
not set). Dynamic switching is not yet supported.
Tianocore (edk2-stable201811-216-g51be9d0) is used as the payload.
Change-Id: Ia4f29df47d76de5069fe53120434cc7c2ab6f044
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
---
M src/mainboard/asrock/h110m/devicetree.cb
M src/mainboard/asrock/h110m/romstage.c
2 files changed, 27 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/31948/1
diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb
index 9e2fca0..78e99f3 100644
--- a/src/mainboard/asrock/h110m/devicetree.cb
+++ b/src/mainboard/asrock/h110m/devicetree.cb
@@ -201,6 +201,13 @@
[PchSerialIoIndexUart2] = PchSerialIoDisabled, \
}"
+ # Use SRCCLKREQ0# and CLKSRC0 for PEG x16 root port
+ register "PcieRpClkReqSupport[0]" = "1"
+ register "PcieRpClkReqNumber[0]" = "0"
+ # Enable Latency Tolerance Reporting Mechanism
+ register "PcieRpLtrEnable[0]" = "1"
+ register "PcieRpClkSrcNumber[0]" = "0"
+
# Enable Root port 6(x1) for LAN.
register "PcieRpEnable[5]" = "1"
# Enable CLKREQ#
diff --git a/src/mainboard/asrock/h110m/romstage.c b/src/mainboard/asrock/h110m/romstage.c
index 4961a79..dacf47b 100644
--- a/src/mainboard/asrock/h110m/romstage.c
+++ b/src/mainboard/asrock/h110m/romstage.c
@@ -83,4 +83,24 @@
/* desktop type */
mem_cfg->UserBd = BOARD_TYPE_DESKTOP;
+
+ /* initialize PEG 0:1:0 x16 Gen3 (8GT/s) root port */
+ mupd->FspmConfig.Peg0Enable = 1;
+ mupd->FspmConfig.Peg0MaxLinkSpeed = 3;
+
+ /*
+ * use Phase 2 Link Equalization for Gen3 Data Rate
+ * to minimize the BER (bit error rate)
+ */
+ mupd->FspmTestConfig.Peg0Gen3EqPh2Enable = 1;
+
+ /*
+ * Set primary display device
+ * default value: 3 (AUTO)
+ * 0: iGPU, 1: external GPU on PEG
+ */
+ if(CONFIG(ONBOARD_VGA_IS_PRIMARY))
+ mupd->FspmConfig.PrimaryDisplay = 0;
+ else
+ mupd->FspmConfig.PrimaryDisplay = 1;
}
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