Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31948 )
Change subject: mb/asrock/h110m: Add PEG Gen3 support ......................................................................
Patch Set 9:
(1 comment)
https://review.coreboot.org/#/c/31948/5/src/mainboard/asrock/h110m/devicetre... File src/mainboard/asrock/h110m/devicetree.cb:
https://review.coreboot.org/#/c/31948/5/src/mainboard/asrock/h110m/devicetre... PS5, Line 210: # Use SRCCLKREQ0# and CLKSRC0 for PEG x16 root port : register "PcieRpClkReqSupport[0]" = "1" : register "PcieRpClkReqNumber[0]" = "0" : # Enable Latency Tolerance Reporting Mechanism : register "PcieRpLtrEnable[0]" = "1" : register "PcieRpClkSrcNumber[0]" = "0" :
Sorry, I did not notice the wrong strings: […]
I'm still convinced that this configures the PCH. 24 entries for 24 PCIe ports? I've no idea how to configure the clock source for the PEG... maybe they just missed it? FSP used to have only the options customers asked for.
Though, it's possible that this has side effects that make your PEG work, e.g. the PEG might use the PCH's clock source 0. I think it's worth a comment at least that this looks odd but makes it work.